Reliable link management for high-speed signaling interconnects

Abstract

The present disclosure relates to reliable link management for high-speed signaling interconnects. A system includes a link having one or more lanes associated with transmitting data and one or more lanes associated with transmitting a clock signal. The system includes a device coupled with the link that receives a signal over the one or more lanes associated with transmitting the clock signal and determines a number of pulses associated with the signal within a time period. The device is further to determine that the number of pulses associated with the signal fails to satisfy a predetermined condition related to a specified number of pulses within the time period and initiate a power down sequence in response to determining that the number of pulses fails to satisfy the predetermined condition related to the specified number of pulses within the time period.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 294,029, filed December 27, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] At least one embodiment relates to processing resources for performing and facilitating high-speed communication. For example, at least one embodiment relates to a reliable link management technique for ground-referenced signaling (GRS) interconnects. Background Technology

[0004] Communication systems transmit signals from a transmitter to a receiver via communication channels or media (e.g., cables, printed circuit boards, links, wireless methods, etc.). For example, a communication channel can communicate signals between devices or chips—e.g., a chip-to-chip (C2C) system. In some communication systems, the communication channel on one of the devices or chips can be powered down or reset via a corresponding software stack to implement fault containment or controlled shutdown operations. Each chip can use a different software stack, so the corresponding software stack of a power-down or reset device cannot communicate with another chip. Furthermore, due to the security specifications of the communication system, the software stack may not be able to control the physical communication channel itself. This can lead to abrupt device shutdown or reset. When a communication channel is abruptly shut down, it may not follow the correct power-down sequence, thus putting additional stress on the communication channel and reducing the reliability of the communication channel's analog circuitry over time. Attached Figure Description

[0005] Various embodiments according to this disclosure will now be described with reference to the accompanying drawings, in which:

[0006] Figure 1 This is an example communication system that employs a reliable link management method according to at least some embodiments;

[0007] Figure 2 An example communication system employing a reliable link management method for high-speed interconnection according to at least some embodiments is shown;

[0008] Figure 3 This is an example communication system that employs a reliable link management method according to at least some embodiments;

[0009] Figure 4 It is an example receiver that employs a reliable link management method for high-speed interconnect systems according to at least some embodiments;

[0010] Figure 5This is an example communication system that employs a reliable link management method according to at least some embodiments;

[0011] Figure 6 This is a flowchart of a reliable link management method for a high-speed interconnect system, according to at least some embodiments;

[0012] Figure 7 An example computer system according to at least some embodiments is shown, including a transceiver that includes a chip-to-chip interconnect for reliable link management. Detailed Implementation

[0013] Communication systems transmit signals from a transmitter to a receiver via a communication channel or medium (e.g., cable, printed circuit board, link, wireless, etc.). Some communication systems may include multiple devices implementing separate, isolated software stacks. For example, a communication system may include a first device (e.g., a first integrated circuit (IC) or chip) and a second device (e.g., a second IC or chip) and communicate data via a Ground Reference Signalling (GRS) link—for example, the communication system may be a chip-to-chip (C2C) interconnect with two devices including a transmitter and a receiver. The first and second devices may implement isolated software stacks, which may result in the first and second devices asynchronously exiting a reset—for example, the first or second device may be powered off or on at any time without the other devices being aware. In some communication systems, a link may be powered off or reset on the first or second device via its corresponding software stack. Because the software stack is isolated, the software stack of a power-off or reset link cannot communicate the power-off or reset to other devices. Furthermore, due to system security specifications, the corresponding software stack cannot access local physical link control. Therefore, a power-off or reset may occur suddenly.

[0014] Some communication systems can shut down links and associated components (e.g., transmitter and receiver components) based on a power-down sequence. That is, link-related components, and components of the link, can have voltage ranges (e.g., below a maximum voltage threshold) within which they operate reliably based on the manufacturing process. Exceeding these voltage ranges imposes additional stress on the components and can cause them to break down over time. For example, a communication system can shut down certain analog components of the transmitter and receiver based on a power-down sequence. The long-term reliability of components can be reduced when they are not shut down or reset in sequence (e.g., not following the power-down sequence). For example, if the power-down sequence is not followed, and receiver termination is disabled on the first device while transmit equalization is enabled on the second device, the transmitter may experience additional stress, and its performance may degrade. Furthermore, if the first device stops transmitting a clock signal, the phase-locked loop (PLL) of the second device may begin to drift (e.g., become out of phase) because the PLL relies on a clock signal as a reference, for example, on the forwarded clock signal. When a component shutdown or reset occurs abruptly, components associated with the link, as well as components within the link, may shut down or reset out of sequence. For example, shutdown or reset may occur out of order when the corresponding software stack is unable to communicate the shutdown or reset to its local link components or other devices. Consequently, the voltage range of some components may be exceeded, leading to reliability issues.

[0015] Advantageously, various aspects of this disclosure can address the aforementioned deficiencies and other challenges by providing a reliable link management method that detects the state of the link coupling the first and second devices via a clock channel. For example, each device can utilize link state detection circuitry in its receiver to monitor incoming signals and patterns on the clock channel. In some embodiments, each device can be configured with counter logic to determine the number of pulses received within a configurable time period—for example, the device can determine the average frequency of the incoming pattern by detecting edges in the pattern within that time period. If the device determines that the incoming pattern does not correspond to a clock pattern associated with transmitted data (e.g., the determined number of pulses differs from the expected number of pulses associated with the clock signal used to transmit data), the device can determine that the link or its associated components are closed at the other end—e.g., on another device. For example, the software stack of the first device can initiate the closure or reset of the link on the first device. In such embodiments, the first device can begin sending a static pattern on the clock channel to indicate that the first device is closing or resetting the link, or the first device can close or reset the transmitter and stop driving signals on the clock channel. In either case, the second device can continuously determine the number of pulses received within the configurable time period. When the first device sends a static mode or stops driving the signal on the clock channel, the second device can determine whether the number of pulses received within a configurable time period does not match the expected number of pulses associated with the clock signal used for data transmission. Therefore, the second device can determine that the link is being powered down or reset at the first device and initiate its own power-down sequence. In some embodiments, the device can set a longer or shorter time period based on the initiation speed of the power-down sequence—for example, if the transmitter of the second device must be turned off within a first time period after the receiver of the first device is turned off, the second device can set that time period to be shorter than the first time period.

[0016] Furthermore, each device may include a ramp-down (e.g., power-down) circuit configured to receive link status, such as indicating whether a determined number of pulses meets an expected number of pulses. The ramp-down circuit can initiate a power-down sequence when the device determines that the link is being powered down or reset on another device; for example, the ramp-down circuit can control physical link control to continue the power-down sequence. For instance, when the device determines that the link is being powered down or reset on another device, the ramp-down circuit can receive an indication and continue to disable the transmitter equalizer and receiver PLL to maintain component reliability. The ramp-down circuit can also be configured to receive a reset signal from faulty circuitry or an indication for power-down and reset from the corresponding software stack. Therefore, even if the software stack cannot control physical link control, the software stack can instruct a power-down to the ramp-down circuit, which can access link control and initiate a power-down sequence.

[0017] By utilizing a clock channel to monitor link status, each device can correctly execute the power-down sequence. That is, upon determining that a link is being powered down or reset on another device, the device can quickly initiate the power-down sequence without software intervention. Furthermore, this solution avoids circuit designs without reliability vulnerabilities, which, while costly, still cannot handle all situations. Therefore, embodiments of this application allow for reliable link management (e.g., more reliable link power-down or reset) using a hardware-autonomous approach in high-speed interconnect systems without increasing design costs.

[0018] Figure 1 An example of a communication system 100 according to at least one exemplary embodiment is shown. System 100 includes device 110, a communication network 108 including a communication channel 109, and device 112. In at least one embodiment, devices 110 and 112 are two endpoint devices in a computing system, such as a central processing unit (CPU) or a graphics processing unit (GPU). In at least one embodiment, devices 110 and 112 are two servers. In at least one exemplary embodiment, devices 110 and 112 correspond to one or more of a personal computer (PC), a laptop computer, a tablet computer, a smartphone, a server, a server cluster, etc. In some embodiments, devices 110 and 112 may correspond to any suitable type of device communicating with other devices connected to a common type of communication network 108. According to embodiments, a receiver 104 of device 110 or 112 may correspond to a GPU, a switch (e.g., a high-speed network switch), a network adapter, a CPU, a memory device, an input / output (I / O) device, other peripheral devices or components on a system-on-a-chip (SoC), or other devices and components for receiving or measuring signals, etc. As another specific but non-limiting example, devices 110 and 112 may correspond to servers that provide information resources, services, and / or applications to user devices, client devices, or other hosts in system 100. In one example, devices 110 and 112 may correspond to network devices such as switches, network adapters, or data processing units (DPUs).

[0019] Examples of communication networks 108 that can be used to connect devices 110 and 112 include Internet Protocol (IP) networks, Ethernet, InfiniBand (IB) networks, Fibre Channel networks, the Internet, cellular communication networks, wireless communication networks, Ground Reference Signalling (GRS) links, combinations thereof (e.g., Fibre Channel over Ethernet), variations thereof, and / or the like. In a specific but non-limiting example, communication network 108 is a network capable of transmitting data between devices 110 and 112 using data signals (e.g., digital, optical, wireless signals).

[0020] Device 110 includes a transceiver 116 for transmitting and receiving signals, such as data signals. The data signals may be digital or optical signals, using data modulation or other suitable signals to carry the data.

[0021] Transceiver 116 may include digital data source 120, transmitter 124, receiver 104, and processing circuitry 132 for controlling transceiver 116. Digital data source 120 may include suitable hardware and / or software for outputting data in a digital format (e.g., binary code and / or thermometer code). Digital data output by digital data source 120 may be retrieved from memory (not shown) or generated based on input (e.g., user input).

[0022] Transmitter 124 includes suitable software and / or hardware for receiving digital data from digital data source 120 and outputting data signals based on the digital data for transmission to receiver 104 of device 112 via communication network 108. Further details of the structure of transmitter 124 are discussed below in more detail with reference to the accompanying drawings.

[0023] Receiver 104 of devices 110 and 112 may include suitable hardware and / or software for receiving signals, such as data signals from communication network 108. For example, receiver 104 may include components for receiving and processing signals to extract data for storage in memory, as described below. Figures 2-5 Detailed description. In at least one embodiment, receiver 104 may include link status detection circuitry 115. In some embodiments, link status detection circuitry 115 may be configured to receive a clock signal from a clock channel of communication network 108. In some embodiments, link status detection circuitry 115 may determine the status of communication network 108—for example, link status detection circuitry 115 may determine whether a link is powered on in another device. For example, link status detection circuitry 115 is configured to receive a clock pattern and determine the number of pulses detected within a predetermined time period. If link status detection circuitry 115 determines that the number of detected pulses meets an expected number of pulses, device 110 or device 112 may determine that the link is powered on in another device. If link status detection circuitry 115 determines that the number of detected pulses does not meet an expected number of pulses, device 110 or device 112 may determine that the link is turned off or reset in another device. In such embodiments, link status detection circuitry 115 may generate an indication that the link is powered off in another device (e.g., link status) and send the indication to, as referenced Figure 5 The described ramp-down component can initiate a power-down sequence in response to a received instruction, enabling device 110 or device 112 to follow the power-down sequence and maintain the reliability of the link components and components associated with the link.

[0024] Processing circuitry 132 may include software, hardware, or a combination thereof. For example, processing circuitry 132 may include a memory containing executable instructions and a processor (e.g., a microprocessor) that executes the instructions on the memory. The memory may correspond to any suitable type of memory device or collection of memory devices configured to store instructions. Non-limiting examples of suitable memory devices that may be used include flash memory, random access memory (RAM), read-only memory (ROM), variations thereof, combinations thereof, or the like. In some embodiments, the memory and processor may be integrated into a common device (e.g., a microprocessor may include integrated memory). Additionally or alternatively, processing circuitry 132 may include hardware such as application-specific integrated circuits (ASICs). Other non-limiting examples of processing circuitry 132 include integrated circuit (IC) chips, central processing units (CPUs), general-purpose processing units (GPUs), microprocessors, field-programmable gate arrays (FPGAs), collections of logic gates or transistors, resistors, capacitors, inductors, diodes, etc. Some or all of processing circuitry 132 may be disposed on a printed circuit board (PCB) or an assembly of PCBs. It should be understood that any suitable type of electrical component or collection of electrical components may be suitable for inclusion in processing circuitry 132. The processing circuit 132 can send and / or receive signals to other components of the transceiver 116 to control the overall operation of the transceiver 116.

[0025] Transceiver 116 or selected elements thereof may take the form of a pluggable card or controller for device 110. For example, transceiver 116 or selected elements thereof may be implemented on a network interface card (NIC).

[0026] Device 112 may include transceiver 136 for transmitting and receiving signals, such as transmitting and receiving data signals through channel 109 of communication network 108. The same or similar structure of transceiver 116 can be applied to transceiver 136, therefore, the structure of transceiver 136 is not described separately.

[0027] Although not explicitly shown, it should be understood that devices 110 and 112, as well as transceivers 116 and 120, may include other processing devices, storage devices, and / or communication interfaces typically associated with computing tasks, such as sending and receiving data.

[0028] Figure 2 An example of a communication system 200 according to at least one example embodiment is shown. System 200 includes, as referenced... Figure 1 The described devices 110 and 112. Devices 110 and 112 may include references. Figure 1Transmitter 124 and receiver 104 are described. Devices 110 and 112 can be coupled to link 220. In at least one embodiment, link 220 can be as described in reference... Figure 1 Examples of the described communication network 108. In at least one embodiment, link 220 may be an example of a high-speed interconnect. For example, link 220 may be an example of a forward clock architecture. In one embodiment, link 220 may be an example of a ground reference signaling (GRS) link 220. In an embodiment, GRS link 220 may be a signaling scheme for serial data transmission between devices 110 and 112. In at least one embodiment, GRS link 220 may be a high-speed link (e.g., transmitting 40 gigabits per second (GBPS) at a frequency of 20 GHz when performing high-speed communication). In at least one embodiment, link 220 may include an RC-dominated channel and an LC transmission line. Furthermore, GRS link 220 may be an on-chip link, a cross-substrate link (e.g., an organic package), or a link that transmits signals over a printed circuit board (PCB). In some examples, GRS link 220 may use a ground network as a signal reference voltage—for example, ground may be a return signaling.

[0029] In at least one embodiment, link 220 may include data channels 202 and 203 for transmitting signals, data, messages, etc., between device 110 and device 112. For example, data channel 202 may be associated with transmitting signals, data, or messages from device 110 to device 112. Data channel 203 may be associated with transmitting signals, data, or messages from device 112 to device 110—for example, data channel 202 may be associated with transmitter 124 of device 110, and data channel 203 may be associated with transmitter of device 112. In at least one embodiment, link 220 may include the same number of data channels 202 and data channels 203. In this embodiment, data channel 202 may be associated with data channel 203—for example, data channel 202-a and data channel 203-a may be a single transmitter / receiver data channel pair. In at least one embodiment, link 220 may include “N” data channel pairs—for example, “N” data channels 202 and data channels 203. In some embodiments, data channel 202 may be associated with forwarding clock channel 205-a, and data channel 203 may be associated with forwarding clock channel 205-b. In at least one embodiment, each clock channel may be associated with two or more data channels—for example, at least two data channels 202 or data channel 203. In at least one embodiment, data channel 202 transmits data to device 112. In such embodiments, the data is latched onto the forwarding clock of receiver 104 of device 112. In some embodiments, data channel 202 and the corresponding data channel 203 are identical—for example, each data channel 202 and the corresponding data channel 203 supports the same signaling rate and includes the same drivers and hardware.

[0030] In at least one embodiment, devices 110 and 112 may include link state detection circuitry 115. In some embodiments, link state detection circuitry 115 may be coupled to clock channel 205—that is, link state detection circuitry 115-a may be coupled to clock channel 205-a, and link state detection circuitry 115-b may be coupled to clock channel 205-b. In some embodiments, the respective software stack of device 110 or device 112 may initiate the shutdown or reset of link 220 on one side—for example, the software stack of device 110 may shut down or reset the receiver and transmitter of device 110. In some embodiments, devices 110 and 112 may execute isolated software stacks—for example, the software stack of device 110 may not be able to communicate with the software stack of device 112. To ensure proper shutdown or power-off, device 110 or device 112 must determine whether link 220 on another device is being powered down or reset. That is, components of the receiver and transmitter of devices 110 and 112 may follow a power-down (e.g., ramp-down) sequence to ensure that components do not exceed corresponding voltage thresholds. Therefore, devices 110 and 112 can utilize link status detection circuit 115 to determine the status of link 220 and initiate a power-off sequence when link 220 is powered off or reset at another device. For example, link status detection circuit 115-a can receive a clock pattern or signal on a corresponding clock channel 205-a. Link status detection circuit 115 can determine the average frequency of the received clock pattern or signal. In some embodiments, if link status detection circuit 115 determines that the average frequency of the incoming clock pattern or signal meets the expected average frequency of the clock signal associated with data transmission via link 220, then link status detection circuit 115 can determine whether link 220 at the other device is active. In such embodiments, devices 110 and 112 can continue to transmit and receive data. In some embodiments, if link status detection circuit 115 determines that the average frequency of the incoming clock pattern or signal fails to meet the expected average frequency of the clock signal associated with data transmission via link 220, then link status detection circuit 115 can determine whether link 220 at the other device is off, reset, is being shut down, or is being reset. In such an embodiment, the link state detection circuit 115 can refer to... Figure 5 The described ramp-down component sends an instruction. Therefore, the corresponding device 110 or device 112 can initiate a power-off sequence and ensure that the component reliably shuts down without exceeding its respective threshold voltage.

[0031] Figure 3 An example of a communication system 300 according to at least one exemplary embodiment is shown. In at least one embodiment, the communication system 300 is a reference Figure 1 and Figure 2Examples of communication systems 100 or 200 are described. System 300 includes, as referenced... Figure 1 Receiver 104 is described. Receiver 104 may be located in device 110 or device 112. In some embodiments, receiver 104 may be associated with, as referenced Figure 2 The described link 220 is coupled. Receiver 104 may include link status detection circuitry 115 and reliability hardware 330.

[0032] In some embodiments, receiver 104 may be configured to determine link state 220 of link 325. For example, receiver 104 may monitor the link state 220 of clock channel 305 (e.g., as referenced). Figure 2 The incoming clock signal received on the described clock channel 205 is used to determine the link state of link 325 on another device—for example, receiver 104 of device 110 can determine the link state 325 at device 110 by monitoring the incoming clock signal 305. In some embodiments, link state 325 may indicate whether link 220 is active or inactive on another device—for example, whether link 220 is driving data or is powered off or reset.

[0033] In some embodiments, the link state detection circuit 115 may receive clock pattern 310 from clock channel 205. In some embodiments, clock pattern 310 is associated with transmitting data or an active link 220. For example, during normal operation, the transmitter (e.g., as referenced) Figure 2The described transmitter 124 can transmit a periodic clock signal 305 on clock channel 205, wherein the periodic clock signal 305 is clock mode 310. In some embodiments, the link state detection circuit 115 can determine (e.g., detect) the number of pulses (e.g., the number of rising or falling edges) for an incoming clock signal 305 within a configurable time period. In at least one embodiment, the link state detection circuit 115 can determine, upon receiving clock mode 310, the number of pulses detected within a time period that satisfies a desired number of pulses (e.g., satisfies a predetermined condition associated with a specified number of pulses for that time period). That is, the link state detection circuit 115 can be programmed to compare the number of pulses detected within a time period with the desired number of pulses associated with the active link 220—e.g., the periodic clock mode 310. Because clock mode 310 is associated with normal operation (e.g., an active link), the link state detection circuit 115 can determine the number of pulses detected upon receiving clock mode 310 that satisfies the desired number of pulses. In such an embodiment, the link state detection circuit 115 can send a link state 325 to the reliability hardware 330, indicating that the link 220 is active. In some embodiments, when the reliability hardware 330 receives the link state 325 indicating that the link 220 is active, the reliability hardware 330 can avoid taking additional action 335. In at least one embodiment, the reliability hardware 330 is an instance of a finite state machine (FSM) configured to start and manage as referenced. Figure 5 The described power outage sequence.

[0034] In some embodiments, the link state detection circuit 115 may receive a static clock 315 from clock channel 205. In some embodiments, the static clock 315 is associated with device 110 or device 112, indicating that it is about to be reset or powered down. For example, the software stack of device 110 may initiate a reset or shutdown of device 110. In such embodiments, device 110 may begin driving the static clock 315 on clock channel 205 to indicate to device 112 that device 110 is being reset or powered down. In at least one embodiment, the link state detection circuit 115 may determine, upon receiving the static clock 315, the number of pulses detected during a period in which a expected number of pulses was not met (e.g., a predetermined condition associated with a specified number of pulses for that period was not met). That is, the static clock 315 may have a number of pulses different from the expected number of pulses associated with clock pattern 310. In such embodiments, the link state detection circuit 115 may send a link state 325 to reliability hardware 330, indicating that link 220 is inactive. In some embodiments, when the reliability hardware 330 receives a link state 325 indicating that the link 220 is inactive, the reliability hardware 330 may take action 335 to initiate, as referenced Figure 5The described power outage sequence.

[0035] In some embodiments, the link state detection circuit 115 may receive a disabled clock 320 (e.g., an undriven clock 320) from clock channel 205. In some embodiments, a disabled clock 320 is associated with device 110 or device 112 not driving anything through clock channel 205. Because nothing is being driven on clock channel 205, the link state detection circuit may receive random noise or switching. In some embodiments, the device may not be able to send a static clock 315 to indicate shutdown when the corresponding software stack of the device initiates a power-off or reset of link 220 or related components. For example, device 110 may ramp down or power off its transmitter 124 before transmitting the static clock 315. In such embodiments, there is no clock signal 305 driven on clock channel 205-a. Therefore, receiver 104 of device 112 may receive a disabled clock 320, including random noise / switching. In at least one embodiment, the link state detection circuit 115 can determine the number of pulses detected during a period in which a predetermined number of pulses (e.g., a predetermined condition related to a specified number of pulses for that period) is not met when the disabled clock 320 is received. That is, the disabled clock 320 may have a number of pulses different from the expected number of pulses associated with clock mode 310 (e.g., zero (0)). In some embodiments, the link state detection circuit 115 is unsure whether a static clock 315 or a disabled clock 320 is received—for example, the link state detection circuit 115 determines that the incoming signal is different from clock mode 310 rather than determining what specific mode is received. In some embodiments, the link state detection circuit 115 may send a link state 325 to the reliability hardware 300 upon receiving the disabled clock 320, indicating that link 220 is in an inactive state. As described above, when the reliability hardware 330 receives the link state 325 indicating that link 220 is in an inactive state, the reliability hardware 330 may take action 335 to initiate, as referenced... Figure 5 The described power outage sequence.

[0036] Figure 4 An example of a communication system 400 for reliable link management according to at least one embodiment is shown. In at least one embodiment, the communication system 400 is as described in reference... Figure 1 and Figure 2 Examples of communication systems 100 or 200 are described. System 400 includes, as referenced... Figure 1 The device 112 is described. Device 112 can be coupled to, as referenced... Figure 2 The described link 220—for example, GRS link 220. Apparatus 112 may include, as referenced... Figure 1The receiver 104 is described. In at least one embodiment, the components shown in receiver 104 can be considered as referenced. Figure 1 This is a part of the described link state detection circuit 115. Although Figure 4 The circuit corresponding to clock channel 205-a is shown, but the communication system 400 may include a similar circuit corresponding to clock channel 205-b, as shown in the reference. Figure 2 As described above. That is, device 110 may also include receiver 104. Receiver 104 may include sampler 405, frequency divider 410, multiplexer 415, low-pass filter (LPF) 425, local phase-locked loop (PLL) 425, and clock counter 430. In some embodiments, LPF 425, local PLL 420, and clock counter 430 may be digital logic. In at least one embodiment, clock counter 430 may be coupled to a controller or otherwise controlled from, as in reference . Figure 1 The processing circuit 132 described receives signals that control or receive signals from the corresponding software stack of the device 112.

[0037] For reference Figure 2 and Figure 3 In some embodiments, the corresponding software stack of device 110 coupled to device 112 can initiate the shutdown or reset of link 220 at device 110. To prevent components of device 112 from exceeding voltage thresholds (e.g., to ensure the execution of a power-down sequence for device 112), receiver 104 is configured to determine, as... Figure 3 The described link state 325—for example, determining whether link 220 is active at device 110.

[0038] In an embodiment, sampler 405 may be configured to receive a set of bits corresponding to a clock signal (e.g., reference). Figure 3 The described clock signal 305) and sample that group of bits. For example, sampler 405 may receive a first group of bits corresponding to clock mode 310, a second group of bits corresponding to static clock 315, or a third group of bits corresponding to disabled clock 320, as described in reference. Figure 3As described. In at least one embodiment, sampler 405 may send a set of sampled bits received to frequency divider 410. In some embodiments, sampler 405 may send a set of sampled bits to multiplexer 415—for example, avoiding sending a set of sampled bits to frequency divider 410. In some embodiments, frequency divider 410 may be configured to divide the frequency of a set of bits received from device 110. For example, frequency divider 410 may be configured to divide clock speeds received by 2, 4, 8, 16, etc. In some embodiments, device 112 may configure frequency divider 410 during initialization of receiver 104. In some embodiments, device 112 may further divide the clock speed received from device 110 to ensure that the clock signal 305 received from device 110 is reliable. Although three frequency dividers 410 are shown, receiver 104 may include any number of frequency dividers 410 (e.g., including 1, 2, 4, 8, 16, etc.) based on the preferred clock speed of device 112. In some embodiments, the number of frequency dividers 410 used can be configured via the software stack of device 112. Frequency dividers 410 can be configured to send a divided clock signal 305 (e.g., a divided set of sampled bits) to multiplexer 415. In some embodiments, multiplexer 415 is configured to multiplex a set of bits received from sampler 405 or a divided set of bits received from frequency divider 410, and send the multiplexed bits to low-pass filter 425.

[0039] In an embodiment, low-pass filter 425 may be configured to further refine a set of bits (or frequency-divided samples) sampled from multiplexer 415. That is, low-pass filter 425 may eliminate short-term fluctuations and reduce noise on a sampled set of bits, enabling clock counter 430 to receive improved samples or signals. In at least one embodiment, low-pass filter 425 may be coupled to local PLL 420. In some embodiments, local PLL 420 may generate an output signal for low-pass filter 425. For example, local PLL 420 may be initialized or configured to operate at high-speed frequencies (e.g., frequencies used for data transmission operations). In such an embodiment, local PLL 420 may be used to sample received samples at low-pass filter 425. Local PLL 420 and low-pass filter 425 may be used to remove high-frequency components from the output of the received clock—e.g., removing higher frequencies used to generate a noise-reduced signal for clock counter 430.

[0040] In embodiments, clock counter 430 may be configured to detect the number of pulses in a sampled set of bits (e.g., received clock signal 305) received from low-pass filter 425 within a predetermined time period—for example, in embodiments where low-pass filter 425 is not used, from multiplexer 415. In some embodiments, clock counter 430 may detect the number of pulses by determining the number of edges (e.g., the number of signal rises or falls) within a predetermined duration. Clock counter 430 may determine the average frequency of the sampled set of bits—for example, the average frequency of clock signal 305 received from device 110 at receiver 104. In some embodiments, the predefined time period is configurable. For example, processing circuitry 132, a controller coupled to clock counter 430 (e.g., a finite state machine (FSM), or a corresponding software stack of receiver 104 can select a time period for detecting the number of pulses. In at least one embodiment, processing circuitry 132 can select a time period from a list of programmed time periods. In some embodiments, processing circuitry 132 can select a time period based on reliability constraints of components of receiver 104, transmitter 124, or link 220. For example, if receiver 104 of device 110 loses power, transmit equalization of transmitter 124 of device 112 can be disabled during a first time period to avoid putting excessive stress on transmitter 124—e.g., to prevent components of transmitter 124 from exceeding their respective threshold voltages and degrading over time. Therefore, in such embodiments, processing circuitry 132 can select a time period shorter than the first time period associated with transmitter 124 to ensure that transmit equalization is disabled before performance degradation occurs. In some embodiments, processing circuitry 132 can also enable or disable the clock counter based on sending an enable signal 435.

[0041] In at least one embodiment, after detecting the number of pulses within the time period, clock counter 430 can compare the detected number of pulses with an expected number of pulses (e.g., a predetermined condition) received via configuration signal 440. That is, the corresponding software stack of processing circuitry 132 or device 112 can program the expected number of pulses into clock counter 430 via configuration signal 440. In some embodiments, the expected number of pulses is associated with the number of pulses in clock mode 310—for example, with the periodic clock signal 305 transmitted during normal operation. In some embodiments, the expected number of pulses is associated with a frequency division clock mode 310. That is, the expected number of pulses can vary based on the amount by which the incoming clock signal 305 is divided. When processing circuitry 132 (or software stack) determines the amount of frequency division of the incoming clock signal 305, processing circuitry 132 (or software stack) can determine the expected number of pulses for the frequency division clock via configuration signal 440 and program the expected number of pulses for the frequency division clock into clock counter 430.

[0042] In some embodiments, if the detected number of pulses differs from the expected number of pulses, the clock counter 430 can determine whether the link 220 at another device (e.g., device 110) is inactive—e.g., being shut down or reset. For example, the clock counter 430 can determine that the detected number of pulses differs from the expected number of pulses when device 110 is driving a static clock 315 or not driving a clock signal (e.g., receiver 104 receives a disabled clock signal 320), as referenced. Figure 3 As described. In such an embodiment, the clock counter 345 can provide information to the reliable hardware of the device 112 (e.g., as referenced). Figure 3 The reliability hardware 330 described sends a local link status 325 indicating that the link is inactive. Therefore, the reliability hardware can continue with the startup and management of the power-down sequence of device 112, as described in reference [reference needed]. Figure 5 As described.

[0043] In some embodiments, if the detected number of pulses is the same as the expected number of pulses (e.g., the expected number of pulses is met), the clock counter 430 can determine whether the link 220 at another device (e.g., device 110) is active—e.g., transmitting data. For example, the clock counter 430 can determine the number of detected pulses that meet the expected number of pulses when device 110 drives clock mode 310, as referenced Figure 3 As described above. In such an embodiment, the clock counter 430 can send the link status 325 to the reliability hardware 330 of the device 112, indicating that the link is active. Therefore, the reliability hardware can avoid the power-down sequence that initiates the device 112, as described in the reference. Figure 5 As described.

[0044] In some embodiments, clock counter 430 may be configured to detect that the number of pulses in the received clock signal 305 is the same as the expected number of pulses over multiple time periods. For example, clock counter 430 may be configured to detect that the number of pulses is the same as the expected number of pulses over two (2) time periods, where each time period has the same value. In other embodiments, clock counter 430 may detect that the number of pulses is the same as the expected number of pulses over more than two (2) time periods. That is, clock counter 430 may avoid indicating that the link is active or inactive until a specified number of cycles has elapsed. In some embodiments, having a specified number of time periods greater than one (1) may improve accuracy and reduce false alarms.

[0045] Figure 5 An example communication system 500 for reliable link management according to at least one embodiment is illustrated. In at least one embodiment, the communication system 500 is a reference... Figure 1-4Examples of communication systems 100, 200, 300, or 400 are described. Communication system 500 includes, as referenced... Figure 1 The described devices 110 and 112. Devices 110 and 112 can be coupled to, for example... Figure 2 The described link 220—for example, a GRS link 220 having one or more data channels 202 and clock channels 205. Apparatus 110 may include a ramp-down component 505, a transmit equalization (TX EQ) disabler 510, a receiver phase-locked loop (RX PLL) disabler 515, a disabler 520, physical layer control 535, physical layer 540-a, and a ramp-down trigger generator 545. In embodiments, the ramp-down component 505, TX EQ disabler 510, RX PLL disabler 515, disabler 520, and ramp-down trigger generator 545 may be considered as part of reliability hardware 330, as referenced. Figure 3 The device 112 may include a physical layer 540-b and a link state detection circuit 115, as described in reference [reference needed]. Figure 1 As described. Although Figure 5 Different circuits in devices 110 and 112 are shown, but each device may have the same components. For example, device 112 may also include a ramp-down component 505, a transmit equalization (TX EQ) disabler 510, a receiver phase-locked loop (RX PLL) disabler 515, a disabler 520, a physical layer control 535, and a ramp-down trigger generator 545, while device 110 may also include a link state detection circuit 115. In at least one embodiment, the ramp-down component 505, TX EQ disabler 510, RX PLL disabler 515, and disabler 520 are examples of finite state machines (FSMs).

[0046] In at least one embodiment, the ramp-down trigger generator 545 is configured to generate a ramp-down trigger 547 based on receiving a reset signal 550, a software signal 55, or a link state 325-a. For example, the ramp-down trigger generator 545 may generate a ramp-down trigger based on receiving a reset signal 550. In some embodiments, the ramp-down trigger generator 545 may receive the reset signal 550 from hardware components. For example, the ramp-down trigger generator 545 may receive the reset signal 550 from an error circuit—for example, when the number of errors in the communication system 500 or device 110 exceeds an error threshold, the error circuit may send the reset signal 550 to the ramp-down trigger generator 545. In some embodiments, the ramp-down trigger generator 545 may receive the reset signal 550 from the software stack associated with device 110. In some embodiments, the reset signal 550 may instruct the ramp-down trigger generator 545 to reset the link 220 at device 110 or components associated with the link 220—for example, resetting the receiver 104 or transmitter 124 of device 110. In some embodiments, the ramp-down trigger generator 545 may generate a ramp-down trigger 547 based on a software signal 555 received from the software stack. In some embodiments, the software signal 555 may instruct the ramp-down trigger generator 545 to shut down or disconnect the link 220 at device 110 or components associated with the link 220. In at least one embodiment, the ramp-down trigger generator 545 is configured to generate a ramp-down trigger 547 based on a link state 325-a received from the link state detection circuit 115 of device 110. For example, the ramp-down trigger generator 545 may generate a ramp-down trigger 547 when link state 325-a indicates that the link is inactive on device 112, as referenced. Figure 3 and Figure 4 As described—for example, device 112 drives a static clock 315, or receiver 104 of device 110 receives a disable clock 320. In some embodiments, ramp-down trigger generator 545 may generate ramp-down trigger 547 based on any combination of received reset signal 550, software signal 555, and link state 325-a—for example, based on received reset signal 550 and software signal 555, or software signal 555 and link state 325-a, or received reset signal 550, software signal 555, link state 325-a, or any combination thereof. In some embodiments, ramp-down trigger 547 may instruct ramp-down component 505 to initiate a power-down or ramp-down sequence associated with device 110.

[0047] In at least one embodiment, the ramp descent component 505 is configured to receive a ramp descent trigger 547. In some embodiments, the ramp descent component 505 is configured to initiate a ramp descent sequence associated with device 110 based on receiving the ramp descent trigger 547. In such embodiments, the ramp descent component 505 may send messages, signals, or commands to physical layer control 535 to shut down or reset analog components in physical layer 540-a associated with the power-down sequence. In some embodiments, the ramp descent component 505 is configured to send messages, commands, or signals to TX EQ disabler 510, RX PLL disabler 515, and disabler 520 to disable their respective components. In at least one embodiment, a software stack may program the ramp descent sequence into the ramp descent component 505—for example, the ramp descent component 505 may initiate and manage ramp descent sequences indicated by the software stack. Thus, the ramp descent component 505 may execute the same ramp descent sequence each time it receives the ramp descent trigger 547. In at least one embodiment, the ramp descent component 505 can instruct the transmitter 124 to send a static clock 315, as referenced. Figure 3 The notification—for example, alerts device 112 link 220 and associated components that are being powered down or reset at device 110. In some embodiments, ramp-down component 505 is configured to ramp down transmitter 124 before ramping down receiver 104. For example, transmitter 124 may be powered down first, otherwise it may be overstressed or exceed a corresponding voltage threshold. In other examples, transmitter 124 may be disabled first, allowing device 112 time to initiate a safe ramp-down sequence and reducing the time device 112's components are exposed to adverse conditions. For example, as described above, if receiver 104 of device 110 is disabled while transmitter 124 of device 112 is enabled, transmitter 124 of device 112 may be subjected to additional stress and degradation. Therefore, device 110 may disable its transmitter 124 first, allowing device 112 to detect a shutdown on clock channel 205 (e.g., when clock channel 205 is not driven) and quickly shut down its transmitter 124 before receiver 104 of device 110 is disabled. In some embodiments, the ramp-down component 505 can ramp down the transmitter 124 at different times—for example, the ramp-down component 505 can disable the component based on the optimal ramp-down sequence for maintaining the reliability of the components of the device 110.

[0048] In at least one embodiment, the TX EQ disabler 510 is configured to receive link status 325-a or a command / signal from the ramp-down component 505. In at least one embodiment, the TX EQ disabler 510 is configured to disable transmitter equalization of transmitter 124 of device 110 based on receiving link status 325-a or a signal from the ramp-down component 505. For example, when link status 325-a indicates that link 220 is being de-energized or reset at device 112, the TX EQ disabler 510 may disable transmitter equalization of transmitter 124. In some embodiments, when link status 325-a indicates that link 220 is active—for example, when link status detection circuit 115 at device 110 receives clock mode 310—the TX EQ disabler 510 may avoid disabling transmitter equalization.

[0049] In at least one embodiment, the RX PLL disabler 515 is configured to receive link status 325-a or command / signal from the ramp descent component 505.

[0050] In at least one embodiment, the disabler 520 is configured to receive link status 325-a or a command / signal from the ramp-down component 505. In at least one embodiment, the disabler 520 is configured to configure other reliability-critical components of the device 110—e.g., other components that are reset or shut down as quickly as possible after it is determined that link 220 is reset or powered down at device 112—based on the receipt of link status 325-a or a signal from the ramp-down component 505. For example, when link status 325-a indicates that link 220 is being powered down or reset at device 112, the disabler 520 may disable other reliability-critical components. In some embodiments, when link status 325-a indicates that link 220 is active—e.g., when the link status detection circuit 115 at device 110 receives clock mode 310—the disabler 520 may avoid disabling other reliability-critical components.

[0051] It should be noted that TX EQ disabler 510, RX PLL disabler 515, and disabler 520 are examples of FSMs, which device 110 can utilize to perform a ramp-down sequence. In other embodiments, device 110 may include additional FSMs for other components sensitive to the link 220 disabled at device 112. In some embodiments, TX EQ disabler 510, RX PLL disabler 515, and disabler 520 may be part of ramp-down component 505—for example, TX EQ disabler 510, RX PLL disabler 515, and disabler 520 may be disabled separately as soon as possible after inactive link 220 is detected to avoid reliability issues. In other embodiments, device 110 may follow different ramp-down procedures. For example, device 110 may perform any combination of operations in any order after determining that link 220 is inactive; disable reliability-sensitive components of transmitter 124, disable reliability-sensitive components of receiver 104, completely shut down transmitter 124, and completely shut down receiver 104.

[0052] Physical layer control 535 may be an interface between digital logic (e.g., link state detection circuitry 115, TX EQ disabler 510, RX PLL disabler 515, disabler 520, ramp descent component 505, etc.) and analog components of physical layer 540-A. In some embodiments, physical layer control 535 may be an example of a flip-flop or a register. In some embodiments, physical layer control 535 may disable the analog circuitry of physical layer 540-a indicated by ramp descent component 505, TX EQ disabler 510, RX PLL disabler 515, and disabler 520.

[0053] In at least one embodiment, physical layers 540-a and 540-b are configured to transmit and receive signals and data via link 220. Physical layers 540-a and 540-b may include references. Figure 1 The transmitter 124 and receiver 104 are described. In some embodiments, the physical layer 540 may be an example of analog circuitry configured to transmit and receive signals via link 220.

[0054] For reference Figure 2-4 The link state detection circuit 115 is configured to detect the number of pulses of the received clock signal and determine whether the detected number of pulses meets the expected number of pulses. In some embodiments, when the detected number of pulses meets the expected number of pulses, the link state detection circuit 115 can generate a link state 325-b, which indicates that the link 220 is active. In such embodiments, the device 112 can continue to operate normally—for example, continue to transmit, process...

[0055] Processing and receiving data. In some embodiments, when the detected number of pulses fails to meet the expected number of pulses, the link state detection circuit 115 can generate a link state 325-b, which indicates that the link 220 is inactive. In such embodiments, the TX EQ disable 510, RX PLL disable 515, disable 520, and the ramp-down component 505 of the device 112 can continue the power-down or ramp-down sequence of the device 112.

[0056] Figure 6 An example flowchart of a method 600 for reliable link management for high-speed interconnects is shown. This method 600 can be executed by processing logic including hardware, software, firmware, or any combination thereof.

[0057] Okay. In at least one embodiment, method 600 is performed by transmitter 124 or receiver 104 of the first device 110 or the second device 112, as referenced. Figure 3 The aforementioned—for example, via TX EQ disable 510, RX PLL disable 515, disable 520, ramp descent assembly 505, ramp descent

[0058] Trigger generator 545 and link status detection circuit 115. Although shown in a specific sequence or order, the order of the processes can be modified unless otherwise stated. Therefore, the illustrated embodiment should be understood only as...

[0059] Examples are provided, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not every embodiment requires all processes. Other diagrams illustrate the possible methods for reliable link management.

[0060] In operation 605, the processing logic can receive signals through one or more channels associated with the transmitted clock signal. For example, the system may include links (e.g., link 220), including those connected to the transmission...

[0061] This includes one or more channels associated with the data transmission (e.g., data channels 202 and 203) and one or more channels associated with the transmission clock signal (e.g., clock channel 205). In some embodiments, the processing logic can be transmitted through one or more channels associated with the transmission clock signal.

[0062] Receive a set of bits associated with a mode, where this mode differs from the second mode associated with data transmission operations—for example, the received signal can be a set of bits. For example, processing logic can be in the...

[0063] In two devices (e.g., device 112), and the first device (e.g., device 110), the group of bits can be transmitted. In some embodiments, the group of bits can be associated with a static clock 315, and the second mode can be as referenced. Figure 3 The described clock mode 310 is associated. In some embodiments, the clock mode 310 is...

[0064] The processing logic can receive a second set of bits associated with the second mode 0 through one or more channels associated with the transmission clock signal—for example, the processing logic can receive clock mode 310. At least

[0065] In one embodiment, the processing logic may receive a signal in response to a first device initiating a power-off sequence (e.g., a second power-off sequence). In some embodiments, the processing logic may determine that the number of pulses associated with a set of bits fails to meet a predetermined condition related to a specified number of pulses within a time period in response to a signal transmitted by the first or second device—for example, failing to meet a condition as referenced... Figure 3 and Figure 4 The expected number of pulses for that time period.

[0066] At operation 610, the processing logic may determine the number of pulses (e.g., one set of bits or a second set of bits) associated with the signal within a time period. In at least one embodiment, the processing logic is configured to select a time period from multiple time periods to determine the number of pulses—for example, the time period is configurable. In some embodiments, the processing logic may select the time period based on the reliability conditions of components of the first or second device—for example, based on concerns that the transmitter 124 of the second device may be over-stressed when the receiver of the first device is disabled. In some embodiments, the processing logic may select a subset of frequency dividers (e.g., frequency divider 410) to divide the received signal, wherein determining the number of pulses associated with the signal within a time period is in response to selecting a subset of the frequency divider set.

[0067] At operation 615, the processing logic may determine that the number of pulses associated with a signal fails to meet a predetermined condition related to a specified number of pulses within that time period. For example, the processing logic may determine that the number of pulses associated with a set of bits fails to meet a predetermined condition related to a specified number of pulses within that time period. In some embodiments, the processing logic may determine that the number of pulses of a signal received in response to a first device initiating a power-off sequence fails to meet a predetermined condition—for example, the number of pulses detected during the period of static clock 315 and disable clock 320 fails to meet a predetermined condition related to a specified number of pulses within that time period. In some embodiments, if the processing logic determines that the number of pulses does not meet the predetermined condition, the processing logic may continue operating at 620. In at least one embodiment, the processing logic may determine that the number of pulses associated with a signal (e.g., a second set of bits) meets a predetermined condition related to a specified number of pulses within that period—for example, the number of pulses detected during the time period in receive clock mode 310 meets the predetermined condition. In such embodiments, the processing logic may avoid initiating a power-off sequence in response to determining the number of pulses that meet the predetermined condition. In at least one embodiment, the processing logic may determine the number of times that the number of pulses associated with the signal satisfies a predetermined condition related to a specified number of pulses in the time period, wherein the number of times satisfies a threshold number of times that the signal satisfies the number of pulses in the time period—for example, the processing logic may determine that the number of pulses in the time period cannot satisfy the predetermined condition in multiple time periods.

[0068] At operation 620, the processing logic may initiate a power-down sequence in response to determining the number of pulses for which a predetermined condition related to a specified number of pulses within the time period has not been met. For example, a ramp-down trigger generator 545 may generate a ramp-down trigger 547 in response to the number of pulses failing to meet the predetermined condition. In at least one embodiment, the processing logic may initiate a power-down sequence in response to receiving a reset signal from a component associated with the link—for example, based on receiving a reset signal from a hardware component 550 associated with the link, as referenced... Figure 5 As described above. In at least one embodiment, the processing logic may initiate a power-down sequence in response to receiving a second signal from a software stack associated with the device—for example, based on, as referenced... Figure 5 The described receiving software signal is 555.

[0069] At operation 625, the processing logic can execute a power-down sequence. For example, the processing logic can disable transmitter equalization in response to determining that the number of pulses does not meet a predetermined condition. In some embodiments, the processing logic can disable the receiver in response to disabling the transmitter. In some embodiments, the processing logic can execute as described in the reference... Figure 5 The described power outage sequence.

[0070] Figure 7A computer system 700 according to at least one embodiment is illustrated, including a transceiver comprising a chip-to-chip interconnect. In at least one embodiment, the computer system 700 may be a system having interconnected devices and components, a System-on-a-Chip (SoC), or some combination thereof. In at least one embodiment, the computer system 700 is formed by a processor 702, which may include execution units for executing instructions. In at least one embodiment, the computer system 700 may include, but is not limited to, components such as the processor 702, which employs execution units including logic to execute algorithms for processing data. In at least one embodiment, the computer system 700 may include a processor, such as one available from Intel Corporation of Santa Clara, California. Processor family, Xeon™ XScale™ and / or StrongARM™ or Nervana TM The microprocessor can be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors can also be used. In at least one embodiment, the computer system 700 can execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0071] In at least one embodiment, the computer system 700 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application can include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions. In embodiments, the computer system 700 can be used in devices such as graphics processing units (GPUs), network adapters, central processing units, and network devices such as switches (e.g., high-speed direct GPU-to-GPU interconnects, such as NVIDIA GH100 NVLINK or NVIDIA Quantum 2 64-port InfiniBand NDR switches).

[0072] In at least one embodiment, the computer system 700 may include, but is not limited to, a processor 702, which may include, but is not limited to, one or more execution units 708 configured to execute a Computational Unified Device Architecture (“CUDA”). (Developed by NVIDIA Corporation, Santa Clara, California) In at least one embodiment, the CUDA program is at least a part of a software application written in the CUDA programming language. In at least one embodiment, the computer system 700 is a single-processor desktop or server system. In at least one embodiment, the computer system 700 may be a multiprocessor system. In at least one embodiment, the processor 702 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing instruction set combinations, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 702 may be coupled to a processor bus 710, which allows data signals to be transmitted between the processor 702 and other components in the computer system 700.

[0073] In at least one embodiment, processor 702 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 704. In at least one embodiment, processor 702 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside outside of processor 702. In at least one embodiment, processor 702 may also include a combination of internal and external caches. In at least one embodiment, register file 706 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0074] In at least one embodiment, an execution unit 707, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 702. The processor 702 may also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 707 of the processor 702 may include logic for processing a compressed instruction set 709. In at least one embodiment, by including the compressed instruction set 709 in the instruction set of the general-purpose processor 702, along with the associated circuitry for executing the instructions, compressed data in the general-purpose processor 702 can be used to perform operations used by many multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor's data bus to perform operations on compressed data, which may eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on a data element at a time.

[0075] In at least one embodiment, the execution unit may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, the computer system 700 may include, but is not limited to, memory 720. In at least one embodiment, memory 720 may be implemented as a DRAM device, SRAM device, flash memory device, or other memory device. Memory 720 may store instructions 719 and / or data 721 represented by data signals that can be executed by processor 702.

[0076] In at least one embodiment, the system logic chip may be coupled to the processor bus 710 and the memory 720. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 716, and the processor 702 may communicate with the MCH 716 via the processor bus 710. In at least one embodiment, the MCH 716 may provide a high-bandwidth memory path 718 to the memory 720 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 716 may initiate data signals between the processor 702, the memory 720, and other components in the computer system 700, and bridge data signals between the processor bus 710, the memory 720, and the system I / O 722. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 716 may be coupled to the memory 720 via the high-bandwidth memory path 718, and the graphics / video card 712 may be coupled to the MCH 716 via an Accelerated Graphics Port (“AGP”) interconnect 714.

[0077] In at least one embodiment, computer system 700 may use system I / O 722 as a proprietary hub interface bus to couple MCH 716 to I / O controller hub (“ICH”) 730. In at least one embodiment, ICH 730 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 720, chipset, and processor 702. Examples may include, but are not limited to, an audio controller 729, a firmware hub (“Flash BIOS”) 728, a transceiver 726, a data storage device 724, a conventional I / O controller 723 including a user input interface 725 and a keyboard interface, a serial expansion port 727 (e.g., USB), and a network controller 734. Data storage device 724 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device. In an embodiment, transceiver 726 includes a constrained FFE 708.

[0078] In at least one embodiment, Figure 7 The system shown includes interconnected hardware devices or "chips" in transceiver 726—for example, transceiver 726 includes a chip-to-chip interconnect comprising a first device 110 and a second device 112, as shown in reference. Figure 1 (as described). In at least one embodiment, Figure 7 An exemplary SoC can be shown. In at least one embodiment, Figure 7 The device shown can be interconnected with proprietary interconnects, standardized interconnects (such as PCIe), or some combination thereof and utilizes, as referenced Figure 2 The GRS link 220 is described. In at least one embodiment, one or more components of system 700 are interconnected using Computational Fast Link (“CXL”) interconnects. In an embodiment, transceiver 726 may include link state detection circuitry 115. In some embodiments, link state detection circuitry 115 may determine whether a link is powered on at another device. If link state detection circuitry 115 determines that the link is not powered on at another device, link state detection circuitry 115 may generate an indication (e.g., link state) that the link is de-energized at the other device and send the indication to, as referenced in [reference missing] Figure 5 The described ramp-down component can initiate a power-down sequence in response to a received instruction, enabling the chip to follow the power-down sequence and maintain the reliability of the link components and related components. Therefore, the link state detection circuit 115 can be configured as described in reference... Figure 2-6 The described reliable link management.

[0079] Other variations are within the spirit of this disclosure. Therefore, although the disclosed technology is readily adaptable to various modifications and alternative constructions, certain embodiments thereof are illustrated in the accompanying drawings and have been described in detail above. However, it should be understood that the disclosure is not intended to be limited to one or more specific forms disclosed, but rather, it is intended to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of this disclosure as defined in the appended claims.

[0080] Unless otherwise stated or obviously contradicted by the context, the terms “a,” “an,” and “the,” and similar references, used in the context of describing the disclosed embodiments (particularly in the context of the appended claims), should be interpreted as encompassing both singular and plural forms, rather than as definitions of terms. Unless otherwise stated, the terms “comprising,” “having,” “including,” and “containing” should be interpreted as open-ended terms (meaning “including, but not limited to”). “Connection” (referring to a physical connection where not modified) should be interpreted as partially or wholly contained, attached to, or joined together, even with some intervention. Unless otherwise indicated herein, references to numerical ranges herein are intended only as a way of abbreviating each individual value falling within that range, and each individual value is incorporated into the specification as if it were separately described herein. In at least one embodiment, unless otherwise indicated or contradicted by the context, the use of the terms “set” (e.g., “item set”) or “subset” should be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by the context, the term “subset” of the corresponding set does not necessarily mean an appropriate subset of the corresponding set, but rather that the subset and the corresponding set can be equal.

[0081] Unless otherwise explicitly stated or clearly contradicted by the context, connective phrases such as “at least one of A, B, and C” or “at least one of A, B, and C” are understood in the context to generally refer to items, terms, etc., which can be A or B or C, or any non-empty subset of the set A, B, and C. For example, in an illustrative example of a set with three members, the connective phrases “at least one of A, B, and C” and “at least one of A, B, and C” refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Therefore, such connective language is generally not intended to imply that some embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless otherwise stated or contradicted by the context, the term “multiple” indicates a plural state (e.g., “multiple items” means multiple items). In at least one embodiment, the number of items in the multiple items is at least two, but may be more if explicitly indicated or indicated by the context. Furthermore, unless otherwise stated or clearly understood from the context, the phrase “based on” means “at least partially based on” rather than “based on only”.

[0082] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations thereof and / or combinations thereof) are executed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more application programs) that is executed jointly on one or more processors via hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagating transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a group of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) on which executable instructions are stored, which, when executed by one or more processors of a computer system (e.g., as a result of execution), cause the computer system to perform the operations described herein. In at least one embodiment, the group of non-transitory computer-readable storage media comprises a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media lack all the code, but the plurality of non-transitory computer-readable storage media collectively store all the code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors.

[0083] Therefore, in at least one embodiment, the computer system is configured to implement one or more services that perform the operations of the processes described herein, either individually or collectively, and such a computer system is configured with suitable hardware and / or software to enable the implementation of the operations. Furthermore, the computer system implementing at least one embodiment of this disclosure is a single device, and in another embodiment it is a distributed computer system comprising multiple devices operating in different ways, such that the distributed computer system performs the operations described herein, and that a single device does not perform all the operations.

[0084] The use of any and all examples or exemplary language (e.g., “such as”) provided herein is intended only to better illustrate embodiments of this disclosure and does not constitute a limitation on the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating that any unclaimed element is essential to the practice of the disclosure.

[0085] All references cited in this article, including publications, patent applications and patents, are incorporated herein by reference as if each reference were individually and specifically indicated to be incorporated herein by reference and the entire contents of which are described herein.

[0086] The terms “coupled” and “connected”, and their derivatives, may be used in the specification and claims. It should be understood that these terms may not be intended to be synonyms with each other. Rather, in certain examples, “connected” or “coupled” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0087] Unless otherwise expressly stated, it will be understood that throughout this specification, terms such as “processing,” “calculating,” “determining,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that process and / or convert data represented as physical quantities (e.g., electrons) in the registers and / or memory of the computing system into other data represented as physical quantities in the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0088] Similarly, the term "processor" can refer to any device or part of memory that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. A "computing platform" can include one or more processors. As used herein, a "software" process can include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Likewise, each process can refer to multiple processes that execute instructions sequentially or intermittently, or in parallel. In at least one embodiment, the terms "system" and "method" are used interchangeably herein, provided that a system can embody one or more methods, and a method can be considered a system.

[0089] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in various ways, such as by receiving data as a parameter to a function call or a call to an application programming interface. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. In at least one embodiment, reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be implemented by transmitting data as an input or output parameter to a function call, an application programming interface, or an inter-process communication mechanism.

[0090] While the description herein illustrates exemplary embodiments of the described technologies, other architectures may be used to implement the described functionality and are intended to fall within the scope of this disclosure. Furthermore, although specific assignments of responsibilities have been defined above for descriptive purposes, various functions and responsibilities may be assigned and divided in different ways depending on the circumstances.

[0091] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or actions described. Rather, specific features and actions are disclosed as exemplary forms for implementing the claims.

Claims

1. A communication system, comprising: A link includes one or more channels associated with transmitting data and one or more channels associated with transmitting clock signals; as well as A means coupled to the link and including a receiver, the means being used to: Signals are received through one or more channels associated with the transmission of the clock signal; Determine the number of pulses associated with the signal within the time period; The number of pulses associated with the signal was determined to be insufficient to meet a predetermined condition related to a specified number of pulses within the time period; as well as In response to determining that the number of pulses fails to meet the predetermined condition related to the number of pulses within the time period, a power-off sequence is initiated.

2. The system according to claim 1, wherein the device is further configured to: Determine that the number of pulses satisfies the predetermined condition related to the specified number of pulses within the time period; and In response to determining that the number of pulses meets the predetermined condition, the power-off sequence is avoided from being initiated.

3. The system according to claim 1, wherein the device is further configured to: A reset signal is received from a component associated with the link, wherein the power-down sequence is initiated at least in part based on the receipt of the reset signal.

4. The system according to claim 1, wherein the device is further configured to: A second signal is received from the software stack associated with the device, wherein the power-down sequence is initiated at least in part based on the receipt of the second signal.

5. The system of claim 1, wherein the apparatus further comprises a frequency divider set, the apparatus being used for: A subset of the frequency divider set is selected for frequency division of the received signal, wherein determining the number of pulses associated with the signal within the time period is in response to selecting the subset of the frequency divider set.

6. The system of claim 1, wherein the device is further configured to: The time period for determining the number of pulses is selected from multiple time periods.

7. The system according to claim 1, wherein the device is further configured to: The number of times the number of pulses associated with the signal fails to meet a predetermined condition related to a specified number of pulses within the time period is determined, wherein the number of times satisfies a threshold number of times the signal satisfies the number of pulses within the time period.

8. The system of claim 1, wherein the means further comprises a transmitter, and the means is further configured to: In response to determining that the number of pulses does not meet the predetermined condition related to the specified number of pulses within the time period, transmitter equalization is disabled; and In response to disabling the transmitter, the receiver is also disabled.

9. The system according to claim 1, further comprising a second device, the second device being used for: The signal is transmitted via one or more channels associated with the transmission of the clock signal, wherein the means is configured to determine, in response to the second means transmitting the signal, that the number of pulses associated with the signal fails to meet the predetermined condition.

10. A communication method, comprising: Receive signals from one or more channels associated with the clock signal of the transmission link; Determine the number of pulses associated with the signal within the time period; It was determined that the number of pulses associated with the signal failed to meet a predetermined condition related to a specified number of pulses within the time period; as well as If the response determines that the number of pulses fails to meet the predetermined condition related to the specified number of pulses within the time period, a power-off sequence is initiated.

11. The method of claim 10, further comprising: Determine that the number of pulses satisfies the predetermined condition related to the specified number of pulses within the time period; as well as In response to determining that the number of pulses meets the predetermined condition, the power-off sequence is avoided from being initiated.

12. The method of claim 10, further comprising: A reset signal is received from a component associated with the link, wherein the power-down sequence is initiated at least in part based on the receipt of the reset signal.

13. The method of claim 10, further comprising: A second signal is received from the software stack, wherein the power-down sequence is initiated at least in part based on the receipt of the second signal.

14. The method of claim 10, further comprising: A subset of the frequency divider set is selected for frequency division of the received signal, wherein determining the number of pulses associated with the signal within the time period responds to the selection of the subset of the frequency divider set.

15. The method of claim 10, further comprising: The time period for determining the number of pulses is selected from multiple time periods.

16. The method of claim 10, further comprising: The number of times the number of pulses associated with the signal fails to meet the predetermined condition related to the specified number of pulses within the time period is determined, wherein the number of times satisfies a threshold number of times the signal satisfies the number of pulses within the time period.

17. The method of claim 10, further comprising: In response to determining that the number of pulses does not meet the predetermined condition related to the specified number of pulses within the time period, transmitter equalization is disabled; as well as The receiver is disabled in response to the transmitter being disabled.

18. A communication system, comprising: A link includes one or more channels associated with transmitting data and one or more channels associated with transmitting clock signals; A first device, coupled to the link and including a transmitter, is configured to: A set of bits associated with a mode is transmitted through one or more channels associated with a transmission clock signal, wherein the mode is different from a second mode associated with a data transmission operation; as well as A second device, coupled to the link and including a receiver, is used for: Receive a set of bits associated with the pattern; Determine the number of pulses associated with the set of bits within the time period; The number of pulses associated with the set of bits was determined to have failed to meet a predetermined condition related to a specified number of pulses within the time period; as well as In response to determining that the number of pulses fails to meet the predetermined condition related to the specified number of pulses within the time period, a power-off sequence is initiated.

19. The system according to claim 18, wherein: The first device is also used for: A second set of bits associated with the second mode is transmitted through one or more channels associated with the transmission of the clock signal; and The second device is also used for: Receive the second group of bits associated with the second mode; Determine the number of second pulses associated with the second group of bits within the time period; Determine that the second pulse number associated with the second group of bits satisfies a predetermined condition related to the specified pulse number within the time period; as well as In response to determining that the second pulse number satisfies the predetermined condition related to the specified pulse number within the time period, the power-off sequence is avoided from being initiated.

20. The system according to claim 18, wherein: The first device is also used for: In response to initiating a second power-off sequence, the transmitter is powered off; and The second device is also used for: In response to the first device initiating the second power-off sequence, a signal is received through one or more channels associated with the transmission of the clock signal; Determine the number of second pulses associated with the signal within the time period; It is determined that the second number of pulses associated with the signal fails to meet the predetermined condition related to the specified number of pulses within the time period; as well as In response to determining that the second pulse count fails to meet the predetermined condition related to the specified pulse count within the time period, the power-off sequence is initiated.

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