Efficient CXP communication method, device and electronic equipment

Abstract

The application discloses a kind of high-efficiency CXP communication method, device and electronic equipment, and high-efficiency coding protocol CXP communication is realized by the cooperation of speed changer and encoding and decoding module based on FPGA.The device comprises: first speed changer, the data sent by CXP data channel is speed-processed, so that data is adapted to encoder;Second speed changer, the data after encoding by encoder is speed-processed, so that data is adapted to FPGA transceiver;FPGA transceiver transmits the data after processing to optical module;Optical module is also used to transmit the data received to FPGA transceiver for processing;Third speed changer, the data after processing by FPGA transceiver is received, and data is speed-processed, so that data is adapted to decoder;Fourth speed changer, the data after decoding by decoder is speed-processed, so that data is adapted to CXP data channel, and data is transmitted to the CXP data channel;Wherein, the encoding and decoding protocol of encoder and decoder is consistent.

Description

Technical Field

[0001] This invention relates to the field of high-speed image data transmission, and in particular to an efficient CXP communication method, apparatus, and electronic device. Background Technology

[0002] CXP (CoaXPress) is a coaxial cable asymmetric high-speed serial communication standard, a digital interface standard for asymmetric high-speed point-to-point serial communication, developed for the machine vision industry. Traditional CXP interfaces rely on 75-ohm coaxial cable transmission, resulting in high costs for the interface chip (PHY), connectors, and cables, complex PCB design, and limited transmission distance; for example, at a line speed of 12.5Gbps, the maximum transmission distance is only 15 meters. Furthermore, due to the use of 8b / 10b encoding, the protocol overhead is significant; for example, at a line speed of 12.5Gbps, only 10Gbps of effective bandwidth is available. For instance, a line scan camera using the CXP12-1 interface with a resolution of 16384 and a bit depth of 8bit has a maximum line frequency of no more than 76.3K.

[0003] Chinese Patent Publication No. CN115174827A discloses a signal transmission method and system. A first conversion device and a second conversion device are deployed between a camera and a data acquisition card. The first and second conversion devices are connected via optical fiber. The first conversion device receives CXP electrical signals sent by the camera, converts the CXP electrical signals into optical signals, and sends the optical signals to the second conversion device via optical fiber. The second conversion device converts the optical signals back into CXP electrical signals and sends them to the data acquisition card. This method can convert CXP electrical signals into optical signals for transmission, and transmits the optical signals via optical fiber, eliminating the need for coaxial cables. However, this solution is based on differential signal conversion and requires the transmission speed of the first CXP electrical signal to be greater than that of the third CXP electrical signal. This invention, based on the efficient encoding and decoding of the CXP protocol, uses a speed-changing mechanism at corresponding positions to achieve CXP data transmission. In this invention, both the high-speed and low-speed links of the CXP data channel use the same linear speed transmission, ensuring that the interface bit width remains consistent with traditional protocols to maintain compatibility with traditional CXP applications.

[0004] In summary, the existing technology has the following main drawbacks: (1) Traditional CXP (CoaXPress) interfaces are based on 75-ohm coaxial cable transmission. The interface chip (PHY), connectors, and cables are expensive and the transmission distance is limited. Traditional CXP communication carries signals with multiple frequency components at the same time. Its PCB layout design has extremely high requirements for impedance matching, and the PCB design is difficult and the board manufacturing cost is high.

[0005] (2) Due to the use of 8b / 10b encoding, the protocol overhead is large. For example, at a line speed of 12.5Gbps, there is only 10Gbps of effective bandwidth.

[0006] (3) Existing methods for implementing CXP protocol data transmission based on optical fiber are complex to implement and the speed of data transmission and reception is limited. Summary of the Invention

[0007] The present invention proposes an efficient CXP communication method, device, and electronic device, which can solve at least one of the above-mentioned technical problems.

[0008] To achieve the above objectives, the present invention proposes the following technical solution: An efficient CXP communication method, based on FPGA, includes: The data input CXP data channel includes: receiving optical signal processing data after speed conversion, decoding the data, and then outputting data adapted to the CXP channel through secondary speed conversion; Data is output from the CXP data channel, including: receiving CXP data after speed conversion, encoding it, and then outputting data adapted to the FPGA transceiver after a second speed conversion. The decoding process uses the same encoding / decoding protocol as the encoding process.

[0009] Furthermore, it also includes: The optical module connected to the FPGA processes the received optical signal data and transmits it to the FPGA transceiver. The FPGA transceiver processes the data to obtain the optical signal processing data.

[0010] Further, receiving the processed optical signal data after speed-adjustment includes: The processed optical signal data after speed-changing has a bit width and frequency that are adapted to the decoder mounted on the FPGA; The process of outputting data adapted to the CXP channel through secondary speed change processing includes: The bit width and frequency of the data after secondary speed-changing processing are adapted to the CXP channel.

[0011] Further, receiving the CXP data after speed-changing processing includes: The CXP data after speed-changing processing has a bit width and frequency that are adapted to the encoder mounted on the FPGA; The process of outputting data adapted to the FPGA transceiver through secondary speed conversion includes: The bit width and frequency of the data after secondary speed-changing processing are adapted to the FPGA transceiver.

[0012] On the other hand, this invention also proposes a high-efficiency CXP communication device, which realizes CXP communication based on an FPGA carrying a transmission, codec, and connected optical module, including: The first gearbox performs speed-changing processing on the data sent by the CXP data channel, so that the bit width and frequency of the data are adapted to the encoder; The second gearbox performs speed-changing processing on the data encoded by the encoder, so that the bit width and frequency of the data are adapted to the FPGA transceiver; the FPGA transceiver transmits the processed data to the optical module, and the optical module transmits the data to other devices. The optical module is also used to transmit the received data to the FPGA transceiver for processing. The third gearbox receives data processed by the FPGA transceiver and performs speed-changing processing on the data to adapt the bit width and frequency of the data to the decoder. The fourth transmission performs speed-changing processing on the data decoded by the decoder, so that the bit width and frequency of the data are adapted to the CXP data channel, and then transmits the data to the CXP data channel. The encoder and the decoder use the same encoding / decoding protocol.

[0013] Furthermore, the optical module includes one of SFP+, SFP, SFP28, QSFP+, and QSFP28; The encoding / decoding protocol includes one of the 64 / 66b, 128 / 130b, and 128 / 132b encoding / decoding protocols; The FPGA transceiver includes a Physical Coding Sublayer (PCS) and a Physical Media Access Layer (PMA).

[0014] Furthermore, the FPGA transceiver transmits the processed data to the optical module, including: The PCS of the FPGA transceiver does not encode the data. The PMA of the FPGA transceiver converts the data with a fixed bit width and frequency into data with a corresponding linear velocity, and transmits the data with the corresponding linear velocity to the optical module. The third transmission receives data processed by the FPGA transceiver, including: The PMA of the FPGA transceiver converts the fixed linear velocity data into data with corresponding bit width and frequency. The PCS of the FPGA transceiver does not decode the data and transmits the data with corresponding bit width and frequency to the third gearbox.

[0015] Furthermore, the CXP data channel includes a 32-bit high-speed link and an 8-bit low-speed link; the first transmission is a 32 / 64b transmission; the second and third transmissions are 64 / 66b transmissions; the fourth transmission is an 8 / 64b transmission; the encoding / decoding protocol is 64 / 66b; the optical module is an SFP+ optical module; wherein, the 32-bit high-speed link of the CXP data channel is used for transmitting data; and the 8-bit low-speed link is used for receiving data.

[0016] Furthermore, the CXP data channel includes a 32-bit high-speed link and an 8-bit low-speed link; the first transmission is an 8 / 64b transmission; the second and third transmissions are 64 / 66b transmissions; the fourth transmission is a 32 / 64b transmission; the encoding / decoding protocol is 64 / 66b; and the optical module is an SFP+ optical module. The 32-bit high-speed link of the CXP data channel is used for receiving data, and the 8-bit low-speed link is used for transmitting data.

[0017] On the other hand, the present invention also proposes an electronic device comprising: processor; Memory, which includes one or more computer program instructions; The one or more computer program instructions are stored in the memory and, when executed by the processor, implement the above-described efficient CXP communication method.

[0018] The beneficial effects of this invention are as follows: (1) This invention is based on SFP (Small Form-factor Pluggsable) + module to realize CXP communication. The cost of SFP+ connector, optical module / electrical port optical module, optical fiber / network cable is low. The PCB does not need to do 75 ohms special impedance matching, and the design difficulty is low. A transmission distance of kilometers can be achieved through optical fiber.

[0019] (2) The acquisition card and industrial camera are equipped with SFP+ modules and connected through optical fiber or other communication media. The linear speed can be selected as the traditional CXP speed, such as 10Gbps, 12.5Gbps, or any other speed, such as 1Gbps, 10.3125Gbps, 25Gbps, etc.

[0020] (3) In addition, by adopting efficient encoding and decoding protocols such as 64 / 66b and 128 / 130b, the protocol overhead is lower and higher effective bandwidth can be achieved at the same line speed. For example, when the line speed is 12.5G and 64 / 66b encoding and decoding is used, the maximum line frequency of a line scan camera with a resolution of 16384 and a bit depth of 8bit can reach 92.4K, which is more than 20% higher than the traditional CXP interface.

[0021] (4) In this invention, both high-speed and low-speed links use the same linear speed for transmission, and the interface bit width is consistent with the traditional protocol to ensure compatibility with traditional CXP applications. Attached Figure Description

[0022] Figure 1 This is a flowchart of the efficient CXP communication method in an embodiment of the present invention; Figure 2 This is a schematic diagram of the high-efficiency CXP communication device in an embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0024] This embodiment first proposes an efficient CXP communication method. It includes: The system receives optical signal data after speed-changing processing, decodes it, and then outputs data adapted to the CXP channel through a second speed-changing process. It also receives CXP data after speed-changing processing, encodes it, and then outputs data adapted to the FPGA transceiver through a second speed-changing process. The decoding and encoding processes use the same encoding and decoding protocols.

[0025] Specifically, this method implements the CXP protocol based on an FPGA-mounted transmission, codec, and optical module. See [link to relevant documentation]. Figure 1The CXP data channel is used to receive and transmit data with a fixed bit width and frequency. The data flow is divided into two processes: transmission and reception. Transmission data passes sequentially through the first gearbox, encoder, second gearbox, and FPGA transceiver, finally reaching the optical module and becoming data with the corresponding linear velocity. The optical module then transmits the data to other devices. Reception data originates from the fixed-linear-velocity data obtained by the optical module from other devices. This data passes sequentially through the FPGA transceiver, third gearbox, decoder, and fourth gearbox, finally reaching the CXP data channel and becoming data with the corresponding bit width and frequency. The optical module on the FPGA processes the received optical signal data and transmits it to the FPGA transceiver; the data obtained after processing by the FPGA transceiver is called optical signal processed data.

[0026] In the aforementioned transmission mechanism, the first transmission performs speed-changing processing on the data transmitted through the CXP data channel to adapt the bit width and frequency of the data to the encoder; the second transmission performs secondary speed-changing processing on the data encoded by the encoder to adapt the bit width and frequency of the data to the FPGA transceiver; the third transmission performs speed-changing processing on the data to adapt the bit width and frequency of the data to the decoder; and the fourth transmission performs secondary speed-changing processing on the data decoded by the decoder to adapt the bit width and frequency of the data to the CXP data channel. This transmission mechanism design ensures that both high-speed and low-speed links use the same linear speed for transmission, but the interface bit width remains consistent with traditional protocols to ensure compatibility with traditional CXP applications that adapt the high-speed transceiver interface to a bit width matching the CXP protocol interface.

[0027] The encoder and decoder in this embodiment use the same encoding / decoding protocol, which can be one of 64 / 66b, 128 / 130b, or 128 / 132b. Traditional CXP (CoaXPress) interfaces use 8b / 10b encoding, resulting in significant protocol overhead; for example, at a line speed of 12.5Gbps, only 10Gbps of effective bandwidth is achieved. The encoder and decoder of this invention employ efficient encoding / decoding protocols such as 64 / 66b, 128 / 130b, and 128 / 132b, resulting in lower protocol overhead and higher effective bandwidth at the same line speed. For example, at a line speed of 12.5Gbps and using 64 / 66b encoding / decoding, a line scan camera with a resolution of 16384 and a bit depth of 8bit can achieve a maximum line frequency of 92.4K, which is more than 20% higher than that of traditional CXP interfaces.

[0028] General-purpose FPGA high-speed transceivers support limited encoding and decoding capabilities and typically do not support the efficient encoding and decoding required for the CXP protocol in this invention. To achieve efficient encoding and decoding for CXP communication, this invention uses two gearboxes and encoding / decoding modules at the transceiver end to adapt the high-speed transceiver interface to a bit width that matches the CXP protocol interface, thus ensuring compatibility with traditional CXP protocol interface modules.

[0029] In this embodiment, the Physical Coding Sublayer (PCS) and Physical Medium Access Layer (PMA) are standard modules of FPGA high-speed transceivers. The interface between the PCS and PMA typically only has standard bit widths such as 40-bit and 64-bit, not 66-bit. For many FPGAs, the PCS layer does not carry a 64 / 66-bit codec module, or if it does, it is only suitable for the 10GBASE-R protocol and not for other protocols such as CXP. Therefore, to implement a universal high-speed codec scheme suitable for the CXP protocol, a custom module must be used outside the high-speed transceiver. Here, the PCS does not encode or decode data. The PMA is used to convert data with a fixed bit width and frequency into data with the corresponding linear velocity, or to convert data with a fixed linear velocity into data with the corresponding bit width and frequency, thus achieving the conversion between the data mode required by the optical module and the data mode required by the CXP data channel.

[0030] The optical module can be one of SFP+, SFP, SFP28, QSFP+, or QSFP28. The SFP (Small Form Factor Pluggable)+ optical module is a hot-pluggable, protocol-independent optical transceiver, typically transmitting light at wavelengths of 850nm, 1310nm, or 1550nm. Using the aforementioned optical module, the data line speed transmitted in this embodiment can be selected from traditional CXP speeds, such as 10Gbps or 12.5Gbps, or any other arbitrary speed, such as 1Gbps, 10.3125Gbps, or 25Gbps.

[0031] The CXP data channel includes a 32-bit high-speed link and an 8-bit low-speed link. As mentioned above, both the high-speed and low-speed links use the same linear speed for transmission. Both the 32-bit high-speed link and the 8-bit low-speed link can be used for data transmission and reception. For industrial cameras with the CXP interface, the 32-bit high-speed link of the CXP data channel is used for data transmission, and the 8-bit low-speed link is used for data reception. For image acquisition cards with the CXP interface, the 32-bit high-speed link of the CXP data channel is used for data reception, and the 8-bit low-speed link is used for data transmission.

[0032] Therefore, for an industrial camera with a CXP interface, an SFP+ optical module, and a linear speed of 10.3125Gbps, the first gearbox is a 32 / 64b gearbox; the second and third gearboxes are 64 / 66b gearboxes; the fourth gearbox is an 8 / 64b gearbox; the encoding / decoding protocol is 64 / 66b; the 32-bit high-speed link of the CXP data channel is used for data transmission; and the 8-bit low-speed link is used for data reception. This embodiment provides the following specific implementation method, which can be found in [reference needed]. Figure 2 The data transmission process in the process.

[0033] The data reception process is as follows: The SFP+ interface sends 10.3125Gbps line-speed data to the PMA of the FPGA transceiver, specifically the RX PMA module. The RX PMA module converts the data to 64bit-161.13MHz. The PMA to the PCS of the FPGA transceiver uses a standard 64bit interface with a clock frequency of 161.13MHz. The PCS of the FPGA transceiver, specifically the RX PCS, does not perform decoding operations and sends the 64bit-161.13MHz data to the 64 / 66b gearbox. The 64b / 66b gearbox uses methods such as asynchronous FIFO to convert the data speed to 66bit-156.25MHz, maintaining the same bandwidth, and outputs it to the 64 / 66b decoder. The 64 / 66b decoder performs 64 / 66b decoding, and the decoded data is 64bit-156.25MHz, outputting it to the 8 / 64b gearbox. (Gearbox); The 8 / 64b gearbox uses methods such as asynchronous FIFO to convert the data speed to 8bit-625MHz for subsequent CXP data channel 8-bit low-speed link reception.

[0034] The data transmission process is as follows: The CXP data channel's 32-bit high-speed link transmits data with a bandwidth of 32bit-312.5MHz. The data is first sent to a 32 / 64b gearbox; within the 32 / 64b gearbox, the data is converted to 64bit-156.25MHz using methods such as asynchronous FIFO, and then sent to a 64 / 66b encoding module; the 64 / 66b encoding module performs 64 / 66b encoding on the data, resulting in 66bit-156.25MHz data, which is then sent to the 64 / 66b gearbox; within the 64 / 66b gearbox, the data is converted to 64bit-161.13MHz using methods such as asynchronous FIFO, maintaining the same bandwidth, and then output to the FPGA transceiver's PCS, specifically the FPGA transceiver's TX PCS; the TX PCS does not perform any encoding operation and sends the data to the FPGA transceiver's PMA, specifically the TX PMA; TX... The PMA converts the data into 10.3125Gbps line speed data and sends it to the SFP+ interface.

[0035] The process is basically the same for image acquisition cards with CXP interfaces. The difference is that the 32-bit high-speed link of the CXP data channel is used to receive data, and the 8-bit low-speed link is used to send data. During data reception, the PMA of the FPGA transceiver is specifically RX PMA, and the PCS is specifically RX PCS. During data transmission, the PMA of the FPGA transceiver is specifically TX PMA, and the PCS is specifically TXPCS. The corresponding first gearbox is an 8 / 64b gearbox; the second and third gearboxes are 64 / 66b gearboxes; and the fourth gearbox is a 32 / 64b gearbox.

[0036] Based on the same inventive concept, this embodiment also proposes a high-efficiency CXP communication device, which can be found in the following details. Figure 2 This device includes a CXP-interface camera and a CXP-interface image acquisition card. It enables more efficient data communication between the CXP-interface camera and the CXP-interface image acquisition card, resulting in more efficient image data transmission. The CXP-interface camera and the CXP-interface image acquisition card are each equipped with the aforementioned optical modules, specifically a first optical module on the camera and a second optical module on the image acquisition card. The first and second optical modules are connected via optical fiber or other communication media, eliminating the reliance on 75-ohm coaxial cables with CXP interfaces for transmission.

[0037] The CXP interface camera communicates with the first optical module using the aforementioned efficient CXP communication method. The CXP interface camera transmits data via a 32-bit high-speed link in the CXP data channel and receives data via an 8-bit low-speed link in the CXP data channel. Similarly, the CXP interface image acquisition card communicates with the second optical module using the same efficient CXP communication method. The CXP interface image acquisition card transmits data via an 8-bit low-speed link in the CXP data channel and receives data via a 32-bit high-speed link in the CXP data channel.

[0038] Based on the same inventive concept, this embodiment also proposes an electronic device, which includes a processor and a memory, the memory including one or more computer program modules. The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for implementing the above-described efficient CXP communication method.

[0039] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0040] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-efficiency CXP communication method, based on FPGA, characterized in that, include: The data input CXP data channel includes: receiving optical signal processing data after speed conversion, decoding the data, and then outputting data adapted to the CXP channel through secondary speed conversion; Data is output from the CXP data channel, including: receiving CXP data after speed conversion, encoding it, and then outputting data adapted to the FPGA transceiver after a second speed conversion. The decoding process uses the same encoding / decoding protocol as the encoding process. The receiving of the processed optical signal data after speed-adjustment includes: The optical signal processing data, after being processed by the third gearbox, has a bit width and frequency that are compatible with the decoder mounted on the FPGA; The process of outputting data adapted to the CXP channel through secondary speed change processing includes: The bit width and frequency of the data after secondary gear shifting through the fourth gearbox are adapted to the CXP channel. The receiving of the CXP data after speed-changing processing includes: The CXP data, after being processed by the first gearbox, has a bit width and frequency that are compatible with the encoder mounted on the FPGA; The process of outputting data adapted to the FPGA transceiver through secondary speed conversion includes: The bit width and frequency of the data after secondary speed change processing by the second gearbox are adapted to the FPGA transceiver; The CXP data channel includes a 32-bit high-speed link and an 8-bit low-speed link; For industrial cameras with CXP interfaces, the 32-bit high-speed link of the CXP data channel is used to transmit data, and the 8-bit low-speed link is used to receive data; for image acquisition cards with CXP interfaces, the 32-bit high-speed link of the CXP data channel is used to receive data, and the 8-bit low-speed link is used to transmit data. The first transmission is a 32 / 64b transmission, the second and third transmissions are 64 / 66b transmissions, the fourth transmission is an 8 / 64b transmission, the encoding / decoding protocol is 64 / 66b, and the optical module is an SFP+ optical module.

2. The efficient CXP communication method according to claim 1, characterized in that, Also includes: The optical module connected to the FPGA processes the received optical signal data and transmits it to the FPGA transceiver. The FPGA transceiver processes the data to obtain optical signal processing data.

3. A high-efficiency CXP communication device, characterized in that, CXP communication is implemented based on an FPGA-based transmission, codec, and optical module, including: The first gearbox performs speed-changing processing on the data sent by the CXP data channel, so that the bit width and frequency of the data are adapted to the encoder; The second gearbox performs speed-changing processing on the data encoded by the encoder, so that the bit width and frequency of the data are adapted to the FPGA transceiver; the FPGA transceiver transmits the processed data to the optical module, and the optical module transmits the data to other devices. The optical module is also used to transmit the received data to the FPGA transceiver for processing. The third gearbox receives data processed by the FPGA transceiver and performs speed-changing processing on the data to adapt the bit width and frequency of the data to the decoder. The fourth transmission performs speed-changing processing on the data decoded by the decoder, so that the bit width and frequency of the data are adapted to the CXP data channel, and then transmits the data to the CXP data channel. The encoder and the decoder use the same encoding / decoding protocol. The CXP data channel includes a 32-bit high-speed link and an 8-bit low-speed link; For industrial cameras with CXP interfaces, the 32-bit high-speed link of the CXP data channel is used to transmit data, and the 8-bit low-speed link is used to receive data; for image acquisition cards with CXP interfaces, the 32-bit high-speed link of the CXP data channel is used to receive data, and the 8-bit low-speed link is used to transmit data. The first transmission is a 32 / 64b transmission, the second and third transmissions are 64 / 66b transmissions, the fourth transmission is an 8 / 64b transmission, the encoding / decoding protocol is 64 / 66b, and the optical module is an SFP+ optical module.

4. The high-efficiency CXP communication device according to claim 3, characterized in that, The optical module includes one of SFP+, SFP, SFP28, QSFP+, and QSFP28; The encoding / decoding protocol includes one of the 64 / 66b, 128 / 130b, and 128 / 132b encoding / decoding protocols; The FPGA transceiver includes a Physical Coding Sublayer (PCS) and a Physical Media Access Layer (PMA).

5. The high-efficiency CXP communication device according to claim 3, characterized in that, The FPGA transceiver transmits the processed data to the optical module, including: The PCS of the FPGA transceiver does not encode the data. The PMA of the FPGA transceiver converts the data with a fixed bit width and frequency into data with a corresponding linear velocity, and transmits the data with the corresponding linear velocity to the optical module. The third transmission receives data processed by the FPGA transceiver, including: The PMA of the FPGA transceiver converts the fixed linear velocity data into data with corresponding bit width and frequency. The PCS of the FPGA transceiver does not decode the data and transmits the data with corresponding bit width and frequency to the third gearbox.

6. The high-efficiency CXP communication device according to claim 3, characterized in that, The CXP data channel includes a 32-bit high-speed link and an 8-bit low-speed link; the first transmission is an 8 / 64b transmission; the second and third transmissions are 64 / 66b transmissions; the fourth transmission is a 32 / 64b transmission; the encoding / decoding protocol is 64 / 66b; the optical module is an SFP+ optical module; wherein, the 32-bit high-speed link of the CXP data channel is used to receive data; and the 8-bit low-speed link is used to transmit data.

7. An electronic device, characterized in that, include: processor; Memory, which includes one or more computer program instructions; The one or more computer program instructions are stored in the memory and, when executed by the processor, implement the instructions of the efficient CXP communication method according to any one of claims 1-2.

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