A memory chip and a manufacturing method thereof

Abstract

The application discloses a memory chip, a memory array area and a logic area include a bottom metal layer; a bottom conductor is arranged on the upper surface of the bottom metal layer, and the bottom metal layer is located in the projection area of the lower surface of the bottom conductor on the horizontal plane; a memory cell layer is arranged on the upper surface of the bottom conductor in the memory array area; a top via conductor is arranged on the upper surface of the bottom conductor in the logic area; and a top metal layer is arranged on the upper surface of the memory cell layer and the upper surface of the top via conductor. In the application, the bottom conductor is arranged on the bottom metal layer of the memory array area and the logic area, the bottom metal layer is located in the projection area of the lower surface of the bottom conductor on the horizontal plane, the bottom conductor directly serves as a copper diffusion barrier layer in the bottom metal layer, the bottom conductors of the two areas can be simultaneously manufactured, the current manufacturing process is compatible, and no additional operation is needed; the height difference between the two areas is reduced, and the etching difficulty is reduced. The application also provides a memory chip manufacturing method.

Description

Technical Field

[0001] This application relates to the semiconductor field, and in particular to a memory chip and a method for fabricating the same. Background Technology

[0002] The memory chip internally includes a memory array area for implementing storage functions and a logic area for implementing logic functions and other functions. In the memory array area, a memory cell layer, such as MRAM (magnetic random access memory), RRAM (resistive random access memory), bottom via conductors, bottom contacts, top contacts, and top via conductors, is placed between the top and bottom metal layers. In the logic area, only a top via conductor is placed between the top and bottom metal layers.

[0003] Due to the different structures of the memory array region and the logic region, the top via depth of the logic region is relatively large. Limited by the capabilities of metal via filling technology, this makes it difficult to reduce the interconnect size of the logic region and also limits the possibility of further increasing the height of the bottom contact. Furthermore, the memory cell layer, bottom via conductor, bottom contact, and top contact in the memory array region also result in a significant difference in the depth of the top vias between the memory array region and the logic region. If the top vias of the array region and the logic region are fabricated on the same photomask, the top via etching step would occur simultaneously in both regions, leading to a large load effect, increasing the difficulty of process control, affecting process stability, and even impacting chip yield. Additionally, published patents such as 201710858218.4 and 201711007715.X disclose the fabrication of memory chips based on bottom contacts, using SiN as a Cu diffusion barrier layer in the bottom circuit.

[0004] Therefore, how to solve the above-mentioned technical problems should be a key focus for those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a memory chip and a method for fabricating the same, so as to reduce the difficulty of manufacturing memory chips.

[0006] To address the aforementioned technical problems, this application provides a memory chip, including a memory array region and a logic region, wherein the memory array region and the logic region include:

[0007] Bottom metal layer;

[0008] A bottom conductor is disposed on the upper surface of the bottom metal layer, and the bottom metal layer is located within the projection area of ​​the lower surface of the bottom conductor in the horizontal plane;

[0009] A memory cell layer disposed on the upper surface of the bottom conductor in the memory array region;

[0010] A top through-hole conductor is provided on the upper surface of the bottom conductor in the logic area;

[0011] A top metal layer disposed on the upper surface of the storage cell layer and on the upper surface of the top through-hole conductor.

[0012] Optional, also includes:

[0013] The top via conductor is disposed between the memory cell layer and the top metal layer;

[0014] A top contact is provided between the top through-hole conductor and the storage cell layer.

[0015] Optionally, the bottom conductor is a one-piece structure formed of a single material.

[0016] Optionally, the bottom conductor includes a first conductive layer and a second conductive layer stacked from bottom to top, wherein the first conductive layer and the second conductive layer are made of different materials.

[0017] Optionally, the dimensions of the bottom conductor located in the logic area satisfy a preset relationship, wherein the preset relationship is:

[0018]

[0019] In the formula, H is the height of the bottom conductor located in the logic area, S1 is the lower surface area of ​​the bottom conductor located in the logic area, and S2 is the upper surface area of ​​the bottom conductor located in the logic area.

[0020] Optionally, the upper surface dimension of the bottom conductor is smaller than the lower surface dimension of the bottom conductor.

[0021] This application also provides a method for fabricating a memory chip, including:

[0022] Fabricate bottom metal layers located in the memory array region and the logic region, respectively;

[0023] A bottom conductor is formed on the upper surface of the bottom metal layer, and the bottom metal layer is located within the projection area of ​​the lower surface of the bottom conductor in the horizontal plane;

[0024] A memory cell layer is formed on the upper surface of the bottom conductor, and the memory cell layer located in the logic area is removed;

[0025] An etch barrier layer and a dielectric layer are deposited in the memory array region and the logic region;

[0026] Etching the etch barrier layer and the dielectric layer located in the logic region forms a top via;

[0027] A top metal layer and a top via conductor are formed in the memory cell layer and the corresponding area of ​​the top via to obtain a memory chip.

[0028] Optionally, when the bottom conductor comprises a first conductive layer and a second conductive layer made of different materials, forming the bottom conductor on the upper surface of the bottom metal layer includes:

[0029] A first conductive layer and a second conductive layer are sequentially formed on the upper surface of the bottom metal layer;

[0030] Etch the second conductive layer, and stop etching at the first conductive layer;

[0031] A protective layer is deposited around the second conductive layer;

[0032] Self-aligned etching of the first conductive layer and removal of the protective layer;

[0033] A dielectric layer is deposited around the first and second conductive layers and then chemically and mechanically planarized to form the bottom conductor.

[0034] Optionally, when the bottom conductor is a one-piece structure formed of a single material, forming the bottom conductor on the upper surface of the bottom metal layer includes:

[0035] A bottom conductive layer is formed on the upper surface of the bottom metal layer;

[0036] The bottom conductive layer is etched in a time-controlled manner to form a bottom conductive layer with an undulating surface morphology;

[0037] A dielectric layer is deposited on the bottom conductive layer of the surface undulation morphology, and self-aligned etching is performed.

[0038] After etching, the dielectric layer is backfilled around the bottom conductive layer and chemically and mechanically planarized to form the bottom conductor.

[0039] Optionally, after removing the storage cell layer located in the logical area, the method further includes:

[0040] Deposit top contacts and etch barrier layers in the memory array region and the logic region;

[0041] The top contact and the etch barrier layer are etched to form the top contact and the etch barrier layer on the upper surface of the memory cell layer;

[0042] Accordingly, etching the etch barrier layer and the dielectric layer located in the logic region to form a top via includes:

[0043] Etching the dielectric layer located in the logic region, the dielectric layer of the memory array region, and the etching barrier layer forms a top via;

[0044] The formation of a top metal layer and a top via conductor in the memory cell layer and the corresponding region of the top via includes:

[0045] The area corresponding to the top via is etched to form a groove, and metal is filled in the groove and the top via to form a top metal layer and a top via conductor.

[0046] This application provides a memory chip including a memory array region and a logic region. The memory array region and the logic region include: a bottom metal layer; a bottom conductor disposed on the upper surface of the bottom metal layer, the bottom metal layer being located within the projection area of ​​the lower surface of the bottom conductor in a horizontal plane; a memory cell layer disposed on the upper surface of the bottom conductor in the memory array region; a top via conductor disposed on the upper surface of the bottom conductor in the logic region; and a top metal layer disposed on the upper surface of the memory cell layer and the upper surface of the top via conductor.

[0047] As can be seen, the memory chip in this application has a bottom conductor on the bottom metal layer of the memory array area and the logic area. The bottom metal layer is located in the projection area of ​​the bottom surface of the bottom conductor on the horizontal plane. That is, the bottom conductor directly serves as a copper diffusion barrier layer in the bottom metal layer. The bottom conductor of the logic area can be fabricated at the same time as the memory array area, which can be perfectly compatible with the current manufacturing process without additional operations. It can still be applied even if the basic manufacturing process is changed to a certain extent. At the same time, it reduces the height difference between the top via of the logic area and the top via of the memory array area, reducing the difficulty of etching and thin film processing.

[0048] In addition, this application also provides a method for fabricating a memory chip with the above advantages. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of the structure of a memory chip in related technologies;

[0051] Figure 2 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application;

[0052] Figure 3 This is a schematic diagram of another memory chip structure provided in an embodiment of this application;

[0053] Figure 4 This is a flowchart illustrating a method for fabricating a memory chip, as provided in an embodiment of this application.

[0054] Figures 5 to 9 A process flow diagram of a memory chip provided in an embodiment of this application;

[0055] Figure 10 A flowchart illustrating another method for fabricating a memory chip provided in this application embodiment;

[0056] Figures 11 to 14 This is a process flow diagram of another memory chip provided in an embodiment of this application. Detailed Implementation

[0057] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0058] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0059] A schematic diagram of the structure of a memory chip in related technologies is shown below. Figure 1 As shown, it can be divided into a storage array area and a logic area. The storage array area includes a bottom metal layer 1, a bottom via conductor 7, a bottom contact 8, a storage cell layer 3, a top contact 6, a top via conductor 4, and a top metal layer 5. The logic area includes a bottom metal layer 1, a top via dielectric 4, and a top metal layer 5.

[0060] The via depth in the top of the logic region is relatively large. Due to the limitations of the metal filling process for the top via, it is difficult to reduce the interconnect size of the logic region and also limits the possibility of increasing the height of the bottom contact. On the other hand, there is a significant difference in the depth of the top vias between the memory array region and the logic region. If the top vias of the array region and the logic region are fabricated on the same photomask, it means that the top via etching step will be performed simultaneously in the array region and the logic region, resulting in a large load effect, which increases the difficulty of process control, affects process stability, and may even affect chip yield.

[0061] In view of this, this application provides a memory chip, please refer to... Figure 2 The memory chip includes a memory array area and a logic area, wherein the memory array area and the logic area include:

[0062] Bottom metal layer 1;

[0063] A bottom conductor 2 is disposed on the upper surface of the bottom metal layer 1, and the bottom metal layer 1 is located in the projection area of ​​the lower surface of the bottom conductor 2 in the horizontal plane;

[0064] A storage cell layer 3 is disposed on the upper surface of the bottom conductor 2 in the storage array region;

[0065] A top through-hole conductor 4 is provided on the upper surface of the bottom conductor 2 in the logic area;

[0066] A top metal layer 5 is disposed on the upper surface of the storage cell layer 3 and on the upper surface of the top through-hole conductor 4.

[0067] This application does not limit the materials of the bottom metal layer 1 and the top metal layer 5, and they can be set arbitrarily. For example, the materials of the bottom metal layer 1 and the top metal layer 5 can be low-resistance materials such as copper or aluminum.

[0068] Optionally, the upper surface dimension of the bottom conductor 2 is smaller than the lower surface dimension of the bottom conductor 2. The upper surface dimension and the lower surface dimension of the bottom conductor 2 are respectively the key dimensions of the upper surface and the key dimensions of the lower surface.

[0069] It should be noted that the shape of the bottom conductor 2 is not limited in this application, as long as the critical dimension of its upper surface is smaller than the critical dimension of its lower surface, and the bottom metal layer 1 is located within the projection range of its lower surface onto the horizontal surface. For example, the cross-section of the bottom conductor 2 can be an inverted T-shape, such as... Figure 2 As shown, it can be trapezoidal or similar. The bottom conductor 2 is made of a metallic material.

[0070] Optionally, as one specific embodiment, the bottom conductor 2 is an integral structure formed of a single material. However, the construction of the bottom conductor 2 is not specifically limited in this application. As another specific embodiment, the bottom conductor 2 includes a first conductive layer and a second conductive layer stacked from bottom to top, and the first conductive layer and the second conductive layer are made of different materials.

[0071] The bottom conductor 2 has the same structure as the bottom metal layer 1 it covers. For example, when the bottom metal layer 1 is dot-shaped, the bottom conductor 2 is also dot-shaped; when the bottom metal layer 1 is strip-shaped, the bottom conductor 2 is also strip-shaped. That is, the bottom metal layer 1 described above is located within the projection area of ​​the lower surface of the bottom conductor 2 on the horizontal plane. Since the bottom conductor 2 and the bottom metal layer 1 it covers have the same structure, there is a possibility that the bottom conductor 2 and the bottom metal layer 1 may share a photomask.

[0072] The bottom conductor 2 of the logic area covers the bottom metal layer 1. The bottom conductor 2 serves both to electrically connect and to block the copper of the bottom metal layer 1.

[0073] The top via conductor 4 is formed by etching a via and then filling it with conductive material. The placement of the bottom conductor 2 in the logic area effectively reduces the via etching depth, while also reducing the etching load and the pressure on the dielectric material filling the via. The top via conductor 4 is typically made of copper and is filled using electroplating.

[0074] The storage cell layer 3 includes magnetic tunnel junctions, resistive switching devices, capacitors, etc. For details, please refer to relevant technologies, which will not be elaborated here.

[0075] It should be noted that this application does not limit whether the top via conductor 4 is included in the storage array area. Figure 2 The memory array area of ​​the shown memory chip does not include the top via conductor 4. Optional, please refer to... Figure 3 In other embodiments of this application, the memory chip further includes:

[0076] The top via conductive body 4 is disposed between the storage cell layer 3 and the top metal layer 5;

[0077] A top contact 6 is provided between the top through-hole conductor 4 and the storage cell layer 3.

[0078] This application does not limit the material of the top contact 6, and the material can be selected by the applicant. For example, the material of the top contact 6 can be a single metal material such as TaN, Ta, TiN, or Ti, or a combination of multiple metal materials, or a metal compound, etc.

[0079] The memory chip in this application has a bottom conductor 2 disposed on the bottom metal layer 1 of the memory array region and the logic region. The upper surface of the bottom conductor 2 is small and the lower surface is large. The bottom metal layer 1 is located in the projection area of ​​the lower surface of the bottom conductor 2 in the horizontal plane. That is, the bottom conductor 2 directly serves as a copper diffusion barrier layer in the bottom metal layer 1. The bottom conductor 2 of the logic region can be fabricated simultaneously with the memory array region, which can perfectly accommodate the current fabrication process without additional operations, and can still be applied even if the basic fabrication process is changed. At the same time, reducing the height difference between the top vias of the logic region and the top vias of the memory array region reduces the difficulty of etching and thin film processing. In addition, the memory chip of this application does not have a bottom via conductor, further reducing the process difficulty and cost.

[0080] Based on any of the above embodiments, in one embodiment of this application, the dimensions of the bottom conductor 2 located in the logic area satisfy a preset relationship, wherein the preset relationship is:

[0081]

[0082] In the formula, H is the height of the bottom conductor 2 located in the logic area, S1 is the lower surface area of ​​the bottom conductor 2 located in the logic area, and S2 is the upper surface area of ​​the bottom conductor 2 located in the logic area.

[0083] When the size of the bottom conductor 2 of the logic region satisfies formula (1), the resistance of the bottom conductor 2 of the logic region will be less than a resistance threshold, thereby avoiding logic delay.

[0084] This application also provides a method for fabricating a memory chip; please refer to [reference needed]. Figure 4 The method includes:

[0085] Step S101: Prepare the bottom metal layers located in the memory array region and the logic region, respectively.

[0086] Please refer to the following steps. Figure 5 The bottom metal layer 1 of the storage array area and the logic area is simultaneously fabricated using photolithography patterning technology.

[0087] Step S102: A bottom conductor is formed on the upper surface of the bottom metal layer, wherein the bottom metal layer is located within the projection area of ​​the lower surface of the bottom conductor in the horizontal plane.

[0088] Please refer to the following steps. Figure 6 The bottom conductors 2 of the storage array area and the logic area are simultaneously fabricated using photolithography patterning technology.

[0089] Step S103: Form a memory cell layer on the upper surface of the bottom conductor and remove the memory cell layer located in the logic area.

[0090] First, memory cell layer 3 is fabricated simultaneously in the memory array region and the logic region. Then, the memory cell layer in the logic region is etched away, leaving memory cell layer 3 in the memory array region. An antioxidant layer (which also serves as a barrier layer for top via etching) is deposited in situ, and the etched structure is subjected to chemical mechanical planarization to expose the top and form conductive contacts. Figure 7 As shown.

[0091] Step S104: Deposit an etch barrier layer and a dielectric layer in the storage array region and the logic region.

[0092] Schematic diagram of the etch barrier layer 9 and dielectric layer 10 after deposition (see reference) Figure 8 .

[0093] Step S105: Etch the etch barrier layer and the dielectric layer located in the logic region to form a top via.

[0094] Please refer to Figure 9 A top via is formed only in the logic area.

[0095] Step S106: A top metal layer and a top via conductor are formed in the memory cell layer and the corresponding area of ​​the top via to obtain a memory chip.

[0096] Both the storage array area and the logic area have top metal layers, resulting in... Figure 2 The memory chip shown.

[0097] The formation process of the bottom conductor will be described below according to the different structures of the bottom conductor.

[0098] When the bottom conductor comprises a first conductive layer and a second conductive layer of different materials, forming the bottom conductor on the upper surface of the bottom metal layer includes:

[0099] Step S201: A first conductive layer and a second conductive layer are sequentially formed on the upper surface of the bottom metal layer;

[0100] Step S202: Etch the second conductive layer, and stop etching at the first conductive layer;

[0101] Step S203: Deposit a protective layer around the second conductive layer;

[0102] Step S204: Self-aligned etching of the first conductive layer;

[0103] Step S205: Deposit a dielectric layer around the first conductive layer and the second conductive layer, and perform chemical mechanical planarization to form the bottom conductor.

[0104] When the bottom conductor is a one-piece structure formed of a single material, forming the bottom conductor on the upper surface of the bottom metal layer includes:

[0105] Step S301: Form a bottom conductive layer on the upper surface of the bottom metal layer;

[0106] Step S302: Time-controlled etching of the bottom conductive layer to form a bottom conductive layer with undulating surface morphology;

[0107] Step S303: Deposit a dielectric layer on the bottom conductive layer of the surface undulation morphology and perform self-aligned etching;

[0108] Step S304: Backfill the dielectric layer around the bottom conductive layer after etching and perform chemical mechanical planarization to form the bottom conductor.

[0109] The memory chip fabrication method in this application involves setting a bottom conductor on the bottom metal layer of the memory array region and the logic region. The bottom conductor has a small upper surface and a large lower surface. The bottom metal layer is located within the projection area of ​​the lower surface of the bottom conductor on the horizontal plane. That is, the bottom conductor directly serves as a copper diffusion barrier layer in the bottom metal layer. The bottom conductor of the logic region can be fabricated simultaneously with the memory array region, which is perfectly compatible with the current fabrication process without additional operations. It is also applicable even if the basic fabrication process is modified. At the same time, reducing the height difference between the top via conductor of the logic region and the top via conductor of the memory array region reduces the difficulty of etching and thin film processing.

[0110] This application also provides another method for fabricating memory chips; please refer to [link / reference]. Figure 10 The method includes:

[0111] Step S401: Prepare the bottom metal layers located in the memory array region and the logic region, respectively.

[0112] Step S402: A bottom conductor is formed on the upper surface of the bottom metal layer, wherein the bottom metal layer is located within the projection area of ​​the lower surface of the bottom conductor in the horizontal plane.

[0113] Step S403: Form a memory cell layer on the upper surface of the bottom conductor and remove the memory cell layer located in the logic area.

[0114] Please refer to the above embodiment for steps S401 to S403, which will not be described in detail here.

[0115] Step S404: Deposit top contacts and etch barrier layers in the storage array region and the logic region.

[0116] Please refer to the following steps. Figure 11Both the storage array region and the logic region are formed with a top contact 6 and an etch barrier layer 9. The top contact 6 of the storage array region is in contact with the storage cell layer 3.

[0117] Step S405: Etch the top contact and the etch barrier layer to form the top contact and the etch barrier layer on the upper surface of the memory cell layer.

[0118] Please refer to the following steps. Figure 12 After etching, only the top contact 6 and the etching barrier layer 9 remain in the storage array area.

[0119] Step S406: Deposit a dielectric layer in the storage array area and the logic area.

[0120] Please refer to the following steps. Figure 13 The upper surface of the dielectric layer 10 is subjected to chemical mechanical planarization treatment.

[0121] Step S407: Etch the dielectric layer located in the logic region, the dielectric layer of the memory array region, and the etch barrier layer to form a top via.

[0122] Please refer to the following steps. Figure 14 Both the logic area and the storage array area have top vias.

[0123] Step S408: Etch the area corresponding to the top via to form a groove, and fill the groove and the top via with metal to form a top metal layer and a top via conductor to obtain a memory chip.

[0124] Simultaneously, the regions corresponding to the top via conductors in the logic region and memory array region are etched and filled with metal to form a top metal layer, resulting in... Figure 3 The memory chip shown.

[0125] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0126] The foregoing has provided a detailed description of the memory chip and its fabrication method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the methods and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A memory chip, comprising a memory array region and a logic region, characterized in that, The storage array area and the logical area include: Bottom metal layer; A bottom conductor is disposed on the upper surface of the bottom metal layer, the bottom metal layer being located within the projection area of ​​the lower surface of the bottom conductor in the horizontal plane; the upper surface dimension of the bottom conductor is smaller than the lower surface dimension of the bottom conductor; the bottom conductor disposed in the logic area simultaneously serves to electrically connect to and block the copper of the bottom metal layer; a memory cell layer is disposed on the upper surface of the bottom conductor in the memory array area; A top through-hole conductor is provided on the upper surface of the bottom conductor in the logic area; A top metal layer disposed on the upper surface of the memory cell layer and on the upper surface of the top through-hole conductor; The dimensions of the bottom conductor located in the logic area satisfy a preset relationship, wherein the preset relationship is: ； In the formula, H is the height of the bottom conductor located in the logic area, S1 is the lower surface area of ​​the bottom conductor located in the logic area, and S2 is the upper surface area of ​​the bottom conductor located in the logic area.

2. The memory chip as described in claim 1, characterized in that, Also includes: The top via conductor is disposed between the memory cell layer and the top metal layer; A top contact is provided between the top through-hole conductor and the storage cell layer.

3. The memory chip as described in claim 1, characterized in that, The bottom conductor is a one-piece structure formed from a single material.

4. The memory chip as described in claim 1, characterized in that, The bottom conductor includes a first conductive layer and a second conductive layer stacked from bottom to top, and the first conductive layer and the second conductive layer are made of different materials.

5. A method for fabricating a memory chip, characterized in that, include: Fabricate bottom metal layers located in the memory array region and the logic region, respectively; A bottom conductor is formed on the upper surface of the bottom metal layer, and the bottom metal layer is located within the projection area of ​​the lower surface of the bottom conductor in the horizontal plane; the upper surface dimension of the bottom conductor is smaller than the lower surface dimension of the bottom conductor. The bottom conductor located in the logic area simultaneously serves to electrically connect to and block the copper in the bottom metal layer. A memory cell layer is formed on the upper surface of the bottom conductor, and the memory cell layer located in the logic area is removed; An etch barrier layer and a dielectric layer are deposited in the memory array region and the logic region; Etching the etch barrier layer and the dielectric layer located in the logic region forms a top via; A top metal layer and a top via conductor are formed in the memory cell layer and the corresponding region of the top via to obtain a memory chip. The dimensions of the bottom conductor located in the logic area satisfy a preset relationship, wherein the preset relationship is: ； In the formula, H is the height of the bottom conductor located in the logic area, S1 is the lower surface area of ​​the bottom conductor located in the logic area, and S2 is the upper surface area of ​​the bottom conductor located in the logic area.

6. The method for fabricating a memory chip as described in claim 5, characterized in that, When the bottom conductor comprises a first conductive layer and a second conductive layer of different materials, forming the bottom conductor on the upper surface of the bottom metal layer includes: A first conductive layer and a second conductive layer are sequentially formed on the upper surface of the bottom metal layer; Etch the second conductive layer, and stop etching at the first conductive layer; A protective layer is deposited around the second conductive layer; Self-aligned etching of the first conductive layer and removal of the protective layer; A dielectric layer is deposited around the first and second conductive layers and then chemically and mechanically planarized to form the bottom conductor.

7. The method for fabricating a memory chip as described in claim 5, characterized in that, When the bottom conductor is a one-piece structure formed of a single material, forming the bottom conductor on the upper surface of the bottom metal layer includes: A bottom conductive layer is formed on the upper surface of the bottom metal layer; The bottom conductive layer is etched in a time-controlled manner to form a bottom conductive layer with an undulating surface morphology; A dielectric layer is deposited on the bottom conductive layer of the surface undulation morphology, and self-aligned etching is performed. After etching, the dielectric layer is backfilled around the bottom conductive layer and chemically and mechanically planarized to form the bottom conductor.

8. The method for fabricating a memory chip according to any one of claims 5 to 7, characterized in that, After removing the storage cell layer located in the logical area, the process further includes: Deposit top contacts and etch barrier layers in the memory array region and the logic region; The top contact and the etch barrier layer are etched to form the top contact and the etch barrier layer on the upper surface of the memory cell layer; Accordingly, etching the etch barrier layer and the dielectric layer located in the logic region to form a top via includes: Etching the dielectric layer located in the logic region, the dielectric layer of the memory array region, and the etching barrier layer forms a top via; The formation of a top metal layer and a top via conductor in the memory cell layer and the corresponding region of the top via includes: The area corresponding to the top via is etched to form a groove, and metal is filled in the groove and the top via to form a top metal layer and a top via conductor.

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