Depth buffer directional tracking based on gpu hardware

Abstract

The present disclosure relates to methods and apparatus for graphics processing. An example method generally includes receiving, at a graphics processing unit (GPU), a plurality of commands corresponding to a plurality of draws spanning a frame, each command of the plurality of commands indicating a depth test direction relative to a low resolution z (LRZ) buffer for a corresponding draw. The method generally includes maintaining, at the GPU, an LRZ state buffer to store the corresponding depth test direction for a first command in time of the plurality of commands processed by the GPU. The method generally includes disabling, at the GPU, use of the LRZ buffer for depth testing for any remaining commands of the plurality of commands that have not been processed after processing a command of the plurality of commands having a different depth test direction than the corresponding depth test direction stored in the LRZ state buffer.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit and priority of U.S. non-provisional application No. 17 / 064,188, filed on October 6, 2020, which has been assigned to the assignee of this application and whose entire contents are expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0003] In summary, this disclosure relates to processing systems, and more specifically, to one or more techniques for graphics processing. Background Technology

[0004] Computing devices typically utilize graphics processing units (GPUs) to accelerate the rendering of graphics data for display. Such devices can include, for example, computer workstations, mobile phones (such as so-called smartphones), embedded systems, personal computers, tablet computers, and video game consoles. A GPU executes a graphics processing pipeline, which includes one or more processing stages that work together to execute graphics processing commands and output frames. A central processing unit (CPU) controls the operation of the GPU by issuing one or more graphics processing commands to it. Modern CPUs are typically capable of executing multiple applications concurrently, each of which may require the GPU to utilize its resources during execution. Devices that provide content for visual presentation on a display typically include GPUs.

[0005] Typically, a device's GPU is configured to execute processes within a graphics processing pipeline. However, with the advent of wireless communication and smaller handheld devices, there has been an increasing demand for improved graphics processing. Summary of the Invention

[0006] The following provides a brief overview of one or more aspects to offer a basic understanding of such aspects. This overview is not a comprehensive summary of all anticipated aspects, nor is it intended to identify key elements of all aspects, nor to depict the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed descriptions that follow.

[0007] In one aspect of this disclosure, a method, a computer-readable medium, an apparatus, and a computing device are provided.

[0008] In some aspects, an example method generally includes: receiving at a graphics processing unit (GPU) a plurality of commands corresponding to a plurality of draws spanning frames, each of the plurality of commands indicating a depth test direction relative to a low-resolution depth (LRZ) buffer for the corresponding draw. The method generally includes: maintaining an LRZ state buffer at the GPU to store the corresponding depth test direction for a first command in time among the plurality of commands processed by the GPU. The method generally includes: at the GPU, after processing a command among the plurality of commands having a depth test direction different from the corresponding depth test direction stored in the LRZ state buffer, disabling the use of the LRZ buffer for depth testing for any remaining unprocessed commands among the plurality of commands.

[0009] In some aspects, an example apparatus generally includes an LRZ buffer, an LRZ state buffer, and a GPU. The GPU can be configured to receive a plurality of commands corresponding to a plurality of draws spanning frames, each of the plurality of commands indicating a depth test direction relative to the LRZ buffer for the corresponding draw. The GPU can be configured to maintain the LRZ state buffer to store the corresponding depth test direction for a temporally first command among the plurality of commands processed by the GPU. The GPU can be configured to disable the use of the LRZ buffer for depth testing for any remaining unprocessed commands among the plurality of commands after processing a command having a depth test direction different from the corresponding depth test direction stored in the LRZ state buffer.

[0010] In some aspects, an example computing device generally includes a central processing unit (CPU), a display, an LRZ buffer, an LRZ state buffer, and a GPU. The GPU is configured to receive a plurality of commands from the CPU, the plurality of commands corresponding to a plurality of draws spanning frames for display on the display, each of the plurality of commands indicating a depth test direction relative to the LRZ buffer for the corresponding draw. The GPU is configured to maintain the LRZ state buffer to store the corresponding depth test direction for a first command in time among the plurality of commands processed by the GPU. The GPU is configured to disable the use of the LRZ buffer for depth testing for any remaining unprocessed commands among the plurality of commands after processing a command having a depth test direction different from the corresponding depth test direction stored in the LRZ state buffer.

[0011] Details of one or more examples of this disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of this disclosure will be apparent from the specification, drawings, and claims. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating an example content generation system based on certain aspects of this disclosure.

[0013] Figure 2 An example GPU is shown in accordance with certain aspects of this disclosure.

[0014] Figure 3 Example images or surfaces are shown in accordance with certain aspects of this disclosure.

[0015] Figure 4 A flowchart illustrating example operations for low-resolution (LRZ) depth testing by a graphics processing unit (GPU) in accordance with certain aspects of this disclosure is shown. Detailed Implementation

[0016] Traditionally, the software driver of a graphics processing system can handle some aspects of graphics processing, including enabling / disabling the low-resolution (LRZ) depth buffer for LRZ depth testing based on orientation. In some aspects, the frame to be displayed is divided into, for example, fixed-size tiles (or bins). Each tile (or bin) can have a corresponding entry in the LRZ depth buffer, indicating the furthest depth value used for that tile / bin. When the GPU processes a draw command for an element (e.g., a triangle) within a bin for rendering, a depth test can be performed to determine if the element is visible (e.g., whether it overlaps with another element), and thus whether the element needs to be rendered and / or whether the draw command is processed if it indicates that depth testing is enabled. For example, the depth value of the draw command can be compared to the depth value stored in the LRZ depth buffer, and if visible, the element is rendered.

[0017] The drawing command further indicates the depth test direction relative to the LRZ buffer for the corresponding draw. If the depth test direction changes between subsequent draws within a partition, it may be necessary to disable the use of the LRZ depth buffer, as the change in direction means the LRZ depth buffer can no longer be used to compare the visibility of other draws. Traditionally, software drivers track changes in the depth test direction and include instructions on enabling or disabling the use of the LRZ depth buffer in the drawing commands for the GPU.

[0018] However, many GPUs include multiple threads for processing drawing commands sent to the GPU by the driver (e.g., accessed by a multi-threaded application programming interface (API)). For example, the GPU may draw drawing commands in parallel from multiple different command buffers. Therefore, the driver may not have prior information about the order in which the GPU will process certain drawing commands, and thus may be unable to predict when to enable / disable the use of the LRZ depth buffer.

[0019] Based on the aspects discussed in this article, the determination of whether to enable / disable the use of the LRZ depth buffer can alternatively be performed by the GPU based on the order of its actual processing commands. Therefore, if the GPU is the entity that handles depth buffer orientation tracking, the driver may no longer need to track the depth buffer orientation and can always simply indicate that the LRZ depth buffer is enabled in the drawing command.

[0020] The following description, with reference to the accompanying drawings, provides a more complete picture of various aspects of the systems, apparatuses, computer program products, and methods. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of this disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether that aspect is implemented independently of or in combination with other aspects of this disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. Furthermore, the scope of this disclosure is intended to cover such apparatuses or methods practiced using structures, functions, or structures and functions other than or different from the aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of the claims.

[0021] While various aspects are described herein, numerous variations and substitutions of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of the aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to a particular benefit, use, or objective. Rather, the aspects of this disclosure are intended to be broadly applicable to various graphics techniques, system configurations, etc., some of which are illustrated by way of example in the accompanying drawings and the description below. The detailed description and drawings are illustrative only and not limiting of this disclosure, the scope of which is defined by the appended claims and their equivalents.

[0022] Several aspects are given with reference to various apparatuses and methods. These apparatuses and methods are described in detail below and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0023] For example, an element, or any part of an element, or any combination of elements, can be implemented as a "processing system," which includes one or more processors (which may also be referred to as processing units). Examples of processors include: microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, system-on-a-chip (SoCs), baseband processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout this disclosure. One or more processors in a processing system can execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, software can be broadly interpreted to mean instructions, instruction sets, code, code segments, program code, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc. The term can be used to refer to software. As described herein, one or more techniques may involve applications, i.e., software, configured to perform one or more functions. In such examples, the application may be stored on memory, such as on-chip memory of a processor, system memory, or any other memory. The hardware described herein (such as a processor) may be configured to execute the application. For example, an application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein. For example, the hardware may access the code from memory and execute the code accessed from memory to perform one or more techniques described herein. In some examples, components are identified in this disclosure. In such examples, a component may be hardware, software, or a combination thereof. A component may be a single component or a subcomponent of a single component.

[0024] Accordingly, in one or more examples described herein, the described functionality can be implemented in hardware, software, or any combination thereof. If implemented in software, the functionality can be stored or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media can be any available medium accessible by a computer. By way of example, and not limitation, such computer-readable media can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of computer-readable media of the types described above, or any other medium that can be used to store computer-executable code in the form of instructions or data structures accessible by a computer.

[0025] In summary, this disclosure describes techniques for using a graphics processing pipeline in a single device or multiple devices, or a single device with multiple pipelines, to improve the rendering of graphics content and / or reduce the load on processing units (i.e., any processing unit, such as a GPU, configured to perform one or more of the techniques described herein). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0026] As used herein, instances of the term "content" can refer to "graphic content," "image," or vice versa. This is true regardless of whether the term is used as an adjective, noun, or other part of speech. In some examples, as used herein, the term "graphic content" can refer to content produced by one or more processes in a graphics processing pipeline. In some examples, as used herein, the term "graphic content" can refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphic content" can refer to content produced by a graphics processing unit.

[0027] In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform display processing. Graphical content can be processed to become display content. For example, a graphics processing unit may output graphical content, such as frames, to a buffer (which may be referred to as a frame buffer). The display processing unit may read graphical content (such as one or more frames) from the buffer and perform one or more display processing techniques on it to generate display content. For example, the display processing unit may be configured to perform compositing on one or more rendering layers to generate frames. As another example, the display processing unit may be configured to composite, blend, or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling (e.g., zooming in or out) on frames. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have been blended together to form a frame, i.e., a frame comprises two or more layers, and frames comprising two or more layers may subsequently be blended.

[0028] Figure 1 This is a block diagram illustrating an example content generation system 100 configured to implement one or more technologies of this disclosure. The content generation system 100 includes a device 104. Device 104 may include one or more components or circuitry for performing the various functions described herein. In some examples, one or more components of device 104 may be components of a System-on-a-Chip (SOC). Device 104 may include one or more components configured to perform one or more technologies of this disclosure. In the illustrated example, device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, device 104 may include multiple optional components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. Reference to display 131 may refer to one or more displays 131. For example, display 131 may include a single display or multiple displays. Display 131 may include a first display and a second display. The first display may be a left-eye display, while the second display may be a right-eye display. In some examples, the first and second displays may receive different frames for presentation thereon. In other examples, the first and second displays may receive the same frames used for rendering on them. In further examples, the results of graphics processing may not be displayed on the devices; for example, the first and second displays may not receive any frames used for rendering on them. Alternatively, frames or graphics processing results may be sent to another device. In some respects, this may be referred to as split rendering.

[0029] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in a graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor (e.g., display processor 127) to perform one or more display processing techniques on one or more frames generated by processing unit 120 before being rendered by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise render the frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: liquid crystal display (LCD), plasma display, organic light-emitting diode (OLED) display, projection display device, augmented reality display device, virtual reality display device, head-mounted display, or any other type of display device.

[0030] Memory external to processing unit 120 and content encoder / decoder 122 (such as system memory 124) may be accessible to processing unit 120 and content encoder / decoder 122. For example, processing unit 120 and content encoder / decoder 122 may be configured to read from and / or write to external memory (such as system memory 124). Processing unit 120 and content encoder / decoder 122 may be communicatively coupled to system memory 124 via a bus. In some examples, processing unit 120 and content encoder / decoder 122 may be communicatively coupled to each other via a bus or different connections.

[0031] Content encoder / decoder 122 can be configured to receive graphic content from any source, such as system memory 124 and / or communication interface 126. System memory 124 can be configured to store the received encoded or decoded graphic content. Content encoder / decoder 122 can be configured to receive, for example, encoded or decoded graphic content in the form of encoded pixel data from system memory 124 and / or communication interface 126. Content encoder / decoder 122 can be configured to encode or decode any graphic content.

[0032] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media or optical storage media, or any other type of memory.

[0033] According to some examples, internal memory 121 or system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or a propagating signal. However, the term "non-transitory" should not be construed as meaning that internal memory 121 or system memory 124 is not movable or that its contents are static. As one example, system memory 124 may be removed from device 104 and moved to another device. As another example, system memory 124 may be not removable from device 104.

[0034] Processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, processing unit 120 may be integrated into the motherboard of device 104. In some examples, processing unit 120 may reside on a graphics card mounted in a port on the motherboard of device 104, or may otherwise be incorporated into a peripheral device configured to interoperate with device 104. Processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, processing unit 120 may store instructions for software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121) and may use one or more processors to execute instructions in hardware to perform the technology of this disclosure. Any of the foregoing, including hardware, software, and combinations of hardware and software, can be considered as one or more processors.

[0035] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 can be integrated into the motherboard of device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is implemented in part in software, the content encoder / decoder 122 may store instructions for software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123), and may use one or more processors to execute instructions in hardware to perform the technology of this disclosure. Any of the foregoing, including hardware, software, combinations of hardware and software, etc., can be considered as one or more processors.

[0036] In some aspects, the content generation system 100 may include an optional communication interface 126. Communication interface 126 may include a receiver 128 and a transmitter 130. Receiver 128 may be configured to perform any of the receiving functions described herein with respect to device 104. Additionally, receiver 128 may be configured to receive information (e.g., eye or head position information, rendering commands, or location information) from another device. Transmitter 130 may be configured to perform any of the transmitting functions described herein with respect to device 104. For example, transmitter 130 may be configured to send information to another device that may include a request for content. Receiver 128 and transmitter 130 may be combined into transceiver 132. In such an example, transceiver 132 may be configured to perform any of the receiving and / or transmitting functions described herein with respect to device 104.

[0037] Refer again Figure 1In some aspects, the graphics processing pipeline 107 may include a low-resolution (LRZ) disable component 198 configured to disable the use of the LRZ buffer for depth testing. The LRZ disable component 198 may also be configured to receive multiple commands corresponding to multiple draws spanning frames, each of the multiple commands indicating a depth testing direction relative to the LRZ buffer for the corresponding draw. The LRZ disable component 198 may also be configured to maintain an LRZ state buffer to store the corresponding depth testing direction for a temporally first command among the multiple commands processed by the GPU. The LRZ disable component 198 may be configured to disable the use of the LRZ buffer for depth testing for any remaining unprocessed commands among the multiple commands after processing a command having a depth testing direction different from the corresponding depth testing direction stored in the LRZ state buffer. The LRZ disable component 198 may also be configured to compare the corresponding depth testing direction of each of one or more commands including the command with the corresponding depth testing direction stored in the LRZ state buffer, wherein disabling the use of the LRZ buffer is in response to the comparison. The LRZ disabling component 198 can also be configured to disable the use of the LRZ buffer by disabling the use of the LRZ buffer for the command and for each of the multiple commands that are processed after the command in time.

[0038] As described herein, a device such as device 104 can refer to any device, apparatus, or system configured to perform one or more of the techniques described herein. For example, a device can be a server, base station, user equipment, client device, station, access point, computer (e.g., personal computer, desktop computer, laptop computer, tablet computer, computer workstation, or mainframe computer), end product, apparatus, telephone, smartphone, server, video game platform or console, handheld device (e.g., portable video game device or personal digital assistant (PDA)), wearable computing device (e.g., smartwatch, augmented reality device, or virtual reality device), non-wearable device, display or display device, television, set-top box, intermediate network device, digital media player, video streaming device, content streaming device, in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the techniques described herein. The processes described herein may be described as being performed by a specific hardware component (e.g., GPU), but in further embodiments, they may be performed using other hardware components (e.g., CPU) consistent with the disclosed embodiments.

[0039] GPUs can process various types of data or data packets within the GPU pipeline. For example, in some aspects, a GPU can process two types of data or data packets, such as context register packets and draw call data. Context register packets can be a collection of global state information that manages how the graphics context will be processed, such as information about global registers, shaders, or constant data. For example, a context register packet may include information about the color format. In some aspects of context register packets, there may be bits indicating which workload belongs to the context register. Furthermore, there may be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program may describe a specific operation, such as a color mode or color format. Therefore, context registers can define multiple states of the GPU.

[0040] Context states can be used to determine how individual processing units (e.g., vertex extractors (VFDs), vertex shaders (VSs), shader processors, or geometry processors) operate, and / or in what modes they operate. For this purpose, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads in the pipeline, such as vertex or pixel workloads, based on the context register definitions of modes or states. Certain processing units (e.g., VFDs) can use these states to determine certain functions, such as how to assemble vertices. Because these modes or states can change, the GPU may need to modify the corresponding context. Furthermore, the workload corresponding to a mode or state can follow the changing mode or state.

[0041] Figure 2 An example GPU 200 is shown, employing one or more technologies according to this disclosure. (Example:) Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z-process engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a render backend (RB) 236, an L2 cache (UCHE) 238, a virtual split cache (VSC) 239, and system memory 240. Although Figure 2 The GPU 200 is shown to include processing units 220-238, but the GPU 200 may include multiple additional processing units. Furthermore, processing units 220-238 are merely examples, and any combination or order of processing units may be used by the GPU in accordance with this disclosure. The GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0042] like Figure 2 As shown, the GPU can utilize a CP (e.g., CP 210) or a hardware accelerator to resolve the command buffer into context register packets (e.g., context register packet 260) and / or draw call data packets (e.g., draw call packet 212). CP 210 can then send the context register packet 260 or the draw call data packet 212 to a processing unit or block within the GPU via a separate path. Furthermore, the command buffer 250 can alternate between different states of the context registers and draw calls. For example, the command buffer can be constructed as follows: context register of context N, draw call of context N, context register of context N+1, and draw call of context N+1.

[0043] GPUs can render images in a variety of different ways. In some instances, GPUs can render images using either binning or tile-based rendering. In a tile-based rendering GPU, an image can be divided or split into different parts or tiles (also known as partitions). After the image is partitioned, each part or tile can be rendered individually. A tile-based rendering GPU can divide a computer graphics image into a grid format, so that each part of the grid (i.e., a tile) is rendered individually. In some aspects, an image can be divided into different partitions or tiles during a binning pass. Furthermore, in a binning pass, different primitives can be colored in certain partitions (e.g., using draw calls). In some aspects, a visibility stream can be constructed during a binning pass, where visible primitives or draw calls can be identified.

[0044] In some aspects, the GPU can apply the drawing or rendering process to different partitions or tiles. For example, the GPU can render for one partition and then perform all drawing for the primitives or pixels within that partition. Furthermore, the GPU can render for another partition and perform drawing for the primitives or pixels within that partition. Therefore, in some aspects, there may be a small number of partitions (e.g., four partitions) that cover all drawing on a surface. Additionally, the GPU can loop through all drawing within a partition, but perform drawing only for visible drawing calls (i.e., drawing calls that include visible geometry). In some aspects, such as in a partitioned path, a visibility stream can be generated to determine the visibility information of each primitive in the image or scene. For example, the visibility stream can identify whether a primitive is visible. In some aspects, this information can be used, for example, to remove invisible primitives in the rendering path. Furthermore, at least some of the primitives identified as visible can be rendered in the rendering path.

[0045] In some aspects of tile-based rendering, multiple processing stages or pathways can exist. For example, rendering can be performed in two pathways, such as a visibility or partition visibility pathway and a rendering or partition rendering pathway. During the visibility pathway, the GPU can input a rendering workload, record the positions of primitives or triangles, and then determine which primitives or triangles fall into which partition or region. In some aspects of the visibility pathway, the GPU can also identify or mark the visibility of each primitive or triangle in the visibility stream. During the rendering pathway, the GPU can input a visibility stream and process one partition or region at a time. In some aspects, the visibility stream can be analyzed to determine which primitives or primitive vertices are visible or invisible. Therefore, visible primitives or primitive vertices can be processed. By doing so, the GPU can reduce the unnecessary workload of processing or rendering invisible primitives or triangles.

[0046] In some aspects, certain types of primitive geometry, such as position-only geometry, can be processed during the visibility path. Furthermore, primitives can be classified into different partitions or regions based on their position or location. In some instances, classifying primitives or triangles into different partitions can be performed by determining visibility information for those primitives or triangles. For example, the GPU can determine the visibility information for each primitive in each partition or region or write it to, for example, system memory. This visibility information can be used to determine or generate a visibility stream. In the rendering path, the primitives in each partition can be rendered separately. In these instances, the visibility stream can be retrieved from memory used to discard primitives that are not visible to that partition.

[0047] GPUs or GPU architectures can offer a variety of different options for rendering, such as software rendering and hardware rendering. In software rendering, the driver or CPU can copy the entire frame geometry by processing each view at a time. Furthermore, several different states can change depending on the view. Therefore, in software rendering, the software can copy the entire workload by changing some states that can be used for rendering for each viewpoint in the image. In some aspects, there can be increased overhead because the GPU may submit the same workload multiple times for each viewpoint in the image. In hardware rendering, the hardware or GPU can be responsible for copying or processing the geometry for each viewpoint in the image. Therefore, the hardware can manage the copying or processing of primitives or triangles for each viewpoint in the image.

[0048] Figure 3 An image or surface 300 is shown, which includes multiple primitives divided into multiple partitions. For example... Figure 3As shown, the image or surface 300 includes region 302, which includes primitives 321, 322, 323, and 324. Primitives 321, 322, 323, and 324 are divided or placed into different partitions, such as partitions 310, 311, 312, 313, 314, and 315. Figure 3 An example of tile-based rendering using multiple viewpoints is shown for primitives 321-324. For example, primitives 321-324 are located in a first viewpoint 350 and a second viewpoint 351. Therefore, a GPU that processes or renders an image or surface 300 including region 302 can utilize multiple viewpoints or multi-view rendering.

[0049] As noted in this article, GPUs or graphics processing units can use tile-based rendering architectures to reduce power consumption or save memory bandwidth. As further stated above, this rendering method divides the scene into multiple partitions, along with visibility paths that include identifying visible triangles within each partition. Therefore, in tile-based rendering, the entire screen can be divided into multiple partitions or tiles. The scene can then be rendered multiple times, for example, once for each partition.

[0050] As noted above, the GPU can loop through each draw call within a partition and execute the visible draw calls. In some respects, draw calls falling into a given partition are considered live draw calls, while draw calls falling outside that partition are considered dead draw calls. Effectively skipping dead draw calls can reduce the hardware overhead caused by rendering the scene multiple times.

[0051] For each function of the GPU, there can be an assigned group, namely a workload group or a graphics state group. A workload or graphics state group can also include a corresponding state or context state. Therefore, each workload or graphics state group corresponding to a specific state or context state can perform the GPU's function. For example, the depth state can be one workload or graphics state group, the blending state can be another, and the fragment shader state can be yet another.

[0052] For each partition or tile, the GPU can execute all workloads or graphics state groups and extract each valid draw for that particular partition. Furthermore, the GPU can extract command streams for rendering each partition. Additionally, as noted above, the GPU can process the command streams in the visibility path. The GPU can also determine which draw calls are visible in a particular partition during the visibility path.

[0053] During the visibility path, the GPU can also construct a set of state information or context state information for each graphics state group in each draw call. In some aspects, the GPU can also construct a complete set of state information for each draw call when the CPU or software provides incremental or changing state or context state. Therefore, the CPU can transmit these incremental states or context states for workloads or graphics state groups during the visibility path. In some aspects, the command stream can be sent before each draw call is executed, for example, in the visibility path. Therefore, the command stream can be sent in the visibility path before the GPU renders or draws.

[0054] In some cases, the CPU or software can build or write a complete set of state or context state for each graphics state group between draw calls. By doing so, the CPU can help the GPU or hardware jump to the next draw call, rather than fetching a command stream for invalid draw calls. Therefore, in some respects, the CPU can build or write a complete set of state information for each graphics state group, regardless of whether the state or context state for a particular graphics state group has changed. For example, if draw calls 1-3 are invalid draw calls, in order to jump from draw call 0 to draw call 4, the CPU or software can build a complete set of state information for each graphics state group between draw calls.

[0055] To construct a complete set of state information for each graphics state group, the CPU can utilize the graphics state (e.g., context registers, constants, shaders, and resource descriptors) within each group. In fact, in some respects, each draw call may contain a complete set of context state information, which can add considerable driver overhead.

[0056] As described above, workload or graphics state groups can include constants, vertex shaders, fragment shaders, geometry shaders, context registers, extractors, resource descriptors, blend states, data states, depth states, etc. The number of workload or graphics state groups can be any suitable number, such as 8, 16, 32, or 64. Furthermore, each workload or graphics state group can correspond to, for example, a specific state or context state executed at the GPU. In some aspects, the CPU can instruct the GPU how to divide its workload into different workload or graphics state groups. The GPU can then process these different workload or graphics state groups. In some aspects, the GPU may not have knowledge about which group corresponds to a specific state or context state.

[0057] Example LRZ depth orientation tracing at the GPU

[0058] In summary, this disclosure relates to processing systems, and more specifically, to one or more techniques for graphics processing. For example, as discussed, by using a graphics processing unit (GPU) to handle low-resolution (LRZ) depth orientation tracking, the use of an LRZ depth buffer for LRZ depth testing can be effectively enabled / disabled, even in a multi-threaded environment.

[0059] LRZ depth testing is a feature that allows the GPU to reject invisible pixels earlier in the image processing pipeline at an increased rate and with improved overall performance. Because depth testing occurs at a coarse level, it can be impossible in some angular situations. For example, with the depth write bit enabled, LRZ depth testing may be unavailable whenever a depth test orientation change occurs. Typically, the software driver tracks depth orientation changes across one or more draws throughout the command to determine whether LRZ depth testing is enabled or disabled (e.g., via the LRZEn bit, as shown below). In Example 1 below, the driver tracks the LRZ buffer orientation for each draw in execution order. Specifically, the driver detects an orientation change at draw4 (e.g., orientation switching from LESS to GREATER) and disables LRZ for the remainder of the rendering (e.g., LRZEn = 0).

[0060] Example 1

[0061] Draw1: Direction is LESS, LRZEn = 1, LRZWriteEn = 1; depthWrites = 1;

[0062] Draw2: Direction is LESS, LRZEn=1, LRZWriteEn=1; depthWrites=1;

[0063] Draw3: Direction is LESS, LRZEn = 1, LRZWriteEn = 0; depthWrites = 0;

[0064] Draw4: Direction is GREATER, LRZEn = 0, LRZWriteEn = 0; depthWrites = 1;

[0065] Draw5: Direction is LESS, LRZEn = 0, LRZWriteEn = 0; depthWrites = 1;

[0066] Draw6: Direction is LESS, LRZEn = 0, LRZWriteEn = 0, depthWrites = 0;

[0067] However, with the advent of next-generation processors and / or multi-threaded graphics application programming interfaces (APIs), drivers may not be aware of the execution order of draws when recording them into individual command buffers. For example, as shown in Examples 2 and 3 below, a driver may have two distinct command buffers, one of which may be committed before the other. In Example 2, if command buffer 1 is committed before command buffer 2, the LRZEn bit will be programmed similarly to Example 1 above. However, if command buffer 2 is committed before command buffer 1, as shown in Example 3, LRZ will not be enabled for draws in command buffer 1 or for draws 4 and 5 in command buffer 2 (e.g., LRZEn = 0). Because of the buffer orientation change in the previous command buffer (command buffer 2), the LRZEn of command buffer 1 is set to 0. Due to this uncertainty, the driver disables LRZ depth testing (e.g., for secondary command buffers, depth load cases, etc.) to avoid accidental rendering (e.g., depth rejection).

[0068] Example 2

[0069] Command Buffer 1:

[0070] Draw1: Direction is LESS, LRZEn = 1, LRZWriteEn = 1; depthWrites = 1;

[0071] Draw2: Direction is LESS, LRZEn=1, LRZWriteEn=1; depthWrites=1;

[0072] Draw3: Direction is LESS, LRZEn = 1, LRZWriteEn = 0; depthWrites = 0;

[0073] Command buffer 2:

[0074] Draw4: Direction is GREATER, LRZEn = 0, LRZWriteEn = 0; depthWrites = 1;

[0075] Draw5: Direction is LESS, LRZEn = 0, LRZWriteEn = 0; depthWrites = 1;

[0076] Draw6: Direction is LESS, LRZEn = 0, LRZWriteEn = 0, depthWrites = 0;

[0077] Example 3

[0078] Command buffer 2:

[0079] Draw4: Direction is GREATER, LRZEn=1, LRZWriteEn=1; depthWrites=1;

[0080] Draw5: Direction is LESS, LRZEn = 0, LRZWriteEn = 0; depthWrites = 1;

[0081] Draw6: Direction is LESS, LRZEn = 0, LRZWriteEn = 0, depthWrites = 0;

[0082] Command Buffer 1:

[0083] Draw1: Direction is LESS, LRZEn = 0, LRZWriteEn = 0; depthWrites = 1;

[0084] Draw2: Direction is LESS, LRZEn = 0, LRZWriteEn = 0; depthWrites = 1;

[0085] Draw3: Direction is LESS, LRZEn = 0, LRZWriteEn = 0, depthWrites = 0;

[0086] Therefore, certain aspects advantageously utilize the GPU, rather than the driver, to track the orientation of the depth buffer, enabling / disabling LRZ depth testing whenever the GPU detects a change in the depth buffer orientation. In some cases, the GPU can store the orientation of the depth buffer in (e.g., an additional, smaller) buffer (e.g., a state buffer) when encountering the first time-varying draw for a given frame (e.g., a given partition of the given frame) with depth writes enabled. The GPU can then compare the depth orientation of other draws with the orientation stored in the state buffer and then decide whether to enable / disable LRZ depth testing on a per-draw basis, and in some cases, disable LRZ for subsequent draws in a given frame (e.g., a given partition of the frame) based on the detected change in the depth buffer orientation (e.g., LESS to GREATER or GREATER to LESS). Thus, certain aspects of this paper allow the driver to no longer need to track the orientation depth used for drawing. In this case, the driver can simply enable LRZ depth testing for all applicable draws based on the depth function (e.g., LRZEn = 1) without actually tracking the depth orientation.

[0087] In some respects, the GPU is responsible for automatically disabling LRZ (or keeping LRZ enabled) based on detected changes in depth buffer orientation. This allows the driver and / or GPU to use LRZ depth testing more efficiently in many possible scenarios. As shown below in Example 4, LRZ depth testing can be enabled for each draw command (e.g., LRZEn = 1 for each of 6 draws). That is, the driver can assume that LRZ depth testing will be performed, and the GPU can make the decision to disable LRZ depth detection.

[0088] With command buffer 1 executed before command buffer 2, the GPU can be responsible for detecting changes in the depth buffer orientation. Therefore, the GPU can store LESS in the state buffer (e.g., as in Draw1) and compare the value of LESS stored in the state buffer with each of the remaining 5 draws (e.g., or N-1 draws, assuming N draws). As noted below, at Draw4, the GPU can detect that the orientation in the depth orientation buffer is now GREATER and determine to disable LRZ depth testing for the remaining draws (e.g., for Draw4, Draw5, and Draw6).

[0089] Example 4

[0090] Command Buffer 1:

[0091] Draw1: Direction is LESS, LRZEn = 1, LRZWriteEn = 1; depthWrites = 1;

[0092] Draw2: Direction is LESS, LRZEn=1, LRZWriteEn=1; depthWrites=1;

[0093] Draw3: Direction is LESS, LRZEn = 1, LRZWriteEn = 0; depthWrites = 0;

[0094] Command buffer 2:

[0095] Draw4: Direction is GREATER, LRZEn=1, LRZWriteEn=1; depthWrites=1;

[0096] Draw5: Direction is LESS, LRZEn=1, LRZWriteEn=1; depthWrites=1;

[0097] Draw6: Direction is LESS, LRZEn=1, LRZWriteEn=0; depthWrites=0.

[0098] In some cases, the GPU can re-enable LRZ depth testing for each partition within a frame (e.g., partitions 310, 311, 312, 313, 314, 315) (e.g., LRZEn = 1). For example, if LRZEn = 0 after N draws in the draw set have finished rendering for the first partition, the GPU can reset LRZEn to 1 to process the draw for the next partition.

[0099] In some aspects, a separate LRZ status buffer is provided for each partition, or one or more LRZ status buffers include separate entries for each partition. For example, device 104 (e.g., processing unit 120) may include one or more LRZ status buffers.

[0100] In some respects, the GPU can process drawing commands for different partitions of a frame in parallel or sequentially, processing some drawing commands across partitions before processing all drawing commands for a given partition of the frame. For example, suppose there are a total of 1000 drawing commands to process for partition 310. For example, the GPU could process drawing commands 1-500 first, and then continue processing drawing commands for another partition (such as partition 311). The GPU could later return to processing drawing command 501 for partition 310. Therefore, by maintaining separate information for the LRZ state buffer for each partition, the GPU could later check whether LRZ depth testing was previously disabled for partition 310 of the current frame, and if not, it could check whether there was a change in depth buffer orientation between drawing command 500 and drawing command 501 for partition 310 to determine whether the use of the LRZ depth state buffer was disabled for partition 310.

[0101] Furthermore, in some aspects, enabling / disabling the use of the LRZ depth buffer is performed on a per-partition basis within a frame. For example, disabling the LRZ depth buffer in one partition does not affect whether the LRZ depth buffer is used in another partition. Additionally, in some aspects, enabling / disabling the use of the LRZ depth buffer is performed on a per-frame basis, meaning that if the use of the LRZ depth buffer is disabled for some partitions in one frame, it is re-enabled for the next frame.

[0102] Figure 4 This is a sample flowchart illustrating example operation 400 for LRZ depth testing performed by a GPU. In some respects, operation 400 can be performed by the GPU, such as in... Figure 1 It is executed in the graphics processing pipeline 107 of the processing unit 120.

[0103] At 405, the operation can begin by the GPU receiving multiple commands corresponding to multiple draws across frames, each command indicating the depth test direction relative to the LRZ buffer for the corresponding draw. For example, each of the multiple commands is received from the driver and includes an indication that the use of the LRZ buffer for depth testing should be enabled for the corresponding draw. In this case, the GPU receives multiple commands from a multiple command buffer.

[0104] At 410, the GPU maintains an LRZ state buffer to store the corresponding depth test direction for the first command in time among multiple commands processed by the GPU.

[0105] At 415, after processing a command from among multiple commands that has a depth test direction different from the corresponding depth test direction stored in the LRZ state buffer, the GPU disables the use of the LRZ buffer for depth testing for any remaining unprocessed commands among the multiple commands. In some cases, the GPU may execute each of multiple draws. Alternatively, the GPU may re-enable the use of the LRZ buffer for depth testing for the second frame.

[0106] In some cases, the use of the LRZ buffer for depth testing can be disabled based on factors other than changes in depth orientation. For example, if the use of the LRZ buffer is enabled for the first draw (e.g., Draw1), then: if depth write (e.g., depthWrite = 0) is disabled, the GPU can disable the use of the LRZ buffer for the second draw (e.g., Draw2), regardless of any changes in depth orientation. In this case, the GPU can determine to re-enable the use of the LRZ buffer for the third draw (e.g., Draw3), even if all draws may be for the same partition within the same frame. In other words, the GPU can disable the use of the LRZ buffer for depth testing based on a given command that indicates disabling depth testing, and then re-enable the use of the LRZ buffer for depth testing based on at least one command processed after that given command.

[0107] In another scenario, after the use of the LRZ buffer is disabled (e.g., for a given partition of a given frame) based on a change in depth orientation, the GPU can determine (e.g., for a given partition of a given frame) to re-enable the use of the LRZ buffer (e.g., based on the GPU receiving (and processing) a depth clear command after such disabling). Specifically, based on the depth clear command, the LRZ buffer is cleared (and subsequently updated with the new value, such as for a partition of a frame). In this case, even with a change in depth orientation, the GPU can still re-enable the use of the LRZ buffer after the depth clear command, such as for a partition of a frame. For example, the Draw1 command can enable the use of the LRZ buffer. Furthermore, the Draw2 command can disable the use of the LRZ buffer based on a change in depth orientation. Additionally, a depth clear command is received after Draw2. Therefore, for Draw3 after the depth clear command, the GPU can re-enable the LRZ buffer. All such drawing can be for the same partition of the same frame.

[0108] In some respects, the GPU compares the corresponding depth test direction of each of one or more commands that include the command with the corresponding depth test direction stored in the LRZ state buffer. In this case, disabling the use of the LRZ buffer is in response to this comparison.

[0109] In some cases, the GPU disables the use of the LRZ buffer by disabling its use for the command and for each of the multiple commands that are processed after the command in time.

[0110] In some respects, a frame may include multiple partitions corresponding to different parts of the frame. The GPU receives multiple commands for each of the multiple partitions, and the GPU maintains a corresponding LRZ state buffer for each of the multiple partitions. In this case, the use of the LRZ buffer for depth testing is disabled independently for each of the multiple partitions.

[0111] In some aspects, operation 400 also includes comparing the corresponding depth test direction of each of one or more commands that include the command with the corresponding depth detection direction stored in the LRZ state buffer, wherein disabling the use of the LRZ buffer is in response to the comparison.

[0112] In some aspects of operation 400, disabling the use of the LRZ buffer at 415 includes: disabling the use of the LRZ buffer for the command and for each of the multiple commands that are processed after the command in time.

[0113] In some aspects of Operation 400, a frame comprises multiple partitions corresponding to different portions of the frame. In this case, the GPU receives multiple commands corresponding to each of the multiple partitions, and maintains a corresponding LRZ state buffer for each of the multiple partitions. In some aspects of Operation 400, the use of the LRZ buffer for depth testing is disabled independently for each of the multiple partitions.

[0114] In some aspects of Operation 400, each of the multiple commands is received from the driver and includes instructions on enabling the use of the LRZ buffer for depth testing for the corresponding draw. In some aspects of Operation 400, the GPU receives multiple commands from multiple command buffers.

[0115] In some respects, operation 400 also includes performing each of the multiple drawings.

[0116] In some respects, Operation 400 also includes re-enabling the use of the LRZ buffer for depth testing for the second frame.

[0117] In some aspects, prior to disabling at 415, operation 400 also includes disabling the use of the LRZ buffer for depth testing based on a given command that indicates the disabling of depth testing, and then re-enabling the use of the LRZ buffer for depth testing for at least one command processed after the given command.

[0118] In some respects, after being disabled at 415, operation 400 also includes re-enabling the use of the LRZ buffer for depth testing based on the processing depth clear command.

[0119] In one configuration, a method or apparatus for graphics processing is provided. The apparatus may be a CPU, a GPU, or some other processor capable of performing graphics processing. In one aspect, the apparatus may be a processing unit 120 within device 104, or some other hardware within device 104 or another device. The apparatus may include: a unit for receiving at the GPU a plurality of commands corresponding to a plurality of drawings spanning frames, each of the plurality of commands indicating a depth test direction relative to an LRZ buffer for the corresponding drawing. The apparatus may include: a unit for maintaining an LRZ state buffer at the GPU to store a corresponding depth test direction for a first command in time among the plurality of commands processed by the GPU. The apparatus may include: a unit for disabling the use of the LRZ buffer for depth testing for any remaining unprocessed commands among the plurality of commands after processing at the GPU a command having a depth test direction different from the corresponding depth test direction stored in the LRZ state buffer. The apparatus may include: a unit for comparing the corresponding depth test direction of each of one or more commands including the command with a corresponding depth detection direction stored in the LRZ state buffer, wherein disabling the use of the LRZ buffer is in response to the comparison. The apparatus may include a unit for performing each of multiple draws. The apparatus may also include a unit for re-enabling the use of the LRZ buffer for depth testing for a second frame.

[0120] The topics described herein can be implemented to achieve one or more benefits or advantages. For example, the described graphics processing techniques can be used by a GPU, CPU, or some other processor capable of performing graphics processing to implement the state information technology described herein. This can also be implemented at a lower cost compared to other graphics processing techniques. Furthermore, the graphics processing techniques described herein can improve or accelerate data processing or execution. Further, the graphics processing techniques described herein can improve resource or data utilization and / or resource efficiency.

[0121] According to this disclosure, unless otherwise specified in the context, the term "or" may be interpreted as "and / or". Additionally, while phrases such as "one or more" or "at least one" may be used for some features disclosed herein but not for others, features for which such language is not used may be interpreted as implying such a meaning unless otherwise specified in the context.

[0122] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” has been used throughout this disclosure, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on or transmitted via a computer-readable medium as one or more instructions or code. A computer-readable medium may include a computer data storage medium or a communication medium, including any medium that facilitates the transfer of a computer program from one place to another. In this way, a computer-readable medium may generally correspond to: (1) a non-transitory tangible computer-readable storage medium; or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described herein. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices. As used herein, disks and optical discs include compact optical discs (CDs), laser optical discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically copy data magnetically, while optical discs use lasers to copy data optically. Combinations of the above should also be included within the scope of computer-readable media. Computer program products may include computer-readable media.

[0123] The code can be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field-programmable arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" as used herein can refer to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. Furthermore, the techniques can be sufficiently implemented in one or more circuit or logic elements.

[0124] The techniques disclosed herein can be implemented in a wide variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs), or a set of ICs (e.g., chipsets). Various components, modules, or units are described in this disclosure to emphasize functional aspects of a device configured to perform the disclosed techniques, but they do not necessarily need to be implemented through different hardware units. Specifically, as described above, the various units can be combined in any hardware unit, or provided by a batch of interoperable hardware units (including one or more processors as described above) combined with suitable software and / or firmware.

[0125] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. A method for image processing, comprising: At the graphics processing unit (GPU), multiple commands corresponding to multiple draws spanning frames are received, each of the multiple commands indicating the depth test direction relative to the low-resolution depth (LRZ) buffer for the corresponding draw; An LRZ state buffer is maintained at the GPU to store the corresponding depth test direction for the first command in time among the plurality of commands processed by the GPU; as well as At the GPU, after processing a second command among the plurality of commands that has a depth test direction different from the corresponding depth test direction stored in the LRZ state buffer, the use of the LRZ buffer for depth testing is disabled for any remaining unprocessed commands among the plurality of commands.

2. The method according to claim 1, further comprising: The corresponding depth test direction of each of one or more commands including the second command is compared with the corresponding depth test direction stored in the LRZ state buffer, wherein disabling the use of the LRZ buffer is in response to the comparison.

3. The method according to claim 1, wherein, Disabling the use of the LRZ buffer includes disabling the use of the LRZ buffer for the second command and for each of the plurality of commands that is processed in time after the second command.

4. The method according to claim 1, wherein, The frame includes multiple partitions corresponding to different parts of the frame, wherein the GPU receives multiple commands corresponding to each of the multiple partitions, and wherein the GPU maintains a corresponding LRZ state buffer for each of the multiple partitions.

5. The method according to claim 4, wherein, The use of the LRZ buffer for depth testing is disabled independently for each of the plurality of partitions.

6. The method according to claim 1, wherein, Each of the plurality of commands is received from the driver and includes an indication that the use of the LRZ buffer for depth testing should be enabled for the corresponding draw.

7. The method according to claim 6, wherein, The GPU receives the multiple commands from multiple command buffers.

8. The method according to claim 1, further comprising: Perform each of the plurality of drawings.

9. The method according to claim 1, further comprising: The use of the LRZ buffer for depth testing is re-enabled for the second frame.

10. The method of claim 1, further comprising, prior to disabling the use of the LRZ buffer for depth testing: The use of the LRZ buffer for depth testing is disabled based on a given command that indicates that depth testing is disabled, and then the use of the LRZ buffer for depth testing is re-enabled for at least one command processed after the given command.

11. The method of claim 1, further comprising, after the disablement of the use of the LRZ buffer for depth testing: The use of the LRZ buffer for depth testing is re-enabled based on the processing depth clear command.

12. An apparatus for graphics processing, comprising: Low-resolution depth (LRZ) buffer; LRZ state buffer; as well as The graphics processing unit (GPU) is configured as follows: Receive multiple commands corresponding to multiple draws spanning frames, each of the multiple commands indicating the depth test direction relative to the LRZ buffer for the corresponding draw; Maintain the LRZ state buffer to store the corresponding depth test direction for the first command in time among the plurality of commands processed by the GPU; as well as After processing a second command among the plurality of commands that has a depth test direction different from the corresponding depth test direction stored in the LRZ state buffer, the use of the LRZ buffer for depth testing is disabled for any remaining unprocessed commands among the plurality of commands.

13. The apparatus according to claim 12, wherein, The GPU is further configured to compare the corresponding depth test direction of each of one or more commands including the second command with the corresponding depth test direction stored in the LRZ state buffer, wherein disabling the use of the LRZ buffer is in response to the comparison.

14. The apparatus according to claim 12, wherein, Disabling the use of the LRZ buffer includes disabling the use of the LRZ buffer for the second command and for each of the plurality of commands that is processed in time after the second command.

15. The apparatus according to claim 12, wherein, The frame includes multiple partitions corresponding to different parts of the frame, wherein the GPU receives multiple commands corresponding to each of the multiple partitions, and wherein the GPU maintains a corresponding LRZ state buffer for each of the multiple partitions.

16. The apparatus according to claim 15, wherein, The use of the LRZ buffer for depth testing is disabled independently for each of the plurality of partitions.

17. The apparatus according to claim 12, wherein, Each of the plurality of commands is received from the driver and includes an indication that the use of the LRZ buffer for depth testing should be enabled for the corresponding draw.

18. The apparatus according to claim 17, wherein, The GPU receives the multiple commands from multiple command buffers.

19. The apparatus according to claim 12, wherein, The GPU is also configured to perform each of the plurality of drawings.

20. The apparatus according to claim 12, wherein, The GPU is also configured to re-enable the use of the LRZ buffer for depth testing for the second frame.

21. The apparatus according to claim 12, wherein, The GPU is also configured to, prior to the disablement of the use of the LRZ buffer for depth testing: The use of the LRZ buffer for depth testing is disabled based on a given command that indicates that depth testing is disabled, and then the use of the LRZ buffer for depth testing is re-enabled for at least one command processed after the given command.

22. The apparatus according to claim 12, wherein, The GPU is also configured to, after the use of the LRZ buffer for depth testing is disabled: The use of the LRZ buffer for depth testing is re-enabled based on the processing depth clear command.

23. A computing device for graphics processing, comprising: Central Processing Unit (CPU); monitor; Low-resolution depth (LRZ) buffer; LRZ state buffer; as well as The graphics processing unit (GPU) is configured as follows: The CPU receives a plurality of commands corresponding to a plurality of drawings across a frame for display on the display, each of the plurality of commands indicating a depth test direction relative to the LRZ buffer for the corresponding drawing; Maintain the LRZ state buffer to store the corresponding depth test direction for the first command in time among the plurality of commands processed by the GPU; as well as After processing a second command among the plurality of commands that has a depth test direction different from the corresponding depth test direction stored in the LRZ state buffer, the use of the LRZ buffer for depth testing is disabled for any remaining unprocessed commands among the plurality of commands.

24. The computing device according to claim 23, wherein, The GPU is further configured to compare the corresponding depth test direction of each of one or more commands including the second command with the corresponding depth test direction stored in the LRZ state buffer, wherein disabling the use of the LRZ buffer is in response to the comparison.

25. The computing device according to claim 23, wherein, Disabling the use of the LRZ buffer includes disabling the use of the LRZ buffer for the second command and for each of the plurality of commands that is processed in time after the second command.

26. The computing device according to claim 23, wherein, The frame includes multiple partitions corresponding to different parts of the frame, wherein the GPU receives multiple commands corresponding to each of the multiple partitions, and wherein the GPU maintains a corresponding LRZ state buffer for each of the multiple partitions.

27. The computing device according to claim 26, wherein, The use of the LRZ buffer for depth testing is disabled independently for each of the plurality of partitions.

28. The computing device according to claim 23, wherein, Each of the plurality of commands is received from the driver and includes an indication that the use of the LRZ buffer for depth testing should be enabled for the corresponding draw.

29. The computing device according to claim 28, wherein, The GPU receives the multiple commands from multiple command buffers.

30. The computing device according to claim 23, wherein, The GPU is also configured to perform each of the plurality of draws.

31. The computing device according to claim 23, wherein, The GPU is also configured to re-enable the use of the LRZ buffer for depth testing for the second frame.

32. The computing device according to claim 23, wherein, The GPU is also configured to, prior to the disablement of the use of the LRZ buffer for depth testing: The use of the LRZ buffer for depth testing is disabled based on a given command that indicates that depth testing is disabled, and then the use of the LRZ buffer for depth testing is re-enabled for at least one command processed after the given command.

33. The computing device according to claim 23, wherein, The GPU is also configured to, after the use of the LRZ buffer for depth testing is disabled: The use of the LRZ buffer for depth testing is re-enabled based on the processing depth clear command.

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