Substrate integrated with passive device and method of manufacturing the same

Abstract

The present disclosure provides a substrate integrated with a passive device and a preparation method thereof, and belongs to the technical field of radio frequency devices. The substrate integrated with the passive device comprises a substrate and a passive device arranged on the substrate, and the passive device at least comprises an inductor. The inductor comprises a plurality of open loop parts arranged in sequence and connected in sequence in the direction away from the substrate. An interlayer dielectric layer is arranged between adjacent open loop parts, and the adjacent open loop parts are electrically connected through a first via hole penetrating the interlayer dielectric layer. The orthographic projection of any two open loop parts on the substrate at least partially overlaps.

Description

Technical Field

[0001] This disclosure belongs to the field of radio frequency device technology, specifically relating to a substrate integrating passive devices and its fabrication method. Background Technology

[0002] In contemporary times, the consumer electronics industry is developing rapidly, with mobile communication terminals, especially 5G phones, evolving quickly. Phones need to process an increasing number of signal frequency bands, leading to a surge in the number of radio frequency (RF) chips required. Meanwhile, the preferred form factors for mobile phones are miniaturization, thinness, and long battery life. Traditional mobile phones contain numerous discrete components on the RF PCB board, such as resistors, capacitors, inductors, and filters. These components suffer from drawbacks such as large size, high power consumption, numerous solder joints, and significant parasitic parameter variations, making them unsuitable for future demands. The interconnection and matching of RF chips require small-area, high-performance, and highly consistent integrated passive components. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a substrate integrating passive devices and a method for fabricating the same.

[0004] In a first aspect, embodiments of this disclosure provide a substrate integrating passive devices, comprising a substrate and passive devices disposed on the substrate, wherein the passive devices include at least an inductor; the inductor includes a plurality of open-loop portions arranged sequentially and connected in a direction away from the substrate; wherein an interlayer dielectric layer is disposed between adjacent open-loop portions, and adjacent open-loop portions are electrically connected through a first via penetrating the interlayer dielectric layer; and the orthographic projections of any two open-loop portions on the substrate at least partially overlap.

[0005] The interlayer dielectric layer includes a first passivation layer, a planarization layer, and a second passivation layer sequentially disposed along the direction away from the substrate; the substrate includes N interlayer dielectric layers; the planarization layer in the Mth interlayer dielectric layer contacts the planarization layer in the (M-1)th interlayer dielectric layer through a second via penetrating the second passivation layer in the (M-1)th interlayer dielectric layer and the first passivation layer in the Mth interlayer dielectric layer; N≥2, 2≤M≤N, and M and N are both integers.

[0006] Wherein, the orthographic projections of the second vias located at least partially in different layers on the substrate at least partially overlap.

[0007] The planarization layer in the Mth interlayer dielectric layer is in contact with the planarization layer in the (M-1)th interlayer dielectric layer through multiple second vias.

[0008] Wherein, at least a portion of the first vias have non-overlapping orthogonal projections onto the substrate.

[0009] The passive device further includes a capacitor, which includes a first electrode plate and a second electrode plate arranged sequentially along the side away from the substrate; the first electrode plate is disposed in the same layer as one of the plurality of open-loop portions and is made of the same material.

[0010] The first electrode plate is disposed in the same layer as the first of the plurality of open-loop portions disposed in the direction opposite to the substrate, and is directly electrically connected.

[0011] The thickness ratio of the second electrode plate to the first electrode plate is 1:100 to 1:30.

[0012] The substrate further includes a first connecting portion, which is electrically connected to the second electrode plate. The first connecting portion is disposed in the same layer as the last of the plurality of open-loop portions disposed in the direction away from the substrate.

[0013] The substrate further includes a transition section, which is disposed on the same layer as any one or more of the plurality of open-loop sections located between the first and the last.

[0014] Secondly, embodiments of this disclosure provide a method for fabricating a substrate integrating passive devices, comprising: providing a substrate and forming passive devices on the substrate, the passive devices including an inductor; the inductor including a plurality of open-loop portions arranged sequentially and connected in a direction away from the substrate; wherein the step of forming the inductor includes: sequentially forming a plurality of open-loop portions and an interlayer dielectric layer covering the open-loop portions on the substrate, the adjacent open-loop portions being electrically connected through a first via penetrating the interlayer dielectric layer; and the orthographic projections of any two open-loop portions on the substrate at least partially overlap.

[0015] The step of forming the open-loop portion includes: forming a metal thin film on the substrate as a seed layer; forming a sacrificial layer on the side of the seed layer away from the substrate, and etching the sacrificial layer to form a groove corresponding to the open-loop portion; electroplating the seed layer to form a metal material in the groove; removing the seed layer, and removing the metal material other than the groove through a patterning process to form the open-loop portion.

[0016] The interlayer dielectric layer includes a first passivation layer, a planarization layer, and a second passivation layer sequentially disposed along the direction away from the substrate; the substrate includes N interlayer dielectric layers; the method further includes forming a second via penetrating the second passivation layer in the (M-1)th interlayer dielectric layer and the first passivation layer in the Mth interlayer dielectric layer, so that the planarization layer in the Mth interlayer dielectric layer contacts the planarization layer in the (M-1)th interlayer dielectric layer; N≥2, 2≤M≤N, and M and N are both integers.

[0017] The passive device further includes a capacitor, and the step of forming the capacitor includes: forming a first electrode plate and a second electrode plate sequentially along the side away from the substrate; the first electrode plate and one of the plurality of open-loop portions are formed in the same patterning process.

[0018] The first electrode plate and the first of the plurality of open-loop portions disposed in the direction away from the substrate are formed in the same patterning process. Attached Figure Description

[0019] Figure 1 This is a perspective view of the inductance and capacitance of a substrate with integrated passive devices according to an embodiment of this disclosure.

[0020] Figure 2 This is a cross-sectional view of a substrate integrating passive devices according to an embodiment of the present disclosure.

[0021] Figure 3 This is a cross-sectional view of the intermediate product formed in step S11 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.

[0022] Figure 4 This is a cross-sectional view of the intermediate product formed in step S12 of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.

[0023] Figure 5 This is a cross-sectional view of the intermediate product formed in step S13 of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.

[0024] Figure 6 This is a cross-sectional view of the intermediate product formed in step S14 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.

[0025] Figure 7 This is a cross-sectional view of the intermediate product formed in step S15 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.

[0026] Figure 8 This is a cross-sectional view of the intermediate product formed in step S16 of the method for preparing a substrate with integrated passive devices according to an embodiment of the present disclosure.

[0027] Figure 9 This is a cross-sectional view of the intermediate product formed in step S17 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure.

[0028] Figure 10 This is a cross-sectional view of the intermediate product formed in step S18 of the method for fabricating a substrate with integrated passive devices according to an embodiment of the present disclosure. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0031] This disclosure provides a substrate with integrated passive components and a method for fabricating the same. The passive components, such as capacitors, inductors, and resistors, are integrated on the substrate to form a circuit structure. This disclosure uses an LC oscillation circuit integrated on the substrate as an example. That is, at least inductors and capacitors are integrated on the substrate. It should be understood that, depending on the circuit function and performance, resistors and other components may also be integrated on the substrate.

[0032] Firstly, combining Figure 1 and Figure 2 As shown, this disclosure provides a substrate integrating passive devices, including a substrate 10 and passive devices disposed on the substrate 10, the passive devices including at least an inductor 1. The inductor 1 includes a plurality of open-loop portions 11 arranged sequentially and connected in a direction away from the substrate 10 (i.e., perpendicular to the plane of the substrate 10). Specifically, each open-loop portion 11 includes a beginning and an end, and the beginning and end of adjacent open-loop portions 11 are connected sequentially. In particular, the side of any open-loop portion 11 away from the substrate 10 is covered with an interlayer dielectric layer 4, and adjacent open-loop portions 11 are electrically connected through a first via 12 penetrating the interlayer dielectric layer 4; in this disclosure embodiment, the orthographic projections of any two open-loop portions 11 on the substrate 10 at least partially overlap.

[0033] Since the orthographic projections of any two open-loop portions 11 of the inductor 1 formed on the substrate 10 in this embodiment of the present disclosure at least partially overlap on the substrate 10, the space occupied by the inductor 1 on the substrate 10 can be effectively reduced, which helps to achieve high integration of the substrate with passive devices.

[0034] In some examples, the orthographic projections of each open-loop portion 11 of the inductor 1 onto the substrate 10 completely overlap, thereby minimizing the size of the inductor 1 and increasing the integration density of the substrate.

[0035] In some examples, the interlayer dielectric layer 4 includes a first passivation layer 41, a planarization layer 42, and a second passivation layer 43 sequentially disposed along the side facing away from the substrate 10. In some examples, both the first passivation layer 41 and the second passivation layer 43 can be made of inorganic materials, which can be the same or different. Inorganic materials include SiNx, SiNOx, and SiOx. The first passivation layer 41 and the second passivation layer 43 can each be composed of one or more of SiNx, SiNOx, and SiOx to form a single-layer structure or a stacked structure. The thickness of both the first passivation layer 41 and the second passivation layer 43 is approximately 2000-4000 Å. The planarization layer 42 is made of an organic material. Organic materials include photosensitive OC materials, such as acrylic polymers and silicon polymers. The thickness of the planarization layer 42 is 2 μm-5 μm, for example, the thickness of the planarization layer 42 is 3 μm.

[0036] Furthermore, when the inductor 1 has N open-loop portions 11, the number of interlayer dielectric layers 4 is also N, where N ≥ 2, and N is an integer. In this case, the planarization layer 42 in the Mth interlayer dielectric layer 4 contacts the planarization layer 42 in the (M-1)th interlayer dielectric layer 4 through a second via 13 that penetrates the second passivation layer 43 in the (M-1)th interlayer dielectric layer 4 and the first passivation layer 41 in the Mth interlayer dielectric layer 4, where 2 ≤ M ≤ N, and M is an integer. That is, for any second via 13, it penetrates the second passivation layer 43 of one adjacent interlayer dielectric layer 4 and the first passivation layer 41 of the other, so that the planarization layers 42 in the adjacent interlayer dielectric layers 4 come into contact. This arrangement is because the planarization layer 42 is usually made of an organic insulating material, and the second via 13 acts as a ventilation channel to allow water, oxygen, etc. absorbed by each planarization layer 42 to be discharged from the substrate.

[0037] Furthermore, in some examples, the orthographic projections of the second vias 13 located at least partially in different layers onto the substrate 10 at least partially overlap, meaning that at least the second vias 13 are connected in the direction perpendicular to the substrate 10. This facilitates the extraction of water, oxygen, and other contaminants from each planarization layer 42. In one example, the substrate includes multiple layers of second vias 13, and each layer contains multiple second vias 13. Second vias 13 in any adjacent layer are arranged in a one-to-one correspondence, and the orthographic projections of the multiple corresponding second vias 13 onto the substrate 10 completely overlap. This method maximizes the extraction of water, oxygen, and other contaminants from each planarization layer 42.

[0038] In some examples, at least a portion of the first vias 12 used to electrically connect adjacent open-loop portions 11 in the inductor 1 have non-overlapping orthographic projections on the substrate 10. For example, the orthographic projections of the i-th and (i+1)-th first vias 12 in the direction away from the substrate 10 do not overlap, where i ≥ 1. This effectively avoids the concentrated arrangement of the first vias 12, reducing the risk of inductor 1 device malfunction. In some examples, the orthographic projections of the i-th and (i+1)-th first vias 12 in the direction away from the substrate 10 do not overlap, while the orthographic projections of the i-th and (i+2)-th first vias 12 completely overlap on the substrate 10. In this case, the patterns of the i-th and (i+2)-th open-loop portions 11 in the direction away from the substrate 10 can be identical, and their orthographic projections on the substrate 10 can overlap.

[0039] In some examples, the passive device in this disclosure embodiment includes not only inductor 1, but also capacitor 2. Capacitor 2 includes a first electrode 21 and a second electrode 22 sequentially disposed along the side facing away from the substrate 10. The first electrode 21 can be disposed in the same layer as one of the multiple open-loop portions 11 of inductor 1, and made of the same material. In this case, the first electrode 21 of capacitor 2 and one open-loop portion 11 of inductor 1 can be formed in a single patterning process, thus reducing process steps and costs. For example, the first electrode 21 of capacitor 2 can be disposed in the same layer as the first open-loop portion 11 of inductor 1 in the direction facing away from the substrate, and directly electrically connected; that is, the first electrode 21 of capacitor 2 can be integrally formed with the first open-loop portion 11 of inductor 1 in the direction facing away from the substrate. In this case, a dielectric layer 23 can be disposed between the second electrode 22 and the first electrode 21 of capacitor 2. This dielectric layer 23 can comprise a single-layer or multi-layer structure composed of one or more materials selected from SiNx, SiNOx, and SiOx, with a thickness of approximately 2000-4000 Å, for example, 1200 Å. In this embodiment, the thickness of the second electrode 22 of capacitor 2 is less than the thickness of the first electrode 21, for example, the thickness ratio of the second electrode 22 to the first electrode 21 is 1:100 to 1:30, preferably 1:60. Of course, the thickness of the two electrodes of capacitor 2 can be specifically set according to product requirements. In some examples, this embodiment also includes a first connecting portion 3, which serves as a signal receiving terminal for the second electrode 22 of capacitor 2. The first connecting portion 3 is disposed in the same layer as the second electrode 22 of capacitor 2 and the last of the plurality of open-loop portions 11 disposed in the direction away from the substrate 10. Furthermore, to prevent a large distance between the first connecting part 3 and the second electrode plate 22 from causing a break in the connection, at least one adapter 5 is provided between the first connecting part 3 and the second electrode plate 22. The first connecting part 3 is electrically connected to the second electrode plate 22 through the adapter 5. For example, the inductor 1 includes three open-loop parts 11, the first electrode plate 21 of the capacitor 2 is disposed on the same layer as the first open-loop part 11, the second electrode plate 22 of the capacitor 2 is only separated from the first electrode plate 21 by a dielectric layer 23, the adapter 5 can be disposed on the same layer as the second open-loop part 11, and the first connecting part 3 can be disposed on the same layer as the third open-loop part 11. In this case, the first connecting part 3 connects to the adapter 5, and the adapter 5 connects to the second electrode plate 22, thereby realizing the electrical connection between the first connecting part 3 and the second electrode plate 22. In some examples, the adapter 5 is disposed on the same layer as any one or more of the multiple open-loop parts 11 in the inductor 1 located between the first and the last. This does not increase the number of process steps and can also reduce process costs.

[0040] It should be noted that a protective layer 6 can be formed on the layer opposite to the substrate where the last open-loop portion 11 and the first connecting portion 3 are located. A third via 71 and a fourth via 72 are formed in the protective layer 6. One end of the last open-loop portion 11 of the inductor 1 is exposed at the location of the third via 71, and the first connecting portion 3 is exposed at the location of the fourth via 72, thereby facilitating the loading of signals onto the capacitor 2 and the inductor 1. The protective layer may include a first passivation layer 61 and a planarization layer 62. The first passivation layer 61 and the planarization layer 62 can be made of the same materials as the first passivation layer 41 and the planarization layer 42 described above, and therefore will not be repeated here.

[0041] In some examples, the substrate 10 in this disclosure embodiment can be a glass substrate or a flexible thin film. The flexible thin film material can be at least one of COP film, polyimide (PI), or polyethylene terephthalate (PET). The thickness of the substrate 10 in this disclosure embodiment can be approximately 0.5 mm to 1 mm, for example, the thickness of the substrate 10 is 0.7 mm. A reverse stress layer can be formed on the substrate 10 in this disclosure embodiment to reduce glass warping.

[0042] Secondly, embodiments of this disclosure provide a method for fabricating a substrate integrating passive devices, which can be used to fabricate the aforementioned substrate. The method may include providing a substrate 10 and forming passive devices on the substrate 10, the passive devices including an inductor 1; the inductor 1 includes a plurality of open-loop portions 11 sequentially arranged and connected along a direction away from the substrate 10; wherein the step of forming the inductor 1 includes: sequentially forming a plurality of open-loop portions 11 and an interlayer dielectric layer 4 covering the open-loop portions 11 on the substrate 10, adjacent open-loop portions 11 being electrically connected through a first via 12 penetrating the interlayer dielectric layer 4; and the orthographic projections of any two open-loop portions 11 on the substrate 10 at least partially overlap.

[0043] To better illustrate the fabrication method in this embodiment, the following description uses three open-loop portions 11 of the inductor 1 as an example. The following description includes not only the step of forming the inductor 1 but also the step of forming the capacitor 2; however, it should be understood that the absence of a capacitor 2 in the substrate is also within the scope of protection of this embodiment. The fabrication method in this embodiment may specifically include the following steps.

[0044] S11, Reference Figure 3 A substrate 10 is provided, on which a pattern including a first plate 21 of a capacitor 2 and a first open-loop portion 11a of an inductor 1 is formed.

[0045] In some examples, step S11 may specifically include:

[0046] S111. A substrate 10 is provided, and a first sacrificial layer is formed on the first substrate 10. The first sacrificial layer is patterned to form a first slot in the first sacrificial layer that corresponds to the pattern of the first electrode 21 of the capacitor 2 to be formed and the first open loop portion 11a of the inductor 1.

[0047] The substrate 10 can be a glass substrate or a flexible film. The flexible film material can be at least one of COP film, polyimide (PI), or polyethylene terephthalate (PET). In this case, in S1, the flexible COP film can be bonded to the glass substrate using transparent optical adhesive (OCA adhesive), and then the glass substrate with the COP film formed is cleaned. The material of the first sacrificial layer includes, but is not limited to, organic materials, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, and other resin materials.

[0048] S112. A first metal thin film is deposited on the side of the first sacrificial layer away from the substrate 10 using an electron beam evaporation apparatus, and this first metal thin film serves as a first seed layer. The material of the first metal thin film includes, but is not limited to, at least one of Cu, Al, Mo, and Ag, and the thickness of the first metal thin film is approximately 100 nm to 500 nm, and further can be 50 nm to 35 μm, for example, 7 μm. In the following description, copper is used as an example as the material of the first metal thin film.

[0049] S113. The substrate 10, after completing the above steps, is placed on the electroplating machine carrier, and an electric pad is pressed on. It is then placed in a via-filling electroplating tank (using a special via-filling electrolyte). Current is applied, and the electroplating solution continues to flow rapidly on the surface of the first metal film. Cations in the electroplating solution gain electrons on the inner wall of the first open tank, becoming atoms and depositing on the inner wall. Using a specially formulated via-filling electrolyte, high-speed deposition of metallic copper (0.5-3 μm / min) is achieved primarily within the first open tank. In contrast, the deposition rate of metallic copper on the flat surface of the substrate 10 is extremely low (0.005-0.05 μm / min). Over time, the metallic copper on the inner wall of the first open tank gradually thickens, forming the first metal film layer. At this point, the first metal film layer is more than 5 μm thicker than the first metal film.

[0050] S113. Remove the first metal film material except for the first slot, and remove the first sacrificial layer to form the first open-loop portion 11a of the inductor 1 and the first electrode plate 21 of the capacitor 2.

[0051] The first open-loop portion 11a of the inductor 1 and the first electrode plate 21 of the capacitor 2, thus completed, are primarily formed using electroplating. It should be noted that the above is only one exemplary method for forming the first open-loop portion 11a of the inductor 1 and the first electrode plate 21 of the capacitor 2. In some examples, a first metal film layer can also be deposited, followed by exposure, development, and etching to form the patterns of the first open-loop portion 11a of the inductor 1 and the first electrode plate 21 of the capacitor 2. The methods for forming the first open-loop portion 11a of the inductor 1 and the first electrode plate 21 of the capacitor 2 are not listed here.

[0052] S12. Reference Figure 4 On the substrate 10 after the above steps are completed, a dielectric layer 23 is formed as the intermediate medium of the capacitor 2.

[0053] In some examples, the dielectric layer 23 can be a single-layer or multilayer structure composed of one or more materials selected from SiNx, SiNOx, and SiOx, with a thickness of about 2000-4000 Å, for example, 1200 Å.

[0054] S13. Reference Figure 5 The step involves forming a second electrode plate 22, including a capacitor 2, on the substrate 10 after completing the above steps through a patterning process.

[0055] In some examples, the material of the second electrode 22 of capacitor 2 may be the same as that of the first electrode 21, except that the thickness of the second electrode 22 is slightly thinner than that of the first electrode 21. The step of forming the second electrode 22 of capacitor 2 by patterning process may specifically include: depositing a second metal thin film by, for example, controlled sputtering, and forming the pattern of the second electrode 22 of capacitor 2 by exposure, development and etching processes.

[0056] S14. Reference Figure 6 On the substrate 10 after the above steps are completed, a first interlayer dielectric layer 4a is formed, and a first first via 12a and a first first transition hole 44a are formed through the first interlayer dielectric layer 4a by a patterning process. Specifically, one end of the first open-loop portion 11 of the inductor 1 (this end is not connected to the first electrode 21 of the capacitor 2) is exposed at the location of the first first via 12a, and at least a portion of the second electrode 22 of the capacitor 2 is exposed at the location of the first first transition hole 44a.

[0057] In some examples, the first interlayer dielectric layer 4a includes a first passivation layer 41, a planarization layer 42, and a second passivation layer 43 sequentially disposed along the substrate 10 away from the substrate. In some examples, both the first passivation layer 41 and the second passivation layer 43 can be made of inorganic materials, which can be the same or different. Inorganic materials include SiNx, SiNOx, and SiOx. The first passivation layer 41 and the second passivation layer 43 can each be composed of one or more of SiNx, SiNOx, and SiOx to form a single-layer structure or a stacked structure. The thickness of both the first passivation layer 41 and the second passivation layer 43 is approximately 2000-4000 Å. The planarization layer 42 is made of an organic material. Organic materials include photosensitive OC materials, such as acrylic polymers and silicon polymers. The thickness of the planarization layer 42 is 2 μm-5 μm, for example, the thickness of the planarization layer 42 is 3 μm.

[0058] In some examples, the steps of forming the first via 12a and the first transition hole 44a may specifically include: First, a first passivation layer 41 and a planarization layer 42 are sequentially formed on the substrate 10 on which the second electrode 22 of the storage capacitor 2 is formed. Then, a first sub-via and a second sub-via are formed through the first passivation layer 41 and the planarization layer 42 using a patterning process. The first sub-via exposes one end of the first open-loop portion 11 of the inductor 1 (this end is not connected to the first electrode 21 of the capacitor 2), and the second sub-via exposes at least a portion of the second electrode 22 of the storage capacitor 2. Next, a second passivation layer 43 is formed, and a third sub-via and a fourth sub-via are formed through the second passivation layer 43. The third sub-via and the first sub-via are connected to form the first via 12a, and the fourth sub-via and the second via are connected to form the first transition hole 44a.

[0059] It should be noted that when the first interlayer dielectric layer 4a includes a first passivation layer 41, a planarization layer 42 and a second passivation layer 43 sequentially disposed along the substrate 10 away from the substrate, step S14 may further include, after sequentially depositing the first passivation layer 41, the planarization layer 42 and the second passivation layer 43, forming a first first via 12 and a first first transition hole 44a penetrating the first passivation layer 41, the planarization layer 42 and the second passivation layer 43 through a single patterning process.

[0060] S15. Reference Figure 7 On the substrate 10 after the above steps are completed, a pattern including a second open-loop portion 11b of the inductor 1 and a transition portion 5 is formed by a patterning process. The second open-loop portion 11b is connected to the first open-loop portion 11a through a first first via 12a, and the transition portion 5 is connected to the second electrode plate 22 of the capacitor 2 through a first first transition hole 44a.

[0061] In some examples, the process methods used for the second open-loop portion 11b and the transition portion 5 of the inductor 1 formed in step S15 are the same as those used in step S11, such as electroplating copper, so they will not be repeated here.

[0062] S16, Reference Figure 8 On the substrate 10 after the above steps are completed, a second interlayer dielectric layer 4 is formed, and a second first via 12b and a second first transition hole 44b penetrating the second interlayer dielectric layer 4b are formed by a patterning process. Specifically, one end of the second open-loop portion 11b of the inductor 1 is exposed at the location of the second first via 12b, and at least a portion of the transition portion 5 is exposed at the location of the second first transition hole 44b.

[0063] In some examples, the second interlayer dielectric layer 4b and the first interlayer dielectric layer 4a can adopt the same film structure, such as including a first passivation layer 41, a planarization layer 42 and a second passivation layer 43 sequentially disposed along the substrate 10 away from the substrate. Therefore, the steps of forming the second first via 12b and the second first transition via 44b can be the same as S14, and will not be described again here.

[0064] In some examples, when the second interlayer dielectric layer 4b is sequentially disposed along the first passivation layer 41, planarization layer 42, and second passivation layer 43 away from the substrate 10, after forming the first passivation layer 41 of the second interlayer dielectric layer 4b, a second via 13 may be formed that penetrates the second passivation layer 43 of the first interlayer dielectric layer 4a and the first passivation layer 41 of the second interlayer dielectric layer 4b, so that the planarization layer 42 of the first interlayer dielectric layer 4 and the planarization layer 42 of the second interlayer dielectric layer 4 can contact each other through the first second via 13a. The first second via 13a acts as a venting channel to allow water, oxygen, and other substances absorbed by each planarization layer 42 to be released to the outside.

[0065] S17, Reference Figure 9 On the substrate 10 after completing the above steps, a third open-loop portion 11c and a first connecting portion 3 of the inductor 1 are formed. The third open-loop portion 11c is connected to one end of the second open-loop portion 11b through a second first through-hole 12b, and the first connecting portion 3 is connected to the adapter portion 5 through a second first adapter hole 44b.

[0066] The process method used for the third open-loop portion 11c and the first connecting portion 3 of the inductor 1 formed in step S17 is the same as that used in step S11 or S15, for example, by electroplating copper, so it will not be repeated here.

[0067] S18, Reference Figure 10A protective layer 6 is formed on the substrate 10 after the above steps are completed, and a third via 71 and a fourth via 72 are formed through the protective layer 6. The third via 71 exposes one end of the third open loop portion 11c of the inductor 1, and the fourth via 72 exposes the first connection portion 3, thereby facilitating the loading of signals onto the capacitor 2 and the inductor 1.

[0068] In some examples, the protective layer 6 may include the first passivation layer 61 and the planarization layer 62 described above. In this case, it may also include a second second via 13b formed after the first passivation layer 61, penetrating the first passivation layer 61 and the second passivation layer 43 of the second interlayer dielectric layer 4, so that the planarization layer 62 of the protective layer 6 and the planarization layer 42 of the second interlayer dielectric layer 4 come into contact, so that the water, oxygen and other substances absorbed by each planarization layer 42 are released to the outside.

[0069] This completes the fabrication of the substrate integrating passive devices in the embodiments of this disclosure.

[0070] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A substrate integrating passive devices, comprising a substrate and passive devices disposed on the substrate, wherein the passive devices include at least an inductor; the inductor includes a plurality of open-loop portions arranged sequentially and connected in a direction away from the substrate; wherein, An interlayer dielectric layer is disposed between adjacent open-loop portions, and the adjacent open-loop portions are electrically connected through a first via penetrating the interlayer dielectric layer; and the orthographic projections of any two open-loop portions on the substrate at least partially overlap. The interlayer dielectric layer includes a first passivation layer, a planarization layer, and a second passivation layer sequentially disposed along the direction away from the substrate; the substrate includes N interlayer dielectric layers; the planarization layer in the Mth interlayer dielectric layer contacts the planarization layer in the (M-1)th interlayer dielectric layer through a second via penetrating the second passivation layer in the (M-1)th interlayer dielectric layer and the first passivation layer in the Mth interlayer dielectric layer; N≥2, 2≤M≤N, and M and N are both integers.

2. The substrate according to claim 1, wherein, The orthographic projections of the second vias, which are at least partially located in different layers, onto the substrate at least partially overlap.

3. The substrate according to claim 1, wherein, The planarization layer in the Mth interlayer dielectric layer is in contact with the planarization layer in the (M-1)th interlayer dielectric layer through multiple second vias.

4. The substrate according to any one of claims 1-3, wherein, At least a portion of the first vias have non-overlapping orthogonal projections onto the substrate.

5. The substrate according to any one of claims 1-3, wherein, The passive device further includes a capacitor, which includes a first electrode plate and a second electrode plate arranged sequentially along the side away from the substrate; the first electrode plate is disposed in the same layer as one of the plurality of open-loop portions and is made of the same material.

6. The substrate according to claim 5, wherein, The first electrode plate is disposed in the same layer as the first of the plurality of open-loop portions disposed in the direction away from the substrate, and is directly electrically connected.

7. The substrate according to claim 5, wherein, The thickness ratio of the second electrode plate to the first electrode plate is 1:100 to 1:

30.

8. The substrate according to claim 5, wherein, The substrate further includes a first connecting portion, which is electrically connected to the second electrode plate. The first connecting portion is disposed in the same layer as the last of the plurality of open-loop portions disposed in the direction away from the substrate.

9. The substrate according to claim 5, wherein, The substrate further includes a transition section, which is disposed on the same layer as any one or more of the plurality of open-loop sections located between the first and the last.

10. A method for fabricating a substrate integrating passive devices, comprising: A substrate is provided, and a passive device is formed on the substrate, the passive device including an inductor; the inductor includes a plurality of open-loop portions arranged sequentially and connected in a direction away from the substrate; wherein... The steps for forming the inductor include: Multiple open-loop portions and an interlayer dielectric layer covering the open-loop portions are sequentially formed on the substrate. The adjacent open-loop portions are electrically connected through a first via penetrating the interlayer dielectric layer. The orthographic projections of any two open-loop portions on the substrate at least partially overlap. The interlayer dielectric layer includes a first passivation layer, a planarization layer, and a second passivation layer sequentially disposed along the direction away from the substrate; the substrate includes N interlayer dielectric layers; the method further includes forming a second via penetrating the second passivation layer in the (M-1)th interlayer dielectric layer and the first passivation layer in the Mth interlayer dielectric layer, so that the planarization layer in the Mth interlayer dielectric layer contacts the planarization layer in the (M-1)th interlayer dielectric layer; N≥2, 2≤M≤N, and M and N are both integers.

11. The preparation method according to claim 10, wherein, The steps for forming the open-loop portion include: A metal thin film is formed on the substrate as a seed layer; A sacrificial layer is formed on the side of the seed layer away from the substrate, and a groove corresponding to the open ring portion is etched into the sacrificial layer. The seed layer is electroplated to form a metallic material in the groove portion; The seed layer is removed, and the metal material outside the groove is removed by a patterning process to form the open ring portion.

12. The preparation method according to claim 10, wherein, The passive device also includes a capacitor, and the steps of forming the capacitor include: forming a first electrode plate and a second electrode plate sequentially along a side away from the substrate; the first electrode plate and one of the plurality of open-loop portions are formed in the same patterning process.

13. The preparation method according to claim 12, wherein, The first electrode plate and the first of the plurality of open-loop portions disposed in the direction away from the substrate are formed in the same patterning process.

Images