A clock signal generation apparatus based on dynamic configuration
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 无锡亚科鸿禹电子有限公司
- Filing Date
- 2022-12-21
- Publication Date
- 2026-06-26
Smart Images
Figure CN116382419B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of clock generation technology, and more specifically to a clock signal generation device based on dynamic configuration. Background Technology
[0002] For control devices such as controllers, processors, or control boards, clock resources are a crucial component. Taking an FPGA as an example, it uses a PLL (Phase-Locked Loop) and an MMCM (Mill Manager for Clocking) to output clock signals. Different FPGA series have different PLLs and MMCMs, specifically varying the number of clock output ports and the composition of their configuration data. In practice, PLLs and MMCMs are typically configured to output the desired clock signal. Changing the state of the clock signal output requires reconfiguration, which is time-consuming due to the need to generate a new bit file each time, resulting in a slow clock generation rate. This bit file contains selection data for the PLL and MMCM, as well as parameter data for the clock signal output from each clock output port. Summary of the Invention
[0003] In view of the shortcomings of the prior art, the present invention provides a clock signal generation device based on dynamic configuration. The technical problem to be solved is that when the clock signals output by the clock output ports of the existing MMCM and PLL change, it is necessary to generate a bit file including the selection data of PLL and MMCM and the parameter data of the clock signals output by each clock output port, which is time-consuming and slow.
[0004] To solve the above technical problems, the present invention provides the following technical solution: a clock signal generation device based on dynamic configuration, comprising...
[0005] M MMCMs and N PLLs, where M and N are both positive integers;
[0006] The configuration data generation unit generates configuration data based on the clock data from the input clock output port;
[0007] The calculation unit calculates the number of MMCMs and PLLs required for the output target clock. Assume that the required number of MMCMs is A and the required number of PLLs is B, where A is a natural number less than or equal to M and B is a natural number less than or equal to N.
[0008] The parsing unit is used to select A MMCMs from all MMCMs and B PLLs from all PLLs, and to generate A+B parsing subunits. Each parsing subunit corresponds to a selected MMCM or a selected PLL, and obtains configuration data and distributes the configuration data to the parsing subunits. The parsing subunits write the received configuration data into the corresponding MMCM or PLL.
[0009] In one implementation, the computing unit calculates the number of MMCMs and PLLs required to output the target number of clock cycles as follows:
[0010] The clock output port includes a first clock output port and a second clock output port; the clock output port of the MMCM is the first clock output port, and the total number of clock output ports of a single MMCM is denoted as V; the clock output port of the PLL is the second clock output port, and the total number of clock output ports of a single PLL is denoted as W.
[0011] Input the number of the first clock output ports required into the computing unit, denoted as J; input the number of the second clock output ports required into the computing unit, denoted as K; when J is divisible by V, A = J / V, otherwise A is an integer of J / V plus one; when K is divisible by W, B = K / W, otherwise B is an integer of K / W plus one.
[0012] In one implementation, the parsing unit sets an identification address for the selected MMCM and PLL; the configuration data includes X-bit clock parameter data, Y-bit register address data, and Z-bit identification address data; the Z-bit identification address data of the configuration data of the same MMCM is the same, the Z-bit identification address data of the configuration data of the same PLL is the same, and the Z-bit identification address data of each MMCM and PLL is different.
[0013] The parsing unit distributes the configuration data to the parsing subunits corresponding to the MMCM or PPL whose identification address is the same as the Z-bit identification address data. The parsing subunits write the X-bit clock parameter data into the corresponding MMCM or PLL register according to the Y-bit register address data.
[0014] In one implementation, the process of setting the Z-bit identification address data of the configuration data is as follows:
[0015] The configuration data generation unit takes the clock data of V first clock output ports that are not grouped as a group of MMCM clock data. When the number of ungrouped first clock output ports is less than V, the clock data of all ungrouped first clock output ports are taken as a group of MMCM clock data. The Z-bit identification address data of the configuration data corresponding to a group of MMCM clock data are the same.
[0016] The configuration data generation unit takes the clock data of W ungrouped second clock output ports as a group of PLL clock data. When the number of ungrouped second clock output ports is less than W, it takes the clock data of all ungrouped second clock output ports as a group of PLL clock data. The Z-bit identification address data of the configuration data corresponding to a group of PLL clock data are the same.
[0017] In one implementation, for all groups of MMCM clock data, the Z-bit identification address data of the configuration data corresponding to each group of MMCM clock data increments sequentially according to the generation order of each group of MMCM clock data;
[0018] For all groups of PLL clock data, the Z-bit identification address data of the configuration data corresponding to each group of PLL clock data increments sequentially according to the generation order of each group of PLL clock data.
[0019] In one embodiment, the configuration data further includes H-bit judgment data and a judgment unit. The configuration data is first input to the judgment unit. When the H-bit judgment data is greater than the judgment threshold, the judgment unit sends the X-bit clock parameter data, Y-bit register address data and Z-bit identification address data of the configuration data to the parsing unit.
[0020] The beneficial effects of this invention compared with the prior art are as follows: In practical use, since this invention can select the MMCM and PLL output clock signals through the calculation unit and the parsing unit, when it is necessary to change the clock signals output by the clock output ports of the MMCM and PLL, it is not necessary to reselect which MMCM and which PLL to output clock signals. It is only necessary to reconfigure the data of the already selected MMCM and PLL, thereby reducing the amount of configuration data required when changing the output clock signals and improving the configuration speed.
[0021] Furthermore, this invention, by selecting MMCM and PLL from all MMCMs and PLLs to output the clock signal, offers high flexibility and strong applicability.
[0022] Finally, when a large number of clocks are required, the corresponding number of MMCMs and PLLs can be selected through the calculation unit and parsing unit of this invention, and then the configuration data of the clock output port of each MMCM and PLL can be configured through the configuration data generation unit, which can meet the needs of large-scale clock usage. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of the first structure of the present invention in the embodiments;
[0024] Figure 2 This is a schematic diagram of the first structure of the configuration data in the embodiment;
[0025] Figure 3 This is a schematic diagram of the second structure of the present invention in the embodiments;
[0026] Figure 4 This is a schematic diagram of a second structure of the configuration data in the embodiment.
[0027] In the diagram: 1. MMCM, 2. PLL, 3. Configuration data generation unit, 4. Calculation unit, 5. Parsing unit, 6. Judgment unit, 50. Parsing sub-unit. Detailed Implementation
[0028] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.
[0029] like Figure 1 As shown, a clock signal generation device based on dynamic configuration includes...
[0030] Two MMCM1s and two PL2Ls;
[0031] Configuration data generation unit 3 generates configuration data based on the clock data from the input clock output port;
[0032] Calculation unit 4 calculates the number of MMCMs and PLLs required for the output target clock. Assume that the required number of MMCMs is A and the required number of PLLs is B, where A is a natural number less than or equal to 2 and B is a natural number less than or equal to 2.
[0033] The parsing unit 5 is used to select A MMCM1s from all MMCM1s and B PLL2s from all PLL2s, and to generate A+B parsing subunits 50. Each parsing subunit 50 corresponds to a selected MMCM1 or a selected PLL2, and obtains configuration data and distributes the configuration data to the parsing subunit 50. The parsing subunit 50 writes the received configuration data into the corresponding MMCM1 or PLL2.
[0034] In practical use, the number of clock output ports of a single MMCM1 and a single PLL2 is fixed. Therefore, the number of MMCM1 and PLL2 can be increased according to the required number of clocks and clock type, and is not necessarily limited to a fixed number. Figure 1 The diagram shows two MMCM1s and two PLL2s. When a larger number of clocks are required, the number of MMCM1s and PLL2s can be increased.
[0035] In practical use, since the present invention selects MMCM1 and PLL2 to output clock signals through the calculation unit 4 and the parsing unit 5, and the selected MMCM1 and PLL2 then output corresponding clock signals through configuration data, when it is necessary to change the clock signals output by the selected MMCM1 and PLL2, only the configuration data of MMCM1 and PLL2 needs to be changed. Unlike the prior art, it is not necessary to generate selection data and parameter data for MMCM1 and PLL2, thereby reducing the configuration data required when changing the output clock signals and improving the configuration speed.
[0036] In this embodiment, the calculation unit 4 calculates the number of MMCM1 and PLL2 required to output the target number of clocks in the following way:
[0037] The clock output ports include a first clock output port and a second clock output port; the clock output port of MMCM1 is the first clock output port, and the total number of clock output ports of a single MMCM1 is denoted as V; the clock output port of PLL2 is the second clock output port, and the total number of clock output ports of a single PL2L is denoted as W.
[0038] Input the number of the first clock output ports required into the calculation unit 4, denoted as J; input the number of the second clock output ports required into the calculation unit 4, denoted as K; when J is divisible by V, A = J / V, otherwise A is an integer of J / V plus one; when K is divisible by W, B = K / W, otherwise B is an integer of K / W plus one.
[0039] More specifically, when the number of first clock output ports of a single MMCM1 is 7 and the number of second clock output ports of a single PLL2 is 2, if the required number of first clock output ports is 6 (J = 6) when inputting to the calculation unit 4, A = 1; if the required number of second clock output ports is 1 (K = 1) when inputting to the calculation unit 4, B = 1. At this time, the parsing unit 5 needs to generate two parsing subunits 50: one MMCM1 is selected from all MMCM1s, and one parsing subunit 50 writes configuration data to the selected MMCM1, causing its six first clock output ports to output clock signals; and one PLL2 is selected from all PLL2s, and the other parsing subunit 50 writes configuration data to the selected PLL2, causing its second clock output port to output clock signals.
[0040] In this embodiment, the configuration data generated by the configuration data generation unit 3 includes X-bit clock parameter data, Y-bit register address data, and Z-bit identification address data. The Z-bit identification address data of the configuration data of the same MMCM is the same, the Z-bit identification address data of the configuration data of the same PLL is the same, and the Z-bit identification address data of each MMCM and PLL is different. The Y-bit register address data is used to store the address of the register of MMCM1 or PLL2 to which the X-bit clock parameter data is to be written. The Z-bit identification address data is used to determine which selected MMCM1 or PLL2 to write the configuration data to.
[0041] The parsing unit 5 sets the identification address for the selected MMCM and PLL. The parsing unit 5 distributes the configuration data to the parsing subunit 50 corresponding to MMCM1 or PPL2 whose identification address is the same as the Z-bit identification address data. The parsing subunit 50 writes the X-bit clock parameter data to the corresponding MMCM1 or PLL2 register according to the Y-bit register address data.
[0042] Reference Figure 2 In this embodiment, the configuration data is 32-bit binary data, where bits 0-1 are reserved, bits 2-17 are clock parameter data, bits 18-24 are register address data, and bits 25-31 are identification address data. In practical use, when the number of MMCM1 and PLL2 is large, the number of bits in the configuration data can be increased to increase the number of bits in the identification address, thereby setting identification addresses for more MMCM1 or PLL2. Conversely, when the number of MMCM1 and PLL2 is small, some bits from 25-31 can be selected as identification address data; it is not necessary to use all bits.
[0043] In this embodiment, the process of setting the Z-bit identification address data of the configuration data is as follows:
[0044] In actual use, users input the clock data of each clock output port on the configuration data generation unit 3. The clock data includes at least the clock output port type, clock frequency and clock phase. The clock output port type is used to determine whether the clock signal is output from the first clock output port of MMCM1 or the second clock output port of PLL2.
[0045] The configuration data generation unit 3 takes the clock data of V first clock output ports that are not grouped as a group of MMCM clock data. When the number of ungrouped first clock output ports is less than V, the clock data of all ungrouped first clock output ports are taken as a group of MMCM clock data. The Z-bit identification address data of the configuration data corresponding to a group of MMCM clock data are the same.
[0046] The configuration data generation unit 3 takes the clock data of W ungrouped second clock output ports as a group of PLL clock data. When the number of ungrouped second clock output ports is less than W, it takes the clock data of all ungrouped second clock output ports as a group of PLL clock data. The Z-bit identification address data of the configuration data corresponding to a group of PLL clock data are the same.
[0047] In actual use, the rules for setting the Z-bit identification address data of the configuration data corresponding to each group of MMCM clock data by the configuration data generation unit 3 are the same as the rules for setting the identification address of the selected MMCM1 by the parsing unit 5. The rules for setting the Z-bit identification address data of the configuration data corresponding to each group of PLL clock data by the configuration data generation unit 3 are the same as the rules for setting the identification address of the selected PLL2 by the parsing unit 5.
[0048] Among them, for all groups of MMCM clock data, the Z-bit identification address data of the configuration data corresponding to each group of MMCM clock data increases sequentially according to the generation order of each group of MMCM clock data;
[0049] For all groups of PLL clock data, the Z-bit identification address data of the configuration data corresponding to each group of PLL clock data increases sequentially according to the generation order of each group of PLL clock data;
[0050] The parsing unit 3 sets the identification address of the selected MMCM1 in ascending order, and sets the identification address of the selected PLL2 in ascending order.
[0051] In practical use, clock signals are divided into controlled clocks and uncontrolled clocks according to different control methods. The control method of this invention is an uncontrolled clock, and MMCM1 and PLL2 output clock signals according to configuration data. When a clock system simultaneously has controlled and uncontrolled clocks and both configure data to the controlled and uncontrolled clocks, for ease of distinction, as follows... Figure 3 As shown, the present invention also includes a judgment unit 6, and the configuration data includes H-bit judgment data. The configuration data is first input to the judgment unit 6. When the H-bit judgment data is greater than the judgment threshold, the judgment unit 6 sends the X-bit clock parameter data, Y-bit register address data and Z-bit identification address data of the configuration data to the parsing unit 5.
[0052] The configuration data generation unit 3 sets the size of the H-bit judgment data according to whether the clock data is to be input to a controlled clock or an uncontrolled clock. When the clock data is to be input to an uncontrolled clock, the H-bit judgment data is set to be greater than the judgment threshold. When the clock data is to be input to a controlled clock, the H-bit judgment data is set to be less than the judgment threshold.
[0053] Indicative, for reference Figure 4 ,exist Figure 2 Based on the configuration data shown, Figure 4 The configuration data structure shown includes 48 bits of binary data, of which bits 31-47 are decision data.
[0054] In summary, since the present invention can select the clock signals of MMCM1 and PLL2 through the calculation unit 4 and the parsing unit 5, when it is necessary to change the clock signals output by the clock output ports of MMCM1 and PLL2, it is not necessary to reselect which MMCM1 and which PLL2 to output the clock signal. It is only necessary to reconfigure the data of the already selected MMCM1 and PLL2, thereby reducing the configuration data required when changing the output clock signals and improving the configuration speed.
[0055] Furthermore, this invention, by selecting MMCM1 and PLL2 from all MMCM1 and PLL2 to output the clock signal, has high flexibility and strong applicability.
[0056] Finally, when a large number of clocks are required, the corresponding number of MMCM1 and PLL2 can be selected through the calculation unit 4 and the parsing unit 5 of the present invention, and then the configuration data of the clock output port of each MMCM1 and PLL2 can be configured through the configuration data generation unit 4, which can meet the needs of large-scale clock usage.
[0057] Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.
Claims
1. A clock signal generation device based on dynamic configuration, characterized in that, include M MMCMs and N PLLs, where M and N are both positive integers; The configuration data generation unit generates configuration data based on the clock data from the input clock output port; The calculation unit calculates the number of MMCMs and PLLs required for the output target clock. Assume that the required number of MMCMs is A and the required number of PLLs is B, where A is a natural number less than or equal to M and B is a natural number less than or equal to N. The parsing unit is used to select A MMCMs from all MMCMs and B PLLs from all PLLs, and to generate A+B parsing subunits. Each parsing subunit corresponds to a selected MMCM or a selected PLL, and obtains configuration data and distributes the configuration data to the parsing subunits. The parsing subunits write the received configuration data into the corresponding MMCM or PLL.
2. The clock signal generation device based on dynamic configuration according to claim 1, characterized in that, The calculation unit calculates the number of MMCMs and PLLs required for the output target clock as follows: The clock output port includes a first clock output port and a second clock output port; the clock output port of the MMCM is the first clock output port, and the total number of clock output ports of a single MMCM is denoted as V; the clock output port of the PLL is the second clock output port, and the total number of clock output ports of a single PLL is denoted as W. Input the number of the first clock output ports required into the computing unit, denoted as J; input the number of the second clock output ports required into the computing unit, denoted as K; when J is divisible by V, A = J / V, otherwise A is an integer of J / V plus one; when K is divisible by W, B = K / W, otherwise B is an integer of K / W plus one.
3. The clock signal generation device based on dynamic configuration according to claim 2, characterized in that, The parsing unit sets the identification address for the selected MMCM and PLL; the configuration data includes X-bit clock parameter data, Y-bit register address data, and Z-bit identification address data; the Z-bit identification address data of the configuration data of the same MMCM is the same, the Z-bit identification address data of the configuration data of the same PLL is the same, and the Z-bit identification address data of each MMCM and PLL is different. The parsing unit distributes the configuration data to the parsing subunits corresponding to the MMCM or PPL whose identification address is the same as the Z-bit identification address data. The parsing subunits write the X-bit clock parameter data into the corresponding MMCM or PLL register according to the Y-bit register address data.
4. The clock signal generation device based on dynamic configuration according to claim 3, characterized in that, The process for setting the Z-bit identification address data in the configuration data is as follows: The configuration data generation unit takes the clock data of V first clock output ports that are not grouped as a group of MMCM clock data. When the number of ungrouped first clock output ports is less than V, the clock data of all ungrouped first clock output ports are taken as a group of MMCM clock data. The Z-bit identification address data of the configuration data corresponding to a group of MMCM clock data are the same. The configuration data generation unit takes the clock data of W ungrouped second clock output ports as a group of PLL clock data. When the number of ungrouped second clock output ports is less than W, it takes the clock data of all ungrouped second clock output ports as a group of PLL clock data. The Z-bit identification address data of the configuration data corresponding to a group of PLL clock data are the same.
5. A clock signal generation device based on dynamic configuration according to claim 4, characterized in that, For all groups of MMCM clock data, the Z-bit identification address data of the configuration data corresponding to each group of MMCM clock data increases sequentially according to the generation order of each group of MMCM clock data; For all groups of PLL clock data, the Z-bit identification address data of the configuration data corresponding to each group of PLL clock data increments sequentially according to the generation order of each group of PLL clock data.
6. The clock signal generation device based on dynamic configuration according to claim 3, characterized in that, The configuration data also includes H-bit judgment data and a judgment unit. The configuration data is first input to the judgment unit. When the H-bit judgment data is greater than the judgment threshold, the judgment unit sends the X-bit clock parameter data, Y-bit register address data and Z-bit identification address data of the configuration data to the parsing unit.