Operation method and device based on coprocessor, storage medium and electronic equipment
By setting up two register groups between the central processing unit (CPU) and the coprocessor, the CPU configures the operands and methods, and the coprocessor hardware triggers the reading of the calculation results, thus solving the problems of high CPU resource consumption and slow calculation speed, and improving the calculation efficiency and result acquisition speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHUHAI HUGE IC CO LTD
- Filing Date
- 2023-02-28
- Publication Date
- 2026-06-12
Smart Images
Figure CN116382893B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computers, and more particularly to a coprocessor-based computing method, apparatus, storage medium, and electronic device. Background Technology
[0002] A coprocessor is a processor developed and used to assist the central processing unit (CPU) in performing processing tasks that the CPU cannot execute or execute efficiently or effectively. In related technologies, the method of using a coprocessor to perform computational tasks involves: the coprocessor having operand registers, result registers, control registers, and status registers; the coprocessor executing the computational task includes: the CPU configuring the operand registers and control registers; the CPU waiting for the status register to complete; and the CPU reading the result from the result register. The problems with this approach are: the CPU needs to move operands to the coprocessor's operand registers, which consumes significant CPU resources and slows down the computation speed if the operand width is large. Furthermore, the CPU needs to query the coprocessor's status register through software to confirm the completion of the computational task, which consumes code space and increases the CPU's execution time. Summary of the Invention
[0003] This application provides a coprocessor-based computing method, apparatus, storage medium, and electronic device, which can improve computing efficiency when using a coprocessor. The technical solution is as follows:
[0004] In a first aspect, embodiments of this application provide a coprocessor-based computation method, the method comprising:
[0005] It is applied to a central processing unit and a coprocessor, wherein the coprocessor has a first register group and a second register group, and both the first register group and the second register group include a first operand register, a second operand register, a control register and a result register;
[0006] The method includes:
[0007] The central processing unit performs the following configuration on the first register group: configuring the address of the first operand in the first operand register, configuring the address of the second operand in the second operand register, configuring the operation mode in the control register, and sending a configuration completion indication signal to the coprocessor after completing the configuration. It then performs the following configuration on the second register group: configuring the address of the first operand in the first operand register, configuring the address of the second operand in the second operand register, configuring the operation mode in the control register, and sending a next configuration completion indication signal to the coprocessor after completing the next configuration.
[0008] After receiving the configuration completion indication signal, the coprocessor reads the address from the first operand register of the first register group and obtains the first operand based on the read address, reads the address from the second operand register of the first register group and obtains the second operand based on the read address, and reads the operation mode from the control register of the first register group.
[0009] The coprocessor performs the current operation based on the first operand, the second operand, and the operation method read, and writes the result of the current operation into the result register of the first register group, and then sends an operation end indication signal to the central processing unit.
[0010] After receiving the end-of-operation indication signal, the central processing unit reads the result of the current operation from the result register of the first register group;
[0011] If the coprocessor receives a configuration completion indication signal after completing the current operation, it reads the address from the first operand register of the second register group and obtains the first operand based on the read address, reads the address from the second operand register of the second register group and obtains the second operand based on the read address, and reads the operation mode from the control register of the second register group.
[0012] The coprocessor performs the current operation based on the first operand, the second operand, and the operation method read, and writes the result of the current operation into the result register of the second register group, and then sends the next operation end indication signal to the central processing unit.
[0013] After receiving the next operation end indication signal, the central processing unit reads the operation result from the result register of the second register group.
[0014] Secondly, embodiments of this application provide a coprocessor-based computing device, the device comprising:
[0015] The central processing unit and the coprocessor, wherein the coprocessor has a first register set and a second register set, and both the first register set and the second register set include a first operand register, a second operand register, a control register and a result register;
[0016] When the central processing unit (CPU) performs this operation, it performs the following configuration on the first register group: configuring the address of the first operand in the first operand register, configuring the address of the second operand in the second operand register, configuring the operation mode in the control register, and sending a configuration completion indication signal to the coprocessor after completing the configuration. It then performs the following configuration on the second register group: configuring the address of the first operand in the first operand register, configuring the address of the second operand in the second operand register, configuring the operation mode in the control register, and sending a next configuration completion indication signal to the coprocessor after completing the next configuration.
[0017] The coprocessor is configured to, after receiving the configuration completion indication signal, read the address in the first operand register of the first register group and obtain the first operand based on the read address, read the address in the second operand register of the first register group and obtain the second operand based on the read address, and read the operation mode in the control register of the first register group.
[0018] The coprocessor is also used to perform the current operation according to the first operand, the second operand, and the operation method read, and to write the result of the current operation into the result register of the first register group, and then send the current operation end indication signal to the central processing unit.
[0019] The central processing unit is also used to read the result of the current operation from the result register of the first register group after receiving the operation completion indication signal;
[0020] The coprocessor is further configured to, if it receives a configuration completion indication signal after completing the current operation, read the address in the first operand register of the second register group and obtain the first operand based on the read address, read the address in the second operand register of the second register group and obtain the second operand based on the read address, and read the operation mode in the control register of the second register group;
[0021] The coprocessor is also used to perform the current operation according to the first operand, the second operand, and the operation method read, and to write the result of the current operation into the result register of the second register group, and then send the next operation end indication signal to the central processing unit.
[0022] The central processing unit is also used to read the result of the current operation from the result register of the second register group after receiving the next operation end indication signal.
[0023] Thirdly, embodiments of this application provide a computer storage medium storing a plurality of instructions adapted for loading by a processor and executing the above-described method steps.
[0024] Fourthly, embodiments of this application provide an electronic device that may include the aforementioned computing device.
[0025] The beneficial effects of the technical solutions provided in some embodiments of this application include at least the following:
[0026] First, when performing computation configuration, the CPU configures the operand addresses in the operand register. Compared to existing technologies that directly configure operands in the operand register, the amount of data written by the CPU is smaller, improving CPU configuration efficiency and reducing computation time. Second, the coprocessor directly triggers the CPU to read the computation results via hardware, resulting in a faster response time compared to existing technologies that use software to query computation results. Third, the coprocessor uses two identical register groups to alternately store the configuration parameters for the current computation and the next computation, allowing for the preparation of configuration parameters for the next computation in advance during the execution of the current computation, further improving computational efficiency. Attached Figure Description
[0027] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a schematic diagram of a coprocessor-based computing device provided in an embodiment of this application;
[0029] Figure 2 This is a flowchart illustrating the coprocessor-based computation method provided in this application embodiment. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0031] The coprocessor-based computing method and apparatus provided in the embodiments of this application will now be described in detail with reference to the accompanying drawings.
[0032] Please see Figure 1 This document provides a schematic diagram of the structure of a coprocessor-based computing device according to an embodiment of this application. Figure 1As shown, a coprocessor-based computing device 100 (hereinafter referred to as device 100) may include: at least one central processing unit 101, at least one communication interface 103, memory 104, at least one communication bus 102, and coprocessor 105.
[0033] The communication bus 102 is used to realize the connection and communication between the above components.
[0034] The communication interface 103 is used to realize communication between external devices or equipment, and may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).
[0035] The coprocessor 105 includes a first register group and a second register group, both having the same number and function of registers. Both the first and second register groups include: a first operand register, a second operand register, a control register, and a result register. The first and second operand registers store the addresses of the operands, with the address length being less than the operand length (e.g., the operand is 32 bits long, and the address is 8 bits long). The control register stores the operation mode, including but not limited to addition, subtraction, multiplication, and division. The result register stores the operation result. The first and second register groups alternately store the relevant parameters for the current operation and the parameters for the next operation to improve computational efficiency.
[0036] The central processing unit 101 may include one or more processing cores. The central processing unit 101 connects to various parts within the device 100 using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 104, and by calling data stored in the memory 104. Optionally, the central processing unit 101 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The central processing unit 101 may integrate one or more of the following: a central processing unit (CPU), a graphics processing unit (GPU), and a modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display on the screen; and the modem handles wireless communication. It is understood that the modem may also not be integrated into the central processing unit 101 and may be implemented as a separate chip.
[0037] The memory 104 may include random access memory (RAM) or read-only memory. Optionally, the memory 104 may include non-transitory computer-readable storage medium. The memory 104 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 104 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 104 may also be at least one storage device located remotely from the aforementioned central processing unit 101. Figure 1 As shown, the memory 104, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and application programs.
[0038] exist Figure 1In the illustrated device 100, the central processing unit 101 can be used to call the application program stored in the memory 104, and the specific steps include: when performing the current operation, the central processing unit 101 performs the current operation configuration on the first register group: configuring the address of the first operand in the first operand register, configuring the address of the second operand in the second operand register, and configuring the operation mode in the control register; after completing the current configuration, the central processing unit 101 sends the current configuration completion indication signal to the coprocessor 102, and performs the next operation configuration on the second register group: configuring the address of the first operand in the first operand register, configuring the address of the second operand in the second operand register, and configuring the operation mode in the control register; after completing the next configuration, the central processing unit 101 sends the next configuration completion indication signal to the coprocessor 102. In this embodiment, the length of the address stored in the first operand register and the second operand register is less than the length of the operand itself. For example, the address length is 8 bits, and the length of the first operand and the second operand is 32 bits. The coprocessor 101 reads the first operand or the second operand from the memory 104 according to the address, or the DMA reads the first operand and the second operand from the memory 104 according to the address. This application does not impose any restrictions. The speed of reading operands is very fast and will not have a significant impact on the operation speed.
[0039] After receiving the configuration completion indication signal, the coprocessor 102 reads the address from the first operand register of the first register group and obtains the first operand based on the read address. It then reads the address from the second operand register of the first register group and obtains the second operand based on the read address. It reads the operation mode from the control register of the first register group, performs the operation based on the obtained first operand, the obtained second operand, and the read operation mode to obtain the result of this operation. The result of this operation is written to the result register of the first register group, and the central processing unit 101 sends an operation completion indication signal. The operands for each operation performed by the coprocessor are stored in the memory 102; that is, the coprocessor 102 retrieves the corresponding first or second operand from the memory 102 based on the address.
[0040] After receiving the end-of-operation indication signal, the central processing unit 101 reads the result of the current calculation from the result register of the first register group.
[0041] After receiving the next configuration completion indication signal, the coprocessor 102 reads the address from the first operand register of the second register group and obtains the first operand based on the read address, reads the address from the second operand register of the second register group and obtains the second operand based on the read address, and reads the operation mode from the control register of the second register group.
[0042] The coprocessor 102 performs the current operation based on the first operand, the second operand, and the operation method read, and writes the result of the current operation into the result register of the second register group, and then sends the next operation end indication signal to the central processing unit 101.
[0043] After receiving the indication signal that the next operation has ended, the central processing unit 101 reads the result of the current operation from the result register in the second register group. This process can be repeated cyclically by the central processing unit 101 and the coprocessor 102.
[0044] In some embodiments of this application, after the coprocessor 102 has completed the current operation and the configuration for the next operation, the central processing unit 102 is in a locked state, which can reduce the processing overhead of the central processing unit 102 and avoid register errors during the operation.
[0045] In some embodiments of this application, the central processing unit has a bit width of 8 bits, and correspondingly, the first operand register and the second operand register have a bit width of 8 bits. The length of the first operand and the second operand in the coprocessor is 32 bits. This can reduce hardware costs and use a low-bit-width central processing unit and a high-bit-width coprocessor to work together to complete the entire operation process.
[0046] Please see Figure 2 This document provides a flowchart illustrating a coprocessor-based computation method as described in an embodiment of this application. Figure 2 As shown, the method described in this application embodiment may include the following steps:
[0047] S201. When performing this operation, the central processing unit performs the following configuration on the first register group: configures the address of the first operand in the first operand register, configures the address of the second operand in the second operand register, configures the operation mode in the control register, and sends a configuration completion indication signal to the coprocessor after completing the configuration. The central processing unit then performs the following configuration on the second register group: configures the address of the first operand in the first operand register, configures the address of the second operand in the second operand register, configures the operation mode in the control register, and sends a configuration completion indication signal to the coprocessor after completing the configuration.
[0048] S202. After receiving the configuration completion indication signal, the coprocessor reads the address from the first operand register of the first register group and obtains the first operand based on the read address. It also reads the address from the second operand register of the first register group and obtains the second operand based on the read address. Finally, it reads the operation mode from the control register of the first register group.
[0049] S203. The coprocessor performs the current operation based on the first operand, the second operand, and the operation method read, and writes the result of the current operation into the result register of the first register group, and then sends an operation end indication signal to the central processing unit.
[0050] S204. After receiving the end-of-operation indication signal, the central processing unit reads the result of the operation from the result register of the first register group.
[0051] S205. If the coprocessor receives the next configuration completion indication signal after completing this operation, it reads the address from the first operand register of the second register group and obtains the first operand based on the read address, reads the address from the second operand register of the second register group and obtains the second operand based on the read address, and reads the operation mode from the control register of the second register group.
[0052] S206. The coprocessor performs the current operation based on the first operand, the second operand, and the operation method read, and writes the result of the current operation into the result register of the second register group, and then sends the next operation end indication signal to the central processing unit.
[0053] S207: After receiving the indication signal that the next operation is over, the central processing unit reads the result of the current operation from the result register in the second register group. After S207 is completed, S201 can be executed to loop the operation process and improve efficiency.
[0054] Among them, the embodiments of this method and Figure 1 The embodiments of the device are based on the same concept, and the specific process can be referred to Figure 1 The description will not be repeated here.
[0055] In this embodiment, firstly, when the central processing unit (CPU) performs arithmetic configuration, it configures the operand addresses in the operand register. Compared to the prior art where operands are directly configured in the operand register, the amount of data written by the CPU is smaller, which improves the CPU's configuration efficiency and reduces computation time. Secondly, the coprocessor directly triggers the CPU to read the computation results through hardware, which has a faster response speed than the prior art where computation results are queried through software. Thirdly, the coprocessor sets up two identical register groups to alternately store the configuration parameters for the current computation and the configuration parameters for the next computation, allowing the configuration parameters for the next computation to be prepared in advance during the execution of the current computation, which can further improve computational efficiency.
[0056] This application also provides an electronic device, which may be a smartphone, tablet computer, laptop computer, desktop computer, etc. In addition to the above-mentioned computing device, the electronic device may also include a housing for housing the above-mentioned circuit, a display screen, and an input device (e.g., keyboard, mouse, or touch screen).
[0057] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic disk, optical disk, read-only memory, or random access memory, etc.
[0058] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.
Claims
1. A coprocessor-based computation method, characterized in that, It is applied to a central processing unit and a coprocessor, wherein the coprocessor has a first register group and a second register group, and both the first register group and the second register group include a first operand register, a second operand register, a control register and a result register; The method includes: The central processing unit performs the following configuration on the first register group: configuring the address of the first operand in the first operand register, configuring the address of the second operand in the second operand register, configuring the operation mode in the control register, and sending a configuration completion indication signal to the coprocessor after completing the configuration. It then performs the following configuration on the second register group: configuring the address of the first operand in the first operand register, configuring the address of the second operand in the second operand register, configuring the operation mode in the control register, and sending a next configuration completion indication signal to the coprocessor after completing the next configuration. After receiving the configuration completion indication signal, the coprocessor reads the address from the first operand register of the first register group and obtains the first operand based on the read address, reads the address from the second operand register of the first register group and obtains the second operand based on the read address, and reads the operation mode from the control register of the first register group. The coprocessor performs the current operation based on the first operand, the second operand, and the operation method read, and writes the result of the current operation into the result register of the first register group, and then sends an operation end indication signal to the central processing unit. After receiving the end-of-operation indication signal, the central processing unit reads the result of the current operation from the result register of the first register group; If the coprocessor receives a configuration completion indication signal after completing the current operation, it reads the address from the first operand register of the second register group and obtains the first operand based on the read address, reads the address from the second operand register of the second register group and obtains the second operand based on the read address, and reads the operation mode from the control register of the second register group. The coprocessor performs the current operation based on the first operand, the second operand, and the operation method read, and writes the result of the current operation into the result register of the second register group, and then sends the next operation end indication signal to the central processing unit. After receiving the next operation end indication signal, the central processing unit reads the operation result from the result register of the second register group.
2. The method according to claim 1, characterized in that, The operations include addition, subtraction, division, and multiplication.
3. The method according to claim 1 or 2, characterized in that, Also includes: If the coprocessor has not completed the current operation and the next configuration has been completed, the central processing unit is locked.
4. The method according to claim 3, characterized in that, The central processing unit has a bit width of 8 bits, and the first operand and the second operand are 32 bits long.
5. A coprocessor-based computing device, characterized in that, The device includes a central processing unit and a coprocessor. The coprocessor has a first register set and a second register set built in it. Both the first register set and the second register set include a first operand register, a second operand register, a control register, and a result register. When the central processing unit (CPU) performs this operation, it performs the following configuration on the first register group: configuring the address of the first operand in the first operand register, configuring the address of the second operand in the second operand register, configuring the operation mode in the control register, and sending a configuration completion indication signal to the coprocessor after completing the configuration. It then performs the following configuration on the second register group: configuring the address of the first operand in the first operand register, configuring the address of the second operand in the second operand register, configuring the operation mode in the control register, and sending a next configuration completion indication signal to the coprocessor after completing the next configuration. The coprocessor is configured to, after receiving the configuration completion indication signal, read the address in the first operand register of the first register group and obtain the first operand based on the read address, read the address in the second operand register of the first register group and obtain the second operand based on the read address, and read the operation mode in the control register of the first register group. The coprocessor is also used to perform the current operation according to the first operand, the second operand, and the operation method read, and to write the result of the current operation into the result register of the first register group, and then send the current operation end indication signal to the central processing unit. The central processing unit is also used to read the result of the current operation from the result register of the first register group after receiving the operation completion indication signal; The coprocessor is further configured to, if it receives a configuration completion indication signal after completing the current operation, read the address in the first operand register of the second register group and obtain the first operand based on the read address, read the address in the second operand register of the second register group and obtain the second operand based on the read address, and read the operation mode in the control register of the second register group; The coprocessor is also used to perform the current operation according to the first operand, the second operand, and the operation method read, and to write the result of the current operation into the result register of the second register group, and then send the next operation end indication signal to the central processing unit. The central processing unit is also used to read the result of the current operation from the result register of the second register group after receiving the next operation end indication signal.
6. A computer storage medium, characterized in that, The computer storage medium stores multiple instructions, which are adapted to be loaded by a processor and executed as described in any one of claims 1 to 4.
7. An electronic device, characterized in that, include: The computing device as described in claim 5.