A data transmission system and method

Abstract

This disclosure relates to a data transmission system and method. The system includes a first central processing unit (CPU), a second CPU, a first neural network processor (NPU), a second NPU, a first conversion unit, a second conversion unit, a third conversion unit, a fourth conversion unit, and an Ethernet switching chip. The data transmission method of this system can isolate the main functional modules of the PCIe bus, which is prone to single-point failures, through Ethernet conversion. In the event of a single CPU failure, the corresponding NPU will not fail, or vice versa. This reduces the impact of a single functional module failure on other functional modules, further decoupling the modules of the data transmission system, ensuring data transmission stability, and simultaneously reducing the impact of a single module failure on the entire system, thereby improving the security and stability of the entire data transmission system.

Description

Technical Field

[0001] This disclosure relates to the field of autonomous driving computing architecture, and in particular to a data transmission system and method. Background Technology

[0002] In the field of computing power architecture for autonomous driving, controllers are generally composed of multiple cascaded System-on-Chip (SoC) chips. These SoCs require data transmission with relatively large bandwidth, such as transmitting video stream data and LiDAR point cloud data. Currently, data transmission between multiple SoC chips is generally achieved through Ethernet cascading. For data transmission with even greater bandwidth, it is generally necessary to use PCIe (Peripheral Component Interconnect Express) cascading to complete the data transmission.

[0003] In existing technologies, both Ethernet cascading and PCIe cascading have their corresponding use cases. Ethernet cascading is more widely used, requiring the raw data to be packaged and transmitted according to the Ethernet protocol. Its latency is lower than that of PCIe cascading. PCIe cascading is suitable for point-to-point cascading and master-slave cascading, with large data bandwidth and low latency. However, due to the inherent characteristics of the PCIe bus, when the CPU and NPU transmit data based on the PCIe bus standard, the failure of a single CPU or NPU can lead to the failure of its corresponding NPU or CPU, thus preventing the data transmission required between SoCs. Furthermore, the failure of a single module can easily lead to the failure of the entire system equipped with the CPU and NPU, causing system restarts and compromising the overall functional safety of the system. Summary of the Invention

[0004] This disclosure provides a data transmission method, apparatus, device, and storage medium to at least solve the problems in related technologies where a single CPU failure leads to the failure of the corresponding NPU, or a single NPU failure leads to the failure of the corresponding CPU, or a single module failure causes the entire data transmission system to restart. The technical solution of this disclosure is as follows:

[0005] According to one aspect of the embodiments of this disclosure, a data transmission control system is provided, comprising:

[0006] The system comprises a first central processing unit (CPU), a second CPU, a first neural network processor (NPU), a second NPU, a first conversion unit, a second conversion unit, a third conversion unit, a fourth conversion unit, and an Ethernet switching chip. The first conversion unit, the second conversion unit, the third conversion unit, and the fourth conversion unit are each connected to the Ethernet switching chip via their respective Ethernet buses. The first CPU is connected to the first conversion unit via a first high-speed serial computer expansion bus standard PCIe bus, the second CPU is connected to the second conversion unit via a second PCIe bus, the first NPU is connected to the third conversion unit via a third PCIe bus, and the second NPU is connected to the fourth conversion unit via a fourth PCIe bus.

[0007] In the event of a failure of the first NPU, the first CPU is used to perform calculations on the first target transmission data to obtain the first PCIe data; the first conversion unit is used to convert the first PCIe data into first Ethernet data, and the Ethernet switching chip is used to transmit the first Ethernet data to the fourth conversion unit; the fourth conversion unit is used to convert the first Ethernet data into the first PCIe data, and the second NPU is used to process the first PCIe data.

[0008] In the event of a failure of the first CPU, the second CPU is used to perform calculations on the first target transmission data to obtain the first PCIe data; the second conversion unit is used to convert the first PCIe data into the first Ethernet data, and the Ethernet switching chip is used to transmit the first Ethernet data to the third conversion unit or the fourth conversion unit. The third conversion unit is used to convert the first Ethernet data into the first PCIe data, and the first NPU is used to process the first PCIe data; or, the fourth conversion unit is used to convert the first Ethernet data into the first PCIe data, and the second NPU is used to process the first PCIe data.

[0009] According to one aspect of the embodiments of this disclosure, a data transmission control method is provided, comprising:

[0010] The first CPU performs calculations on the first target data to obtain the first PCIe data, and sends the first PCIe data to the first conversion unit based on the first PCIe bus;

[0011] The first conversion unit converts the first PCIe data into first Ethernet data and sends the first Ethernet data to the Ethernet switching chip based on the corresponding Ethernet bus.

[0012] In the event of a failure in the first NPU, the Ethernet switching chip transmits the first Ethernet data to the fourth conversion unit.

[0013] The fourth conversion unit converts the first Ethernet data into the first PCIE data and sends the first PCIE data to the second NPU based on the fourth PCIE bus.

[0014] The second NPU processes the first PCIe data.

[0015] According to one aspect of the embodiments of this disclosure, another data transmission control method is provided, including:

[0016] In the event of a failure of the first CPU, the second CPU performs calculations on the first target data to obtain the first PCIe data, and sends the first PCIe data to the second conversion unit based on the second PCIe bus.

[0017] The second conversion unit converts the first PCIe data into first Ethernet data and sends the first Ethernet data to the Ethernet switching chip based on the corresponding Ethernet bus;

[0018] The Ethernet switching chip transmits the first Ethernet data to the third or fourth conversion unit;

[0019] The third conversion unit converts the first Ethernet data into the first PCIE data and sends the first PCIE data to the first NPU based on the third PCIE bus;

[0020] The first NPU processes the first PCIe data;

[0021] The fourth conversion unit converts the first Ethernet data into the first PCIE data and sends the first PCIE data to the second NPU based on the fourth PCIE bus.

[0022] The second NPU processes the first PCIe data.

[0023] The technical solutions provided by the embodiments of this disclosure have at least the following beneficial effects:

[0024] The data transmission system includes a first CPU, a second CPU, a first NPU, a second NPU, a first conversion unit, a second conversion unit, a third conversion unit, a fourth conversion unit, and an Ethernet switching chip. This data transmission system enables data transmission between the two CPUs and two NPUs based on the PCIe bus standard. Ethernet conversion isolates the main functional modules, achieving decoupling between modules. That is, the failure of a single CPU (e.g., the first CPU) will not cause the failure of its corresponding NPU (e.g., the second NPU), or vice versa. Other usable modules in the data transmission system can continue data transmission, reducing the impact of a single functional module failure on other functional modules. This improves the reliability of data transmission between the CPU and NPU, and avoids the entire data transmission system restarting due to a single module failure, thus enhancing system stability.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0027] Figure 1 This is a schematic diagram illustrating a data transmission system according to an exemplary embodiment;

[0028] Figure 2 This is a schematic diagram illustrating another data transmission system according to an exemplary embodiment;

[0029] Figure 3 This is a schematic diagram illustrating another data transmission system according to an exemplary embodiment;

[0030] Figure 4 This is a flowchart illustrating another data transmission method according to an exemplary embodiment;

[0031] Figure 5 This is a flowchart illustrating another data transmission method according to an exemplary embodiment;

[0032] Figure 6 This is a schematic diagram illustrating an application environment according to an exemplary embodiment; Detailed Implementation

[0033] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0034] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0035] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for display, data used for analysis, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties.

[0036] Please see Figure 1 , Figure 1 This is a schematic diagram of a data transmission system according to an exemplary embodiment. The system may include a first CPU (Central Processing Unit), a second CPU, a first NPU (Neural-network Processing Unit), a second NPU, a first conversion unit, a second conversion unit, a third conversion unit, a fourth conversion unit, and an Ethernet switching chip.

[0037] In an optional embodiment, the first conversion unit, the second conversion unit, the third conversion unit, and the fourth conversion unit are respectively connected to the Ethernet switching chip based on their respective Ethernet buses. Specifically, the first conversion unit, the second conversion unit, the third conversion unit, and the fourth conversion unit can be PCIe (Peripheral Component Interchange) chips. The InterconnectExpress (High-Speed ​​Serial Computer Expansion Bus) interface and multiple Ethernet interfaces are conversion chips. Specifically, the conversion chip is an integrated circuit chip that can convert between PCIe data and Ethernet data. The first CPU is connected to the first conversion unit via the first PCIe bus, the second CPU is connected to the second conversion unit via the second PCIe bus, the first NPU is connected to the third conversion unit via the third PCIe bus, and the second NPU is connected to the fourth conversion unit via the fourth PCIe bus. Specifically, the first CPU and the second CPU are central processing units that can perform calculations on the first target transmission data to obtain the first PCIe data. Specifically, the first target transmission data is the data to be transmitted. In practical applications, the data to be transmitted can be AI vision algorithm data or video stream data, etc. The first PCIe data is data generated based on the first target transmission data that can be transmitted via the PCIe bus. The first NPU and the second NPU are neural network processors that can perform calculations on the first PCIe data.

[0038] In practical applications, the aforementioned first, second, third, and fourth conversion units can realize the conversion between PCIe data and Ethernet data. Since the bandwidth required for PCIe data transmission is greater than that required for Ethernet data transmission, each of the first to fourth conversion units can have one PCIe interface and multiple Ethernet interfaces. These multiple Ethernet interfaces can be multiple RGMII (Reduced Gigabit Media Independent Interface) or multiple SGMII (Serial Gigabit Media Independent Interface) interfaces, ensuring that the data bandwidth transmitted by the multiple Ethernet interfaces matches the bandwidth transmitted by the PCIe interfaces. The aforementioned first and second CPUs can be automotive CPU chips with corresponding data processing capabilities. Optionally, the operating system running on the automotive CPU chip can include, but is not limited to, Android operating system, QNX (Quick... The first CPU and second CPU can process data transmitted from the first target to obtain first PCIe data during autonomous driving, using either a Unix-like real-time operating system or a RTOS (Real-Time Operating System). The first CPU and second CPU can also process resource-intensive data during autonomous driving, such as LiDAR data, device management data, centralized computing data, and human-machine interaction data. The first NPU and second NPU can be equipped with onboard NPU chips with corresponding data processing capabilities. The operating system on the onboard NPU chip can be, but is not limited to, Linux (GNU / Linux, a Unix-like operating system). By using the corresponding operating system, the first NPU and second NPU can process the received first PCIe data during autonomous driving.

[0039] In an optional embodiment, if the first NPU fails, the first CPU can be used to perform calculations on the first target transmission data to obtain first PCIe data; the first conversion unit can be used to convert the first PCIe data into first Ethernet data, and the Ethernet switching chip can be used to transmit the first Ethernet data to the fourth conversion unit; the fourth conversion unit can be used to convert the first Ethernet data into first PCIe data, and the second NPU can be used to process the first PCIe data, thereby calling the second NPU in the event of a failure of the first NPU to perform data transmission between the first CPU and the second NPU.

[0040] In an optional embodiment, if the first CPU fails, the second CPU can perform calculations on the first target transmission data to obtain first PCIe data; the second conversion unit is used to convert the first PCIe data into first Ethernet data, and the Ethernet switching chip is also used to transmit the first Ethernet data to a third conversion unit or a fourth conversion unit. The third conversion unit is used to convert the first Ethernet data into first PCIe data, and the first NPU is used to process the first PCIe data; or, the fourth conversion unit is used to convert the first Ethernet data into first PCIe data, and the second NPU is used to process the first PCIe data, thereby calling the second CPU in the event of a first CPU failure to perform data transmission between the second CPU and the first NPU, or to perform data transmission between the second CPU and the second NPU.

[0041] In the above embodiments, the data transmission system includes a first CPU, a second CPU, a first NPU, a second NPU, a first conversion unit, a second conversion unit, a third conversion unit, a fourth conversion unit, and an Ethernet switching chip. This data transmission system enables the two CPUs and two NPUs to transmit data based on the PCIe bus standard. Ethernet conversion achieves isolation between the main functional modules, decoupling between modules. That is, a failure of a single CPU will not cause the corresponding NPU to fail, and a failure of a single NPU will not cause the corresponding CPU to fail. Modules in the data transmission system that are functioning normally can continue to complete data transmission, thereby improving the reliability of data transmission between the CPU and NPU, avoiding the impact of a single module failure on the entire data transmission system, and preventing the data transmission system from restarting, thus improving the stability of the data transmission system.

[0042] Please see Figure 2 , Figure 2This is a schematic diagram illustrating another data transmission system according to an exemplary embodiment. In an optional embodiment, the first CPU can be connected to an Ethernet switching chip via a corresponding Ethernet bus. The first CPU is also used to send second Ethernet data to a first NPU or a second NPU. Specifically, the data bandwidth of the second Ethernet data is less than the data bandwidth of the first Ethernet data. In practical applications, the second Ethernet data can be communication data sent by the first CPU to the first NPU or communication data sent by the first CPU to the second NPU. The second CPU is connected to the Ethernet switching chip via a corresponding Ethernet bus. The second CPU is also used to send third Ethernet data to the first NPU or the second NPU. Specifically, the bandwidth of the third Ethernet data is less than the data bandwidth of the first NPU. Regarding the data bandwidth of the first Ethernet data, in practical applications, the second Ethernet data can be communication data sent from the second CPU to the first NPU or communication data sent from the second CPU to the second NPU; the first NPU is connected to the Ethernet switching chip based on the corresponding Ethernet bus, and the first NPU is also used to send fourth Ethernet data to the first CPU or the second CPU. Specifically, the fourth Ethernet data can be working data fed back from the first NPU to the first CPU or the second CPU; the second NPU is connected to the Ethernet switching chip based on the corresponding Ethernet bus, and the second NPU is also used to send fifth Ethernet data to the first CPU or the second CPU. The fifth Ethernet data can be working data fed back from the second NPU to the first CPU or the second CPU.

[0043] In the above embodiments, the first CPU, the second CPU, the first NPU, and the second NPU are directly connected to the Ethernet chip based on their respective Ethernet buses. This allows the two CPUs to transmit communication data to the two NPUs through their respective Ethernet buses, and the two NPUs to feed back working data to the two CPUs through their respective Ethernet buses. This does not occupy the transmission resources of the first to fourth PCIe buses, thus rationally allocating data transmission resources and improving data transmission efficiency.

[0044] Please see Figure 3 , Figure 3 This is a schematic diagram of another data transmission system according to an exemplary embodiment. In an optional embodiment, the data transmission system may further include a logic detection unit and a microcontroller unit. The logic detection unit is connected to a first CPU, a second CPU, a first NPU, and a second NPU, respectively. Specifically, the logic detection unit is used to generate a first fault signal and send the first fault signal to the microcontroller unit when the first NPU fails, or to generate a second fault signal and send the second fault signal to the microcontroller unit when the first CPU fails, or to generate a third fault signal and send the third fault signal to the microcontroller unit when the first CPU and the second CPU fail.

[0045] Specifically, the microcontroller unit is connected to the Ethernet switching chip. The microcontroller unit is used to send a first switching command to the Ethernet switching chip based on a first fault signal, so that the Ethernet switching chip forwards the first Ethernet data to the fourth conversion unit; or it is used to send a second switching command to the Ethernet switching chip based on a second fault signal, so that the Ethernet switching chip forwards the first Ethernet data to the third or fourth conversion unit; or it is used to send a control command to an external device connected to the data transmission system based on a third fault signal, so as to change the working state of the external device, and send a restart command to the Ethernet switching chip, so that the Ethernet switching chip restarts.

[0046] In practical applications, the logic detection unit can be a CPLD (Complex Programmable Logic Device), the microcontroller unit can be an onboard MCU (Microcontroller Unit) carrying low-level autonomous driving control algorithms, and the external device can be an autonomous vehicle. The first, second, and third fault signals sent by the logic detection unit to the microcontroller unit can be interrupt signals or level signals, or bus signals such as SPI (Serial Peripheral Interface) signals or I2C (Inter-Integrated Circuit) signals. The logic detection unit detects the fault status of the data transmission system, generates fault signals according to the fault status, and sends corresponding signals to the microcontroller unit. The microcontroller unit sends the first and second switching instructions or restart instructions to the Ethernet chip based on the received fault signals, and sends control instructions to the external device based on the third fault signal to change the working state of the external device. For example, the onboard MCU (microcontroller unit) initiates an autonomous driving downgrade instruction to the autonomous vehicle (external device), causing the autonomous vehicle in motion to change from Level 4 highly automated driving to Level 2 partially automated driving.

[0047] In the above embodiments, by setting a logic detection unit and a microcontroller unit in the data transmission system, the working status of the data transmission system can be monitored in real time. If the first NPU fails, the logic detection unit can generate a first fault signal and send it to the microcontroller unit. The microcontroller unit then sends a first switching command to the Ethernet switching chip based on the first fault signal. Alternatively, if the first CPU fails, the logic detection unit can generate a second fault signal and send it to the microcontroller unit. The microcontroller unit then sends a second switching command to the Ethernet switching chip based on the second fault signal. Or, if both the first CPU and the second CPU fail, the logic detection unit can generate a third fault signal and send it to the microcontroller unit. The microcontroller unit then sends a restart command to the Ethernet switching chip based on the third fault signal, and simultaneously sends control commands to external devices. The logic detection unit generates corresponding fault signals based on different fault conditions and sends them to the microcontroller unit. The microcontroller unit then sends commands corresponding to the fault signals to the Ethernet switching chip and external devices based on the different fault signals. This allows for timely responses to various fault conditions in the data transmission system, improving the stability and security of the data transmission system.

[0048] Those skilled in the art will understand that Figure 1 , Figure 2 or Figure 3 The structure shown is merely a block diagram of a part of the system structure related to the present disclosure and does not constitute a limitation on the system structure to which the present disclosure is applied. A specific data transmission system may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0049] The following describes an embodiment of a data transmission method based on the above-described data transmission system, such as... Figure 4 As shown, Figure 4 This is a flowchart illustrating a data transmission method according to an exemplary embodiment, the method including the following steps:

[0050] In step S401, the first CPU performs calculations on the first target transmission data to obtain the first PCIe data, and sends the first PCIe data to the first conversion unit based on the first PCIe bus.

[0051] Specifically, the first target transmission data can be AI vision algorithm data or video stream data, etc., and the first PCIe data can be data that can be transmitted through the PCIe bus generated by the first CPU based on the first target transmission data. After the first CPU calculates the first target transmission data to generate the first PCIe data, it sends the first PCIe data to the first conversion unit based on the first PCIe bus.

[0052] In step S403, the first conversion unit converts the first PCIe data into first Ethernet data and sends the first Ethernet data to the Ethernet switching chip based on the corresponding Ethernet bus.

[0053] Specifically, the first conversion unit is an integrated circuit chip that can convert PCIe data to Ethernet data. The first PCIe data can be converted into first Ethernet data through the first conversion unit. The first conversion unit sends the first Ethernet data to the Ethernet switching chip. Specifically, the Ethernet switching chip is used to forward the first Ethernet data to the third conversion unit or the fourth conversion unit.

[0054] In step S405, the Ethernet switching chip transmits the first Ethernet data to the fourth conversion unit in the event of a failure of the first NPU.

[0055] Specifically, in the event of a failure of the first NPU, due to the isolation between the first and second conversion units, the first CPU and the first NPU are not directly connected via the PCIe bus. This ensures that the failure of the first NPU does not affect the normal operation of its corresponding first CPU. In this case, the first CPU in the data transmission system can normally generate the first PCIe data and transmit it to the first conversion unit based on the first PCIe bus. The first conversion unit converts the first PCIe data into first Ethernet data and sends the first Ethernet data to the Ethernet chip. The Ethernet switching chip can then forward the first Ethernet data, which was originally intended to be forwarded to the third conversion unit, to the fourth conversion unit, so that the second NPU, which is in normal operation, can receive and process the first PCIe data.

[0056] In step S407, the fourth conversion unit converts the first Ethernet data into first PCIe data and sends the first PCIe data to the second NPU based on the fourth PCIe bus.

[0057] Specifically, the fourth conversion unit is an integrated circuit chip that can convert PCIe data to Ethernet data. The first Ethernet data can be converted back to the first PCIe data through the fourth conversion unit, and the fourth conversion unit sends the first PCIe data to the second NPU.

[0058] In step S409, the second NPU processes the first PCIe data.

[0059] Specifically, the second NPU is used to process the first PCIe data. In the event of a failure of the first NPU, the second NPU, which is in normal operation, can be invoked to complete the data transmission between the first CPU and the second NPU. In practical applications, the second NPU can process the first PCIe data, generate corresponding control commands, and send corresponding commands to external devices. For example, during the operation of an autonomous vehicle, the second NPU generates display group control commands and camera group control commands based on the first PCIe data, and sends corresponding commands to the display group and camera group of the autonomous vehicle to change the working state of the display group and camera group.

[0060] In the above embodiment, if the first NPU fails, the first CPU can send the first PCIe data to the second NPU. The data passes through the first and fourth conversion units in sequence, first converting it into Ethernet data and then back into PCIe data, and finally reaching the first NPU to complete the transmission. This prevents the failure of a single NPU from causing the corresponding CPU to fail, thus affecting the entire system and improving the stability of the system.

[0061] In an optional embodiment, the above method further includes:

[0062] Determine the total data bandwidth of the Ethernet switching chip;

[0063] Allocate data bandwidth to the first virtual LAN and the second virtual LAN based on the total data bandwidth;

[0064] Specifically, the first virtual local area network (VLAN) is a VLAN between the first CPU, the second NPU, the first conversion unit, the fourth conversion unit, and the Ethernet switching chip; the second VLAN is a VLAN between the second CPU, the second NPU, the second conversion unit, the fourth conversion unit, and the Ethernet switching chip.

[0065] In the above embodiments, due to the limited forwarding capability of the Ethernet switching chip, a first virtual local area network is added to the data path between the first CPU and the second NPU, and a second virtual local area network is added to the data path between the second CPU and the second NPU. This ensures that the two data paths do not compete for data bandwidth or data transmission priority when transmitting data, thereby guaranteeing data transmission latency and transmission quality.

[0066] In an optional embodiment, the above method further includes:

[0067] In the event of a failure in the first NPU, the logic detection unit generates a first fault signal;

[0068] The logic detection unit sends a first fault signal to the microcontroller unit;

[0069] The microcontroller sends a first switching command to the Ethernet switching chip based on the first fault signal, so that the Ethernet switching chip forwards the first Ethernet data to the fourth conversion unit.

[0070] In the above embodiments, the logic detection unit can monitor the working status of the data transmission system in real time. When the logic detection unit detects a fault in the first NPU, it sends a first fault signal to the microcontroller unit. Based on the signal, the microcontroller unit sends a first switching instruction to the Ethernet switching chip to promptly call the second NPU that can operate normally, thereby completing the data transmission between the first CPU and the second NPU and improving the stability and security of the data transmission system.

[0071] The following describes another embodiment of a data transmission method based on the above-described data transmission system, such as... Figure 5 As shown, Figure 5 This is a flowchart illustrating a data transmission method according to an exemplary embodiment, the method including the following steps:

[0072] In step S501, if the first CPU malfunctions, the second CPU performs calculations on the first target transmission data to obtain the first PCIE data, and sends the first PCIE data to the second conversion unit based on the second PCIE bus.

[0073] Specifically, in the event of a failure of the first CPU, due to the isolation between the first and second conversion units, the first CPU and the first NPU are not directly connected via the PCIe bus. This ensures that the failure of the first CPU does not affect the normal operation of its corresponding first NPU. Furthermore, the second CPU and the second NPU are still in normal operation at this time. The second CPU can be invoked first to process the first target transmission data to obtain the first PCIe data. The first target transmission data can be AI vision algorithm data or video stream data, etc. The first PCIe data can be data that can be transmitted via the PCIe bus and generated by the second CPU based on the first target transmission data. After the CPU processes the first target transmission data to generate the first PCIe data, it sends the aforementioned first PCIe data to the second conversion unit via the second PCIe bus.

[0074] In step S503, the second conversion unit converts the first PCIe data into first Ethernet data and sends the first Ethernet data to the Ethernet switching chip based on the corresponding Ethernet bus.

[0075] Specifically, the second conversion unit is an integrated circuit chip that can convert PCIe data to Ethernet data. The first PCIe data can be converted into first Ethernet data through the second conversion unit. The second conversion unit sends the first Ethernet data to the Ethernet switching chip. Specifically, the Ethernet switching chip is used to forward the first Ethernet data to the third or fourth conversion unit.

[0076] In step S505, the Ethernet switching chip transmits the first Ethernet data to the third or fourth conversion unit.

[0077] Specifically, in the event of a CPU failure, due to the isolation between the first and second conversion units, the first CPU and the first NPU are not directly connected via the PCIe bus, thus not affecting the normal operation of the first NPU. In this case, both the first and second NPUs in the data transmission system can receive the first PCIe data. Therefore, after the second conversion unit converts the first PCIe data into first Ethernet data and sends the first Ethernet data to the Ethernet chip, the Ethernet switching chip can forward the first Ethernet data that the first CPU originally intended to forward to the third conversion unit to the third or fourth conversion unit. This allows the first NPU, which is in normal operation, to receive and process the first PCIe data, or the second NPU, which is in normal operation, to receive and process the first PCIe data.

[0078] In step S507, the third conversion unit converts the first Ethernet data into first PCIe data and sends the first PCIe data to the first NPU based on the third PCIe bus.

[0079] Specifically, the third conversion unit is an integrated circuit chip that can convert PCIe data to Ethernet data. The first Ethernet data can be converted back to the first PCIe data through the third conversion unit, and the third conversion unit sends the first PCIe data to the second NPU.

[0080] In step S509, the first NPU processes the first PCIe data.

[0081] Specifically, the first NPU is used to process the first PCIe data. In the event of a failure of the first CPU, the second CPU is invoked to generate the first PCIe data and transmit it to the first NPU in normal operation for processing, thus completing the data transmission between the second CPU and the first NPU. In practical applications, the first NPU can process the first PCIe data, generate corresponding control commands, and send corresponding commands to external devices. For example, during the operation of an autonomous vehicle, the first NPU generates display group control commands and camera group control commands based on the first PCIe data and sends corresponding commands to the display group and camera group of the autonomous vehicle to change the working state of the display group and camera group.

[0082] In step S511, the fourth conversion unit converts the first Ethernet data into first PCIe data and sends the first PCIe data to the second NPU based on the fourth PCIe bus.

[0083] Specifically, the fourth conversion unit is an integrated circuit chip that can convert PCIe data to Ethernet data. The first Ethernet data can be converted back to the first PCIe data through the fourth conversion unit, and the fourth conversion unit sends the first PCIe data to the second NPU.

[0084] In step S513, the second NPU processes the first PCIe data.

[0085] Specifically, the second NPU is used to process the first PCIe data. In the event of a failure of the first CPU, the second CPU is invoked to generate the first PCIe data. The data can also be transferred to the second NPU, which is in normal operation, for processing, thus completing the data transfer between the second CPU and the second NPU.

[0086] In the above embodiments, if the first CPU fails, the second CPU can send the first PCIe data to the first NPU. The data passes through the first and third conversion units, first converting it into Ethernet data and then back into PCIe data, before reaching the first NPU, thus completing the data transmission between the second CPU and the first NPU. Alternatively, the second CPU can send the first PCIe data to the second NPU. The data passes through the second and fourth conversion units, first converting it into Ethernet data and then back into PCIe data, before reaching the second NPU, thus completing the data transmission between the second CPU and the second NPU. This prevents the failure of a single CPU from causing the failure of its corresponding NPU, thereby avoiding the impact of a single CPU failure on the entire system and improving system stability.

[0087] In an optional embodiment, the above method further includes:

[0088] Determine the total data bandwidth of the Ethernet switching chip;

[0089] Allocate data bandwidth to the third and fourth virtual LANs based on the total data bandwidth;

[0090] The third virtual local area network (VLAN) is a VLAN between the second CPU, the first NPU, the second conversion unit, the third conversion unit, and the Ethernet switching chip; the fourth VLAN is a VLAN between the second CPU, the second NPU, the second conversion unit, the fourth conversion unit, and the Ethernet switching chip.

[0091] In the above embodiments, a third virtual local area network is added to the data path from the second CPU to the first NPU, and a fourth virtual local area network is added to the data path from the second CPU to the second NPU, so that the two data paths will not compete for data bandwidth or data transmission priority when transmitting data, thus ensuring data transmission latency and transmission quality.

[0092] In an optional embodiment, the above method further includes:

[0093] In the event of a failure in the first CPU, the logic detection unit generates a second fault signal;

[0094] The logic detection unit sends a second fault signal to the microcontroller unit;

[0095] The microcontroller sends a second switching command to the Ethernet switching chip based on the second fault signal, so that the Ethernet switching chip forwards the first Ethernet data to the third or fourth conversion unit.

[0096] In the above embodiment, when the logic detection unit detects a fault in the first CPU, it sends a second fault signal to the microcontroller unit. Based on the signal, the microcontroller unit sends a second switching instruction to the Ethernet switching chip, so that the Ethernet switching chip forwards the first Ethernet data to the third or fourth conversion unit. This allows the normally operating second CPU to call the first NPU or the second NPU, thereby completing the data transmission between the second CPU and the first NPU, or between the second CPU and the second NPU, to improve the stability of the data transmission system.

[0097] In an optional embodiment, the above method further includes:

[0098] In the event of a failure in the first CPU or the second CPU, the logic detection unit generates a third fault signal.

[0099] The logic detection unit sends a third fault signal to the microcontroller unit;

[0100] The microcontroller sends a restart command to the Ethernet switching chip based on the third fault signal, so that the Ethernet switching chip can restart.

[0101] The microcontroller sends control commands to external devices connected to the data transmission system based on a third fault signal to change the operating state of the external devices.

[0102] In the above embodiment, when the logic detection unit detects that both the first CPU and the second CPU have failed, it sends a third fault signal to the microcontroller unit. Based on the third fault signal, the microcontroller unit sends a restart command to the Ethernet switching chip to restart the Ethernet switching chip. At the same time, based on the third fault signal, the microcontroller unit sends control commands to external devices to change the working state of the external devices. The external devices can be autonomous vehicles. For example, the microcontroller unit sends a safe parking command to the autonomous vehicle.

[0103] The following example, using an autonomous driving scenario, illustrates an embodiment of a data transmission method based on the aforementioned data transmission system. Figure 6 As shown, Figure 6 This is a schematic diagram of an application environment according to an exemplary embodiment. Specifically, the data transmission system can be mounted on an autonomous vehicle that adopts a cockpit-driver integrated centralized domain control management system. The aforementioned data transmission system can communicate with the display screen group and the first camera group of the autonomous vehicle through the first CPU and the second CPU, and communicate with the second camera group of the autonomous vehicle through the first NPU and the second NPU. At the same time, the microcontroller unit of the data transmission system can send control commands to the vehicle control unit (external device) of the autonomous vehicle to change the driving state of the autonomous vehicle.

[0104] Specifically, when all modules are operating normally, the first CPU can receive first video data sent by the first camera group and generate first target transmission data based on the first video data. The first video data can be forward-view driving video data and side-view driving video data captured by the first camera group. Further, the first CPU performs calculations on the first target transmission data to obtain first PCIe data and sends the first PCIe data to the first conversion unit via the first PCIe bus. Further, the first conversion unit converts the first PCIe data into first Ethernet data and sends the first Ethernet data to the Ethernet switching chip via the corresponding Ethernet bus. The Ethernet switching chip transmits the first Ethernet data to the third conversion unit, so that the third conversion unit converts the first Ethernet data into... The first PCIe data is sent to the first NPU via the third PCIe bus. The first NPU receives the first PCIe data, thus completing the data transmission between the first CPU and the first NPU. At the same time, the first NPU processes the received first PCIe data. In practical applications, the first NPU processes the first PCIe data to generate working data (fourth Ethernet data) and feeds it back to the first CPU via the corresponding Ethernet bus, so that the first CPU can generate corresponding control instructions and send them to the autonomous vehicle. For example, during the operation of the autonomous vehicle, the first CPU generates control instructions for the first camera group based on the fourth Ethernet data and sends the instructions to the first camera group of the autonomous vehicle to change the working state of the first camera group.

[0105] Correspondingly, the second CPU can receive the second video data sent by the second camera group and the display data sent by the display group, and generate the second target transmission data. The second video data can be surround-view driving video data, parking driving video data, and cockpit video data captured by the second camera group. Further, the second CPU performs calculations on the second target transmission data to obtain second PCIe data, and sends the second PCIe data to the second conversion unit based on the second PCIe bus. The second conversion unit converts the second PCIe data into sixth Ethernet data, and sends the sixth Ethernet data to the Ethernet switching chip based on the corresponding Ethernet bus. Further, the Ethernet switching chip transmits the sixth Ethernet data to the fourth conversion unit, so that the fourth conversion unit converts the sixth Ethernet data into second PCIe data, and sends the data to the fourth PCIe bus based on the fourth PCIe bus. The CIE bus sends second PCIE data to the second NPU, and the second NPU receives the second PCIE data to complete the data transmission between the second CPU and the second NPU. At the same time, the second NPU processes the second PCIE data. In practical applications, the second NPU can generate working data (fifth Ethernet data) by processing the second PCIE data and feed it back to the second CPU through the corresponding Ethernet bus, so that the second CPU can generate corresponding control commands and send corresponding commands to the autonomous vehicle. For example, during the operation of the autonomous vehicle, the second CPU generates control commands for the second camera group and the display screen based on the fifth Ethernet data fed back by the first NPU, and sends corresponding commands to the second camera group and the display screen group of the autonomous vehicle respectively to change the working state of the second camera group and the display screen group.

[0106] Using the above method, when each module is in normal working condition, data transmission between the first CPU and the first NPU enables AI processing of the forward-looking and side-looking driving videos of the autonomous vehicle. Data transmission between the second CPU and the second NPU enables AI processing of the surround-view, parking, cockpit video, and display screen data of the autonomous vehicle. By using two data paths to transmit the data to be processed, local resources are rationally allocated and utilized, thereby improving data transmission efficiency.

[0107] Optionally, with all modules in normal working condition, the total data bandwidth of the Ethernet switching chip is determined; based on the total data bandwidth, data bandwidth is allocated to the fifth virtual local area network and the sixth virtual local area network; wherein, the fifth virtual local area network is the virtual local area network between the first CPU, the first NPU, the first conversion unit, the third conversion unit and the Ethernet switching chip; the sixth virtual local area network is the virtual local area network between the second CPU, the second NPU, the second conversion unit, the fourth conversion unit and the Ethernet switching chip.

[0108] Optionally, in the event of a failure in the first NPU, the logic detection unit generates a first fault signal and sends it to the microcontroller unit. Based on the first fault signal, the microcontroller unit sends a first switching instruction to the Ethernet switching chip, causing the Ethernet switching chip to forward the first Ethernet data to the fourth conversion unit. The first CPU sends the first PCIe data to the second NPU. This data can pass through the first and fourth conversion units sequentially, first being converted into Ethernet data and then back into first PCIe data, finally reaching the first NPU, completing the data transmission between the first CPU and the second NPU. Simultaneously, the second CPU can send the second PCIe data to the second NPU. This data passes through the second and fourth conversion units sequentially, first being converted into Ethernet data and then back into second PCIe data, reaching the second NPU, completing the data transmission between the first CPU and the second NPU. Correspondingly, the second NPU is responsible for processing the first PCIe data and the second PCIe data.

[0109] Furthermore, a first virtual local area network (VLAN) is added to the data path between the first CPU and the second NPU, and a second VLAN is added to the data path between the second CPU and the second NPU. This ensures that the two data paths do not compete for data bandwidth or data transmission priority when transmitting data, thus guaranteeing data transmission latency and quality.

[0110] Optionally, in the event of a failure in the first CPU, the logic detection unit generates a second fault signal and sends it to the microcontroller unit. Based on the second fault signal, the microcontroller unit sends a second switching instruction to the Ethernet switching chip, causing the Ethernet switching chip to forward the first Ethernet data to the third conversion unit. The second CPU sends the first PCIe data to the first NPU. The data passes through the first and third conversion units sequentially, first being converted into Ethernet data and then back into first PCIe data, before reaching the first NPU, thus completing the data transmission between the second CPU and the first NPU. Simultaneously, the second CPU can send the second PCIe data to the second NPU. This data passes through the second and fourth conversion units sequentially, first being converted into Ethernet data and then back into second PCIe data, before reaching the second NPU, thus completing the data transmission between the second CPU and the second NPU. Correspondingly, the first NPU is responsible for processing the received first PCIe data, and the second NPU is responsible for processing the received second PCIe data.

[0111] Alternatively, in the event of a failure in the first CPU, the logic detection unit generates a second fault signal and sends it to the microcontroller unit. Based on the second fault signal, the microcontroller unit sends a second switching instruction to the Ethernet switching chip, causing the Ethernet switching chip to forward the first Ethernet data to the fourth conversion unit. The second CPU can then send the first PCIe data to the second NPU. The data passes through the second and fourth conversion units sequentially, first being converted into Ethernet data and then back into the first PCIe data, before reaching the second NPU, thus completing the data transmission between the second CPU and the second NPU. Simultaneously, the second CPU can send the second PCIe data to the second NPU. This data passes through the second and fourth conversion units sequentially, first being converted into Ethernet data and then back into the second PCIe data, before reaching the second NPU, thus completing the data transmission between the second CPU and the second NPU. Correspondingly, the second NPU is responsible for processing the first PCIe data and the second PCIe data.

[0112] Furthermore, a third virtual local area network (VLAN) is added to the data path from the second CPU to the first NPU, and a fourth VLAN is added to the data path from the second CPU to the second NPU. This ensures that the two data paths do not compete for data bandwidth or data transmission priority, thus guaranteeing data transmission latency and quality.

[0113] In the above embodiments, on the one hand, the PCIe bus, which is prone to single-point failures, can be isolated from each major functional module through Ethernet conversion, reducing the impact of a single functional module failure on the remaining functional modules, further decoupling the modules, and thus ensuring stable data transmission. On the other hand, by performing logic detection on the major functional modules and using a microcontroller unit, when a certain functional module fails, the data path can be switched in a timely manner based on the instructions issued by the microcontroller unit, reducing the impact of a single module failure on the entire system and improving the security and stability of the entire data transmission system.

[0114] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0115] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A data transmission system, characterized in that, The system includes: The system comprises a first central processing unit (CPU), a second CPU, a first neural network processor (NPU), a second NPU, a first conversion unit, a second conversion unit, a third conversion unit, a fourth conversion unit, and an Ethernet switching chip. The first conversion unit, the second conversion unit, the third conversion unit, and the fourth conversion unit are each connected to the Ethernet switching chip via their respective Ethernet buses. The first CPU is connected to the first conversion unit via a first high-speed serial computer expansion bus standard PCIe bus, the second CPU is connected to the second conversion unit via a second PCIe bus, the first NPU is connected to the third conversion unit via a third PCIe bus, and the second NPU is connected to the fourth conversion unit via a fourth PCIe bus. When all modules are in normal working condition, data is transmitted between the first CPU and the first NPU, and data is transmitted between the second CPU and the second NPU. In the event of a failure of the first NPU, the first CPU is used to perform calculations on the first target transmission data to obtain the first PCIe data; the first conversion unit is used to convert the first PCIe data into first Ethernet data, and the Ethernet switching chip is used to transmit the first Ethernet data to the fourth conversion unit; the fourth conversion unit is used to convert the first Ethernet data into the first PCIe data, and the second NPU is used to process the first PCIe data. In the event of a failure of the first CPU, the second CPU is used to perform calculations on the first target transmission data to obtain the first PCIe data; the second conversion unit is used to convert the first PCIe data into the first Ethernet data, and the Ethernet switching chip is further used to transmit the first Ethernet data to the third conversion unit or the fourth conversion unit, the third conversion unit is used to convert the first Ethernet data into the first PCIe data, and the first NPU is used to process the first PCIe data; or, the fourth conversion unit is used to convert the first Ethernet data into the first PCIe data, and the second NPU is used to process the first PCIe data.

2. The system according to claim 1, characterized in that, The system also includes: The first CPU is connected to the Ethernet switching chip based on a corresponding Ethernet bus. The first CPU is also used to send second Ethernet data to the first NPU or the second NPU. The data bandwidth of the second Ethernet data is less than the data bandwidth of the first Ethernet data. The second CPU is connected to the Ethernet switching chip based on the corresponding Ethernet bus. The second CPU is also used to send third Ethernet data to the first NPU or the second NPU. The bandwidth of the third Ethernet data is less than the data bandwidth of the first Ethernet data. The first NPU is connected to the Ethernet switching chip based on the corresponding Ethernet bus. The first NPU is also used to send fourth Ethernet data to the first CPU or the second CPU. The fourth Ethernet data is the working data fed back by the first NPU to the first CPU or the second CPU. The second NPU is connected to the Ethernet switching chip based on the corresponding Ethernet bus. The second NPU is also used to send fifth Ethernet data to the first CPU or the second CPU. The fifth Ethernet data is the working data fed back by the second NPU to the first CPU or the second CPU.

3. The system according to claim 1, characterized in that, The system also includes: A logic detection unit is connected to the first CPU, the second CPU, the first NPU, and the second NPU respectively. The logic detection unit is used to generate a first fault signal and send the first fault signal to the microcontroller unit when the first NPU fails, or to generate a second fault signal and send the second fault signal to the microcontroller unit when the first CPU fails, or to generate a third fault signal and send the third fault signal to the microcontroller unit when both the first CPU and the second CPU fail. A microcontroller unit is connected to the Ethernet switching chip. The microcontroller unit is used to send a first switching command to the Ethernet switching chip based on the first fault signal, so that the Ethernet switching chip forwards the first Ethernet data to the fourth conversion unit; or to send a second switching command to the Ethernet switching chip based on the second fault signal, so that the Ethernet switching chip forwards the first Ethernet data to the third conversion unit or the fourth conversion unit; or to send a control command to an external device connected to the data transmission system based on the third fault signal, so as to change the working state of the external device, and send a restart command to the Ethernet switching chip, so that the Ethernet switching chip restarts.

4. A data transmission method based on the data transmission system as described in any one of claims 1 to 3, characterized in that, The method includes: The first CPU performs calculations on the first target data to obtain the first PCIe data, and sends the first PCIe data to the first conversion unit based on the first PCIe bus; The first conversion unit converts the first PCIe data into first Ethernet data and sends the first Ethernet data to the Ethernet switching chip based on the corresponding Ethernet bus. In the event of a failure of the first NPU, the Ethernet switching chip transmits the first Ethernet data to the fourth conversion unit. The fourth conversion unit converts the first Ethernet data into the first PCIE data and sends the first PCIE data to the second NPU based on the fourth PCIE bus. The second NPU processes the first PCIe data.

5. The method according to claim 4, characterized in that, The method further includes: Determine the total data bandwidth of the Ethernet switching chip; Based on the total data bandwidth, allocate data bandwidth to the first virtual local area network and the second virtual local area network; The first virtual local area network (VLAN) is a VLAN between the first CPU, the second NPU, the first conversion unit, the fourth conversion unit, and the Ethernet switching chip; the second VLAN is a VLAN between the second CPU, the second NPU, the second conversion unit, the fourth conversion unit, and the Ethernet switching chip.

6. The method according to claim 4, characterized in that, The method further includes: In the event of a malfunction in the first NPU, the logic detection unit generates a first fault signal; The logic detection unit sends the first fault signal to the microcontroller unit; The microcontroller sends a first switching command to the Ethernet switching chip based on the first fault signal, so that the Ethernet switching chip forwards the first Ethernet data to the fourth conversion unit.

7. A data transmission method based on the data transmission system as described in any one of claims 1 to 3, characterized in that, The method includes: In the event of a failure of the first CPU, the second CPU performs calculations on the first target data to obtain the first PCIe data, and sends the first PCIe data to the second conversion unit based on the second PCIe bus. The second conversion unit converts the first PCIe data into first Ethernet data and sends the first Ethernet data to the Ethernet switching chip based on the corresponding Ethernet bus; The Ethernet switching chip transmits the first Ethernet data to the third or fourth conversion unit; The third conversion unit converts the first Ethernet data into the first PCIE data and sends the first PCIE data to the first NPU based on the third PCIE bus; The first NPU processes the first PCIe data; The fourth conversion unit converts the first Ethernet data into the first PCIE data and sends the first PCIE data to the second NPU based on the fourth PCIE bus. The second NPU processes the first PCIe data.

8. The method according to claim 7, characterized in that, The method further includes: Determine the total data bandwidth of the Ethernet switching chip; Based on the total data bandwidth, allocate data bandwidth to the third virtual LAN and the fourth virtual LAN; The third virtual local area network (VLAN) is a VLAN between the second CPU, the first NPU, the second conversion unit, the third conversion unit, and the Ethernet switching chip; the fourth VLAN is a VLAN between the second CPU, the second NPU, the second conversion unit, the fourth conversion unit, and the Ethernet switching chip.

9. The method according to claim 7, characterized in that, The method further includes: In the event of a failure in the first CPU, the logic detection unit generates a second fault signal; The logic detection unit sends the second fault signal to the microcontroller unit; The microcontroller sends a second switching command to the Ethernet switching chip based on the second fault signal, so that the Ethernet switching chip forwards the first Ethernet data to the third conversion unit or the fourth conversion unit.

10. The method according to claim 7, characterized in that, The method further includes: In the event of a failure in the first CPU or the second CPU, the logic detection unit generates a third fault signal; The logic detection unit sends the third fault signal to the microcontroller unit; The microcontroller sends a restart command to the Ethernet switching chip based on the third fault signal, so that the Ethernet switching chip can be restarted. The microcontroller sends control commands to external devices connected to the data transmission system based on the third fault signal, so as to change the working state of the external devices.

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