A driving method for high-speed data transmission based on multiple PCIE cards

Abstract

The application discloses a driving method for high-speed data transmission based on a multi-PCIE card, and the driving hierarchy comprises an upper application layer and a PCIE driving layer; the PCIE driving layer comprises two parts of a PCIE driver and a character device driver; wherein the PCIE driver identifies the PCIE card and initializes PCIE resources; and the character device driver identifies the PCIE card as a standard character device and accesses the PCIE card through the standard character device. By adopting the technical scheme, the demand for large-scale physical continuous memory of a machine is greatly reduced; the DMA transmission performance is improved; the lock-free concurrent access of a buffer area is realized; the quantum random number output performance of the upper application layer is improved; in the use scene of 'one machine with multiple cards', the upper application layer is simple and easy to use, and can well cope with complex situations such as a large number of user accesses, a large amount of data transmission of the PCIE card by the user, real-time changes of data demand of multiple users and the like.

Description

Technical Field

[0001] This invention belongs to the technical field of high-speed data transmission in quantum communication, and particularly relates to a driving method for high-speed data transmission based on multiple PCIe cards. Background Technology

[0002] With the development of electronic technology and the growth of user demand, the functions of PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) cards are becoming more and more diversified. Some PCIe cards only need to implement the high-speed data reception function of PCIe, such as high-speed quantum random number generator (QRNG).

[0003] Existing general PCIe driver methods use a contiguous block of physical memory for DMA (Direct Memory Access) transfer caching on such devices;

[0004] When the upper application layer needs to read data, the driver layer will allocate a contiguous physical memory for DMA transfer cache based on the size of the data to be read by the upper application layer.

[0005] During concurrent access, a strategy of locking the PCIe card is used to control concurrent access;

[0006] In the "one machine, multiple cards" usage scenario, the driver layer does not consider the PCIe multi-card scheduling strategy, which is generally left to the upper application layer to solve.

[0007] However, the application of existing general PCIe driver methods to such devices has the following limitations:

[0008] 1. When large-scale data transfer is required, extremely large physical contiguous memory allocations can increase the memory management pressure on the operating system and may even lead to memory allocation failures.

[0009] 2. When the application layer retrieves a small amount of data each time, it will severely degrade DMA transfer performance, resulting in a significant decrease in the overall data output performance of the PCIe card;

[0010] 3. In scenarios with large-scale concurrent access, the locking control concurrency strategy for PCIe cards may become a bottleneck for PCIe card data transmission, reducing the performance of application layer data output.

[0011] 4. In the "one machine, multiple cards" usage scenario, there may be complex situations such as a large number of users accessing the network, a large amount of data transmission between users and the PCIe card, and real-time changes in the demand from multiple users; these scenarios require the application layer to monitor the usage of the PCIe card, which complicates the user experience. Summary of the Invention

[0012] This invention provides a driver method for high-speed data transmission based on multiple PCIe cards, the purpose of which is to reduce the need for large-scale physical contiguous memory in the system and improve DMA transfer performance.

[0013] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0014] The present invention provides a high-speed data transmission driver method based on multiple PCIe cards, the driver hierarchy of which includes an upper application layer and a PCIe driver layer; the PCIe driver layer includes two parts: a PCIe driver and a character device driver; wherein: the PCIe driver identifies the PCIe card and initializes PCIe resources; the character device driver identifies the PCIe card as a standard character device and accesses the PCIe card through the standard character device.

[0015] The driver method is based on the Linux system. During the initialization process, a DMA cache pool is requested for each PCIe card, and all DMA cache pools are added to the free list. The cache pool consists of multiple cache areas, and each buffer is a contiguous physical memory.

[0016] The DMA cache pool is managed using three linked lists: a free list, a valid list, and a transfer list. The free list manages empty buffers; the valid list manages buffers containing valid data; and the transfer list manages buffers currently being transferred via DMA.

[0017] After the PCIe driver is loaded, the device is automatically identified and the device driver software is initialized based on the PID and VID of the quantum random number generator; the initialization process is as follows:

[0018] a) Initialize PCIe resources. The system will allocate independent resources to each PCIe card. The PCIe resources include interrupts, I / O, and locks.

[0019] b) Initialize DMA buffer pool resources, request N DMA buffer pools, each with a size of M; set the effective data length of each buffer to 0, and add all DMA buffer pools to the free list;

[0020] c) Initialize the scheduling policy resource, which is used to record the total number of PCIe cards, the DMA cache pool queue count, the PCIe card operating status, and the total number of quantum random number outputs. waitThe above information for each PCIe card will be recorded in the scheduling resource area;

[0021] d) Initialize the character device driver and PCIe driver software. Will also Initialize the PCIe card as a character device, upper application layer Can Access the PCIe card via the standard character driver interface;

[0022] e) Then, enable the PCIe device to complete the initialization process.

[0023] The management methods for the free linked list, valid linked list, and transfer linked list are as follows:

[0024] a) After initialization, the DMA cache pool will set the effective data length of all DMA cache areas to 0, put all DMA buffers into the free list, and start the DMA transfer task.

[0025] b) The DMA transfer task will move the buffer in the free list to the transfer list and start the DMA transfer.

[0026] c) When the upper application layer initiates a quantum random number acquisition operation, it will obtain a buffer from the buffer pool of the valid linked list and copy the valid data in the buffer to the memory space of the upper application layer.

[0027] d) After the copy operation is complete, if the remaining valid data in the buffer is 0, add it to the free list; if the number of items in the free list is greater than the threshold, restart the DMA transfer task. If the remaining valid data in the buffer is greater than 0, add it to the valid list.

[0028] When a DMA transfer task is started, the buffer of the free list is moved to the transfer list to complete the DMA transfer from the PCIe card to the transfer list buffer pool.

[0029] If the transfer completes normally, the effective data length of the DMA buffer is set to M; M is the size of the DMA buffer, and the buffer pool on the transfer list is moved to the effective list.

[0030] If a transmission error occurs, the effective data length of the DMA buffer is set to 0, and the buffer pool on the transmission list is moved to the free list.

[0031] The specific procedures for handling DMA transfer tasks that complete normally or encounter transfer errors are as follows:

[0032] a) Lock the linked list, move all free linked list buffers to the transfer linked list, and then unlock the linked list;

[0033] b) Issue the command to obtain quantum random numbers, start the DMA transfer task, and wait for the DMA transfer to end signal;

[0034] c) If no DMA transfer signal is received within 500ms, proceed to step d); if a DMA transfer completion signal is received, update the effective data length of all transfer list buffers to M, and proceed to step e).

[0035] d) Lock the linked list, move all transfer linked list buffers to the free linked list, unlock the linked list, the device status error is reported, and the DMA transfer task ends.

[0036] e) Lock the linked list, move all transfer linked list buffers to the valid linked list, unlock the linked list, and wake up the processes waiting to access the valid linked list. The DMA transfer task ends.

[0037] The upper application layer initiates the operation of obtaining K quantum random numbers. First, a fair scheduling strategy is adopted to select the most idle quantum random number generator. The operation process of the fair scheduling strategy is as follows:

[0038] a) View the status information of all quantum random number generators and count all quantum random number generators in normal state;

[0039] b) Count the idle device among all normal quantum random number generators; the idle device is the device with the fewest queued accesses in the effective linked list buffer pool corresponding to the quantum random number generator.

[0040] c) Count the device with the smallest total output data among all the most idle quantum random number generators.

[0041] After selecting the most idle quantum random number generator, K quantum random numbers are taken from the buffer pool corresponding to that quantum random number generator. The operation process is as follows:

[0042] a) If K == 0, complete the operation and end; if K > 0, proceed to step b).

[0043] b) Lock the linked list, obtain a buffer B from the valid linked list buffer pool, and then unlock the linked list;

[0044] c) Detect the remaining size L of buffer B;

[0045] If K < L, copy K bytes to user space, L = L - K; if K = 0, proceed to step d).

[0046] If K≥L, copy L bytes to user space, K=K-L, L=0, proceed to step e);

[0047] d) Lock the linked list, add buffer B to the valid linked list buffer pool, unlock the linked list, and jump to step a).

[0048] e) Lock the linked list, add buffer B to the free linked list buffer pool, and unlock the linked list; if the number of free linked list buffers is greater than the threshold M1, start the DMA transfer task and jump to step a).

[0049] This invention adopts the above-mentioned technical solution and proposes an innovative PCIe driver scheme for the practical application scenarios of quantum random number generators, solving the problems existing in the prior art. When applying for a DMA cache pool, it is only necessary to ensure that the physical addresses of each DMA cache are contiguous, which greatly reduces the demand for large-scale physical contiguous memory on the machine. When the free list exceeds a threshold, a DMA transfer task will be started. Selecting an appropriate threshold can effectively control the data size during each DMA transfer and reduce the number of times the DMA transfer task is started, thereby improving DMA transfer performance. In the PCIe driver, a DMA cache pool is added for each quantum random number generator, and each DMA cache pool is managed using three linked lists to enable users to read DMA cache. The system enables concurrent access to the DMA cache pool from the quantum random number generator by the pool and the driver. When there is a large number of concurrent accesses at the upper application layer, each access retrieves a buffer from the valid linked list, enabling lock-free concurrent access to the buffer. This improves the performance of quantum random number output at the upper application layer. In the "one machine, multiple cards" usage scenario, when users concurrently read quantum random numbers, the driver layer adopts a fair scheduling strategy based on the quantum random number generator device status and the waiting access status of the DMA cache pool to reasonably arrange users to access the more idle quantum random number generator device. The upper application layer access is simple and easy to use, and can well cope with complex situations such as a large number of users accessing the network, large data transfer volume of users to PCIe cards, and real-time changes in data demand from multiple users. Attached Figure Description

[0050] The following is a brief description of the content shown in the attached diagram:

[0051] Figure 1 This is a schematic diagram of the PCIE driver hierarchy of the present invention;

[0052] Figure 2 This is a flowchart of the PCIE driver initialization process of the present invention;

[0053] Figure 3 This is a state diagram of the PCIE driver DMA cache pool of the present invention;

[0054] Figure 4 This is a diagram of the PCIE-driven quantum random number DMA transfer task of the present invention;

[0055] Figure 5This is a diagram illustrating the PCIe driver multi-device fair scheduling strategy of the present invention.

[0056] Figure 6 This is a flowchart of the application layer quantum random number acquisition process for the PCIE driver according to the present invention. Detailed Implementation

[0057] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, so as to help those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention.

[0058] like Figure 1 The structure shown in this invention is a driving method for high-speed data transmission based on multiple PCIe cards, and its driving layers include an upper application layer and a PCIe driver layer.

[0059] 1. In order to solve the problems and overcome the defects of the existing technology, and to achieve the invention objective of reducing the demand for large-scale physical contiguous memory of the system and improving DMA transfer performance, the technical solution adopted by the present invention is as follows:

[0060] like Figure 1 As shown, the driver method for high-speed data transmission based on multiple PCIe cards of the present invention includes a PCIe driver layer comprising two parts: a PCIe driver and a character device driver. Specifically, the PCIe driver identifies the PCIe card and initializes PCIe resources; the character device driver identifies the PCIe card as a standard character device and accesses the PCIe card through the standard character device.

[0061] For practical applications of quantum random number generators (QRNGs), this invention proposes the aforementioned high-speed data transmission scheme based on multiple PCIe cards. It employs DMA cache pool technology and adds a driver-level scheduling scheme, thus overcoming the limitations of existing technologies. The achieved technical effects are:

[0062] For practical applications of quantum random number generators, an innovative PCIE driver solution is proposed, which solves the problems and defects of existing technologies.

[0063] This invention is based on the Linux system and adopts a character device driver architecture, which recognizes all quantum random number generators as character devices. The upper application layer accesses the quantum random number generator based on the standard character device driver interface.

[0064] When applying for a DMA cache pool, it is only necessary to ensure that the physical addresses of each DMA cache are contiguous, which greatly reduces the need for large-scale physical contiguous memory on the machine.

[0065] When the free list is larger than the threshold, a DMA transfer task will be started. Selecting an appropriate threshold can effectively control the data size during each DMA transfer and reduce the number of times the DMA transfer task is started, thereby improving DMA transfer performance.

[0066] In the PCIe driver, a DMA cache pool is added for each quantum random number generator. Each DMA cache pool is managed using three linked lists, enabling concurrent access for users to read from the DMA cache pool and for the driver to read data from the quantum random number generator into the DMA cache pool. When there is a large number of concurrent accesses in the upper application layer, each access obtains a buffer from the valid linked list, which can realize lock-free concurrent access to the buffer, thereby improving the performance of quantum random number output in the upper application layer.

[0067] In the "one machine, multiple cards" usage scenario, when users concurrently read quantum random numbers, the driver layer adopts a fair scheduling strategy based on the quantum random number generator device status and the waiting access status of the DMA cache pool. This strategy rationally arranges for users to access more idle quantum random number generator devices. The upper application layer is simple and easy to use, and can effectively cope with complex scenarios such as a large number of users accessing the network, large data transfer volumes from users to PCIe cards, and real-time changes in data demand from multiple users.

[0068] like Figure 1 As shown:

[0069] The driver method is based on the Linux system. During the initialization process, a DMA cache pool is requested for each PCIe card, and all DMA cache pools are added to the free list. The cache pool consists of multiple cache areas, and each buffer is a contiguous physical memory.

[0070] This driver is the link between upper-layer application software and the underlying hardware platform, such as... Figure 1 As shown, the PCIe driver consists of two parts: the PCIe driver and the character device driver. The PCIe driver identifies the PCIe card and initializes PCIe resources; the character device driver recognizes the PCIe card as a standard character device and accesses the PCIe card through the standard character device.

[0071] like Figure 3 As shown:

[0072] The DMA cache pool is managed using three linked lists: a free list, a valid list, and a transfer list. The free list manages empty buffers; the valid list manages buffers containing valid data; and the transfer list manages buffers currently being transferred via DMA.

[0073] 2. After the PCIe driver is loaded, the device is automatically identified and the device driver software is initialized based on the PID and VID of the quantum random number generator; for example... Figure 2As shown, the initialization process is as follows:

[0074] a) Initialize PCIe resources. The system will allocate independent resources to each PCIe card. The PCIe resources include interrupt, I / O, lock, and other resources.

[0075] b) Initialize DMA buffer pool resources, request N DMA buffer pools, each with a size of M; set the effective data length of each buffer to 0, and add all DMA buffer pools to the free list;

[0076] c) Initialize the scheduling policy resource, which is used to record the total number of PCIe cards, the DMA cache pool queue count, the PCIe card operating status, and the total number of quantum random number outputs. wait The above information for each PCIe card will be recorded in the scheduling resource area;

[0077] d) Initialize the character device driver. The PCIe driver software initializes the PCIe card as a character device, and the upper application layer accesses the PCIe card through the standard character driver interface.

[0078] e) Then, enable the PCIe device to complete the initialization process.

[0079] 3. DMA cache pool state transitions, such as... Figure 3 As shown, the DMA cache pool is managed using three linked lists; the management method for the free linked list, valid linked list, and transfer linked list is as follows:

[0080] a) After initialization, the DMA cache pool will set the effective data length of all DMA cache areas to 0, put all DMA buffers into the free list, and start the DMA transfer task.

[0081] b) The DMA transfer task will move the buffer in the free list to the transfer list and start the DMA transfer.

[0082] c) When the upper application layer initiates a quantum random number acquisition operation, it will obtain a buffer from the buffer pool of the valid linked list and copy the valid data in the buffer to the memory space of the upper application layer.

[0083] d) After the copy operation is completed, if the remaining size of the valid data in the buffer is 0, add it to the free list; if the number of free lists is greater than the threshold, restart the DMA transfer task; if the remaining size of the valid data in the buffer is greater than 0, add it to the valid list.

[0084] When the DMA transfer task is started, the buffer of the free list will be moved to the transfer list to complete the DMA transfer of quantum random numbers from the PCIe card to the transfer list buffer pool.

[0085] If the transfer completes normally, the effective data length of the DMA buffer is set to M; M is the size of the DMA buffer, and the buffer pool on the transfer list is moved to the effective list.

[0086] If a transmission error occurs, the effective data length of the DMA buffer is set to 0, and the buffer pool on the transmission list is moved to the free list.

[0087] 4. After initiating the DMA transfer task, the DMA transfer of quantum random numbers from the PCIe card to the free buffer pool will be completed, such as... Figure 4 As shown; the specific operation procedures for the normal completion and abnormal completion of the DMA transfer task are as follows:

[0088] a) Lock the linked list, move all free linked list buffers to the transfer linked list, and then unlock the linked list;

[0089] b) Issue the command to obtain quantum random numbers, start the DMA transfer task, and wait for the DMA transfer to end signal;

[0090] c) If no DMA transfer signal is received within 500ms, proceed to step d); if a DMA transfer completion signal is received, update the effective data length of all transfer list buffers to M, and proceed to step e).

[0091] d) Lock the linked list, move all transfer linked list buffers to the free linked list, unlock the linked list, the device status error is reported, and the DMA transfer task ends.

[0092] e) Lock the linked list, move all transfer linked list buffers to the valid linked list, unlock the linked list, and wake up the processes waiting to access the valid linked list. The DMA transfer task ends.

[0093] 5. The upper application layer initiates the operation to obtain K quantum random numbers. First, a fair scheduling strategy is adopted to select the most idle quantum random number generator. The fair scheduling strategy is as follows: Figure 5 As shown; its operation process is as follows:

[0094] a) View the status information of all quantum random number generators and count all quantum random number generators in normal state;

[0095] b) Count the idle device among all normal quantum random number generators; the idle device is the device with the fewest queued accesses in the effective linked list buffer pool corresponding to the quantum random number generator.

[0096] c) Count the device with the smallest total output data among all the most idle quantum random number generators.

[0097] 6. After selecting the most idle quantum random number generator, K quantum random numbers are taken from the buffer pool corresponding to that quantum random number generator, such as... Figure 6 As shown, the operation process is as follows:

[0098] a) If K≡0, complete the operation and end; if K>0, proceed to step b).

[0099] b) Lock the linked list, obtain a buffer B from the valid linked list buffer pool, and then unlock the linked list;

[0100] c) Detect the remaining size L of buffer B;

[0101] If K < L, copy K bytes to user space, K = 0, L = L - K, and proceed to step d).

[0102] If K≥L, copy L bytes to user space, K=K-L, L=0, proceed to step e);

[0103] d) Lock the linked list, add buffer B to the valid linked list buffer pool, unlock the linked list, and jump to step a).

[0104] e) Lock the linked list, add buffer B to the free linked list buffer pool, and unlock the linked list; if the number of free linked list buffers is greater than the threshold M1, start the DMA transfer task and jump to step a).

[0105] (e) Lock the linked list, add buffer B to the free linked list buffer pool, unlock the linked list, and if the number of free linked list buffers is greater than the threshold M1, start the DMA transfer task; return to step a).

[0106] The present invention has been described above by way of example with reference to the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvements made using the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other occasions without modification, are all within the protection scope of the present invention.

Claims

1. A driver method for high-speed data transmission based on multiple PCIe cards, wherein the driver layer includes an upper application layer and a PCIe driver layer; characterized in that The aforementioned driver method is based on the Linux system; The PCIE driver layer comprises two parts: the PCIE driver and the character device driver; wherein, the PCIE driver identifies the PCIE card and initializes PCIE resources; The character device driver recognizes the PCIe card as a standard character device and accesses the PCIe card through the standard character device. During initialization, a DMA cache pool is requested for each PCIe card, and all DMA cache pools are added to the free list; the cache pool consists of multiple buffers, each of which is contiguous physical memory.

2. The driving method of high-speed data transmission based on multi-PCIE card according to claim 1, characterized in that: The DMA cache pool is managed using three linked lists: a free list, a valid list, and a transfer list. The free list manages empty buffers; the valid list manages buffers containing valid data; and the transfer list manages buffers currently being transferred via DMA.

3. The driving method for high-speed data transmission based on multiple PCIe cards according to claim 1, characterized in that: After the PCIe driver is loaded, the device is automatically identified and the device driver software is initialized based on the PID and VID of the quantum random number generator; the initialization process is as follows: a) Initialize PCIe resources. The system allocates independent resources to each PCIe card. The PCIe resources include interrupts, I / O, and locks. b) Initialize DMA cache pool resources, request N DMA cache pools, each with a buffer size of M; set the effective data length of each buffer to 0, and add all DMA cache pools to the free list; c) Initialize the scheduling policy resource, which is used to record the total number of PCIe cards, the DMA cache pool queue count, the PCIe card running status, and the total number of quantum random number outputs. The above information for each PCIe card will be recorded in the scheduling resource area. d) Initialize the character device driver. The PCIE driver software initializes the PCIE card as a character device, and the upper application layer accesses the PCIE card through the standard character driver interface. e) Then, enable the PCIe device to complete the initialization process.

4. The driving method for high-speed data transmission based on multiple PCIe cards according to claim 2, characterized in that: The management methods for the free linked list, valid linked list, and transfer linked list are as follows: a) After the DMA buffer pool is initialized, the effective data length of all DMA buffers is set to 0, all DMA buffers are put into the free list, and the DMA transfer task is started at the same time. b) The DMA transfer task moves the buffer in the free list to the transfer list and starts the DMA transfer. c) The upper application layer initiates a quantum random number acquisition operation, obtains a buffer from the cache pool of the valid linked list, and copies the valid data in the buffer to the memory space of the upper application layer; d) After the copy operation is completed, if the remaining size of the valid data in the buffer is 0, add it to the free list; if the number of free lists is greater than the threshold, restart the DMA transfer task; if the remaining size of the valid data in the buffer is greater than 0, add it to the valid list.

5. The driving method for high-speed data transmission based on multiple PCIe cards according to claim 4, characterized in that: Once the DMA transfer task is started, the buffer in the free list is moved to the transfer list to complete the DMA transfer from the PCIe card to the transfer list buffer. If the transfer completes normally, set the effective data length of the DMA buffer to M; M is the size of the DMA buffer, and the buffer pool on the transfer list is moved to the valid list; If a transmission error occurs, the effective data length of the DMA buffer is set to 0, and the buffer pool on the transmission list is moved to the free list.

6. The driving method for high-speed data transmission based on multiple PCIe cards according to claim 4, characterized in that: The specific procedures for handling DMA transfer tasks that complete normally or encounter transfer errors are as follows: a) Lock the linked list, move all free linked list buffers to the transfer linked list, and then unlock the linked list; b) Issue the command to obtain quantum random numbers, start the DMA transfer task, and wait for the DMA transfer to end signal; c) If no DMA transfer signal is received within 500ms, proceed to step d); If a DMA transfer completion signal is received, update the effective data length of all transfer list buffers to M, and proceed to step e). d) Lock the linked list, move all transfer linked list buffers to the free linked list, unlock the linked list, the device status error is reported, and the DMA transfer task ends; e) Lock the linked list, move all transfer linked list buffers to the valid linked list, unlock the linked list, and wake up the processes waiting to access the valid linked list. The DMA transfer task ends.

7. The driving method for high-speed data transmission based on multiple PCIe cards according to claim 1, characterized in that: The upper application layer initiates the operation of obtaining K quantum random numbers. First, a fair scheduling strategy is adopted to select the most idle quantum random number generator. The operation process of the fair scheduling strategy is as follows: a) View the status information of all quantum random number generators and count all quantum random number generators in normal state; b) Count the idle device among all normal quantum random number generators; the idle device is the one with the fewest queued accesses in the valid linked list buffer corresponding to the quantum random number generator. c) Count the device with the smallest total output data among all the most idle quantum random number generators.

8. The driving method for high-speed data transmission based on multiple PCIe cards according to claim 7, characterized in that: After selecting the most idle quantum random number generator, K quantum random numbers are taken from the buffer corresponding to that quantum random number generator. The operation process is as follows: a) If K == 0, complete the operation and end; if K > 0, proceed to step b). b) Lock the linked list, obtain a buffer B from the valid linked list buffer, and then unlock the linked list; c) Detect the remaining size L of buffer B; If K < L, copy K bytes to user space, L = L - K; if K = 0, proceed to step d). If K ≥ L, copy L bytes to user space, K = K - L, L = 0; proceed to step e). d) Lock the linked list, add buffer B to the valid linked list cache pool, unlock the linked list, and jump to step a). e) Lock the linked list, add buffer B to the free linked list buffer pool, and unlock the linked list; if the number of free linked list buffers is greater than the threshold M1, start the DMA transfer task and jump to step a).

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