Cosine number transform based image encryption hardware accelerator

Abstract

The application discloses an image encryption hardware accelerator based on cosine number transformation, which is composed of a modulo module, a CNT transformation module, a selection module and a transposition module, and is characterized in that: firstly, an image input from outside is divided into blocks, then j times of CNT row transformation is performed on the image blocks, and the results of the j times of operation are simultaneously output to the selection module through a shift register, a certain result is selected as a 1D-CNT image block coefficient according to a first key, and then the 1D-CNT image block coefficient is transposed; then, the transposed 1D-CNT image block coefficient is subjected to a row transformation process again to obtain a result of j times of CNT column transformation, and a certain result is selected as a 2D-CNT image block coefficient according to a second key, so that the overall image is encrypted. The application aims at optimizing resource consumption and cycle number of the algorithm, thereby improving the speed of the digital image hardware encryption circuit, and improving the security of the encrypted image under the premise of ensuring the realization of the encryption function.

Description

Technical Field

[0001] This invention belongs to the field of image encryption technology of integrated circuits, and more specifically, it is an image encryption hardware accelerator based on cosine transform. Background Technology

[0002] In fields such as commerce, medicine, military, and even personal life, digital images represent a multimedia technology containing confidential information. However, when using public or shared digital networks for data storage and processing, digital images are vulnerable to destructive attacks, such as replay attacks, human-based attacks, brute-force attacks, and statistical attacks. Simultaneously, with the advent of the 5G era, the amount of data generated per capita and the demand for processing data in the cloud are surging, placing increasingly higher demands on the speed of digital image processing. Therefore, designing an efficient cryptographic system to protect confidential images during storage and movement is a challenge.

[0003] Currently, most image encryption schemes run in software, and software attacks on computers are highly complex and difficult to detect. In contrast, hardware circuits offer greater flexibility, stronger processing power, and superior security. Hardware implementations can also provide higher performance and security by running algorithms. Therefore, using hardware implementations is the best solution for building strong cryptographic systems.

[0004] While some hardware-based image encryption schemes exist, they still have limitations:

[0005] In 2019, Ravi et al. proposed a hybrid algorithm image encryption scheme that offered good security, but its processing time was 216 ms and its throughput was 4.85 Mbps. In 2021, Lata et al. proposed an image encryption algorithm based on chaos theory and implemented it on an FPGA. The designed image encryption hardware had strong robustness, but its encryption time was 21.14 ms. In 2022, Siva et al. proposed a fractal-based chaotic image encryption scheme and implemented it on an FPGA. This scheme required 12.13 ms to encrypt an image and achieved a throughput of 86.44 Mbps, offering faster processing speed. However, the above schemes still could not meet the requirements for real-time image encryption. For these reasons, it is necessary to design a high-speed image encryption hardware scheme. Summary of the Invention

[0006] To address the shortcomings of the existing technology, this invention proposes an image encryption hardware accelerator based on cosine transform, aiming to optimize the resource consumption and cycle number of the algorithm, thereby improving the speed of digital image encryption circuits and enhancing the security of encrypted images while ensuring the encryption function is implemented.

[0007] The technical solution adopted by the present invention to achieve the above objectives is as follows:

[0008] The present invention provides an image encryption hardware accelerator based on cosine transform, which includes: a modulus extraction module, a CNT transform module, a selection module, and a transpose module; wherein the transpose module includes a first RAM and a second RAM.

[0009] The CNT transformation module receives an externally input image of size k×k pixels and performs block processing to obtain several image blocks of size 8×8 pixels. For each image block, j CNT row transformations and several modulo operations are performed on 8 pixels x0 to x7 to obtain j sets of 1D-CNT coefficients after modulo operation.

[0010] The modulus-taking module divides each data point in the t-bit-width intermediate data of the CNT transformation module into low t / 2 bits and high t / 2 bits. It then multiplies the high t / 2 bits by -1 and adds them to the low t / 2 bits to obtain the modulus result for each data point, which is returned to the CNT transformation module. If the modulus result is negative, the modulus q is added to the negative modulus result to obtain the final modulus result. The intermediate data includes: preprocessed data a0~a3, preliminary CNT row transformation results y0~y7, and a set of 1D-CNT coefficients C0~C7. The modulus result includes: preprocessed data a′0~a′3 after modulus taking, preliminary CNT row transformation results y′0~y′7 after modulus taking, and a set of 1D-CNT coefficients C′0~C′7 after modulus taking.

[0011] The selection module simultaneously receives j sets of 1D-CNT coefficients after modulo operation through j-1 shift registers, and selects a set of 1D-CNT coefficients after modulo operation as a row of data I0 to I7 of 1D-CNT image block coefficient I according to the first key received from the outside. Thus, after 8 operations on each image block, the 1D-CNT image block coefficient I of 8×8 pixels corresponding to each image block is obtained.

[0012] After receiving the 1D-CNT image block coefficient I, the transpose module uses the first RAM to convert the 1D-CNT image block coefficient I into the 1D-CNT image block transpose coefficient I in a row-write and column-read manner. T When reading data in the first RAM by column, the 1D-CNT image block coefficients of the next image block are written to the second RAM by row. When reading data in the second RAM by column, the 1D-CNT image block coefficients of the next image block are written to the first RAM by row, thereby realizing the alternating reading and writing of the first RAM and the second RAM until the transpose of the 1D-CNT image block coefficients of all image blocks is completed.

[0013] The CNT transformation module receives the transpose coefficient I of an 8×8 pixel 1D-CNT image block. T and to I T A row of data i0 to i7 undergoes j CNT column transformations and several modulo operations to obtain j sets of 2D-CNT coefficients after modulo operations;

[0014] The modulus extraction module extracts a portion of the intermediate data from the CNT transformation module and returns it to the CNT transformation module.

[0015] The selection module simultaneously receives j sets of modulo-digested 2D-CNT coefficients through j-1 shift registers, and selects one set of modulo-digested 2D-CNT coefficients as a row of data M0 to M7 of the 2D-CNT image block coefficients M, thereby controlling I. T After eight calculations, the coefficients M of the 8×8 pixel 2D-CNT image block are obtained to encrypt the k×k pixel image.

[0016] The present invention discloses a hardware acceleration method for image encryption based on cosine transform, characterized in that it is applied to an accelerator composed of a modulus extraction module, a CNT transform module, a selection module, and a transpose module. The CNT transform module includes a hybrid addition / subtraction module, an even coefficient generation module, and an odd coefficient generation module. The transpose module includes a first RAM and a second RAM with a depth of 8×8. The image encryption hardware acceleration method is performed according to the following steps:

[0017] Step 1: The CNT transformation module acquires an image of size k×k pixels and performs block processing to obtain several image blocks of size 8×8 pixels. Any one of these image blocks is denoted as A.

[0018] Step 2: The CNT transformation module sends the 8 pixels x0 to x7 in image block A to its own hybrid addition and subtraction operation module. The hybrid addition and subtraction operation module performs addition or subtraction operations on x0 to x7 respectively according to the external enable signal en to obtain preprocessed data a0 to a3.

[0019] If en is high, then add operations are performed on x0 to x7;

[0020] If en is low, then subtraction is performed on x0 to x7;

[0021] Step 3: The modulo module divides the preprocessed data a0 to a3, each with a bit width of t, into low t / 2 bits and high t / 2 bits respectively. The high t / 2 bits are multiplied by negative one and then added to the low t / 2 bits to obtain the modulo result a′0 to a′3 for each data. If the modulo result is negative, the modulo result of the negative number is added to the modulus q to obtain the final modulo result.

[0022] Step 4: If en is high, the modulo result a′0~a′3 of the preprocessed data is sent to the even coefficient generation module. The first adder in the even coefficient generation module performs addition operation on a′0~a′3 and outputs two coefficients b0, b1. At the same time, the four shift addition and subtraction modules SAU1, SAU2, SAU3, and SAU4 in the even coefficient generation module perform shift and addition and subtraction operations on a′0~a′3 respectively, and obtain two coefficients output by each shift addition and subtraction module.

[0023] Step 5: If en is low, then a′0~a′3 is sent to the odd coefficient generation module. The four shift addition and subtraction modules SAU5, SAU6, SAU7, and SAU8 perform shift and addition / subtraction operations on a′0~a′3 respectively, and obtain the four coefficients output by each shift addition and subtraction module.

[0024] Step 6: The second adder in the even coefficient generation module receives two coefficients b0 and b1 and performs an addition operation to obtain the 0th term y0 of the preliminary CNT row transformation result;

[0025] Step 7: The two coefficients b0 and b1 are multiplied by different numbers and then sent to the third adder in the even coefficient generation module for addition to obtain the fourth term y4 of the preliminary CNT row transformation result;

[0026] Step 8: The fourth adder in the even coefficient generation module receives a coefficient output from the shift addition and subtraction modules SAU1 and SAU4 respectively and performs an addition operation to obtain an intermediate addition value c. 00 ;

[0027] The fifth adder in the even coefficient generation module receives a coefficient output by shift addition and subtraction modules SAU2 and SAU3 respectively and performs an addition operation to obtain an intermediate addition value c. 10 ;

[0028] Step 9: Reuse the fourth and fifth adders in the even coefficient generation module described five times to receive the coefficients output by the eight shift addition and subtraction modules SAU and perform addition operations to obtain 10 intermediate addition values ​​c. 01 ,c 11 ,c 02 ,c 12 ,c03 ,c 13 ,c 04 ,c 14 ,c 05 ,c 15 ;

[0029] Step 10: The sixth adder in the even coefficient generation module receives two intermediate addition values ​​c respectively. 00 ,c 10 Then perform an addition operation to obtain the second term y2 of the preliminary CNT row transformation result;

[0030] The seventh adder in the even coefficient generation module and the eighth to eleventh adders in the odd coefficient generation module each receive two intermediate addition values ​​and perform addition operations, thereby obtaining the remaining terms y6, y1, y3, y5, y7 of the preliminary CNT row transformation result, where y6 = c 01 +c 11 y1=c 02 +c 12 y3=c 03 +c 13 y5=c 04 +c 14 y7 = c 05 +c 15 ;

[0031] Step 11: The modulus extraction module performs modulus extraction on the preliminary CNT row transformation results y0~y7 to obtain the modulo-extracted preliminary CNT row transformation results y′0~y′7;

[0032] Step 12: Multiply the initial 1D-CNT row transformation results y′0~y′7 after modulo by the corresponding normalization factors β0~β7 respectively to obtain a set of 1D-CNT coefficients C0~C7;

[0033] Step 13: The modulus extraction module extracts the modulus of a set of 1D-CNT coefficients C0 to C7 to obtain a set of 1D-CNT coefficients C′0 to C′7 after the modulus extraction.

[0034] Step 14: The selection module receives j sets of 1D-CNT coefficients after modulo operation through j-1 shift registers simultaneously, and selects a set of 1D-CNT coefficients after modulo operation as a row of data I0 to I7 of 1D-CNT image block coefficient I according to the first key received from the outside. Thus, after 8 operations on image block A, the 8×8 pixel 1D-CNT image block coefficient I is obtained.

[0035] Step 15: The transpose module writes a row of data I0 to I7 from the 1D-CNT image block coefficients I into the first RAM row by row until all 8 rows are written; then, it reads a column of data i0 to i7 from the first RAM column by column until all 8 columns are read, thereby obtaining the 8×8 1D-CNT image block transpose coefficients I. T Simultaneously, write one row of data J0 to J7 from the coefficient J of the 1D-CNT image block corresponding to the next image block B into the second RAM row by row until all 8 rows have been written.

[0036] Then, a column of data j0 to j7 in the second RAM is read out column by column until all 8 columns are read; at the same time, a row of data in the 1D-CNT image block coefficients corresponding to the next image block C is written into the first RAM row by row until all 8 rows are written, thereby realizing the alternating reading and writing of the first RAM and the second RAM until the transpose of the 1D-CNT image block coefficients of all image blocks is completed.

[0037] Step 16: The CNT transformation module receives the transpose coefficient I of an 8×8 pixel 1D-CNT image block. T and to I T A row of data i0 to i7 undergoes j CNT column transformations and several modulo operations to obtain j sets of 2D-CNT coefficients after modulo operations;

[0038] Step 17: The modulus extraction module performs modulus extraction on a portion of the intermediate data in the CNT transformation module and returns it to the CNT transformation module;

[0039] Step 18: The selection module simultaneously receives j sets of modulo-digested 2D-CNT coefficients through j-1 shift registers, and selects a set of modulo-digested 2D-CNT coefficients as a row of data M0 to M7 of the 2D-CNT image block coefficients M, thereby adjusting the 1D-CNT image block transpose coefficients I. T After eight calculations, the coefficients M of the 2D-CNT image block of 8×8 pixels are obtained, which can be used to encrypt the image of k×k pixels.

[0040] Compared with the prior art, the beneficial technical effects of the present invention are reflected in:

[0041] 1. In designing and implementing a digital image encryption circuit, this invention proposes a constant multiplication system based on a multiplier-free CNT architecture with a computation length of 8. This architecture consists of a circuit for separating parity coefficients and a shift addition / subtraction module (SAU). Based on the separable computational characteristics of CNT parity coefficients, parity coefficient operation circuits are built using the characteristics of their respective coefficients. When calculating coefficients, multiple multipliers are required. To save resources, eight SAU modules are used instead of multipliers, thereby saving resource consumption.

[0042] 2. This invention utilizes the central symmetry of CNT even coefficients. When calculating coefficients, the input data is first summed end-to-end before being sent to the SAU module for calculation. Compared to directly calculating even coefficients, this method saves half the resources when calculating even coefficients with central symmetry. However, CNT odd coefficients exhibit correlation, requiring the value of the previous odd coefficient to calculate the next, making full parallelism impossible. This invention combines even coefficient operations with time-division multiplexing technology. After data is output from the SAU module, the adder is multiplexed to complete the calculation of each coefficient. Compared to the fully parallel architecture for even coefficients and the serial architecture for odd coefficients, this method saves 55% of adder resources with only two additional cycles.

[0043] 3. This invention uses different keys for row transformation and column transformation when performing CNT transformation, which improves the security of encrypted images while ensuring the encryption function is implemented. Attached Figure Description

[0044] Figure 1 This is an overall flowchart of the present invention;

[0045] Figure 2 This is a hardware circuit diagram of the CNT conversion module of the present invention;

[0046] Figure 3 This is a circuit diagram of the model extraction module of the present invention;

[0047] Figure 4 This is a timing diagram of the CNT conversion module of the present invention;

[0048] Figure 5 Circuit diagram for selecting modules in this invention;

[0049] Figure 6 This is a circuit diagram of the transpose module of the present invention. Detailed Implementation

[0050] In this embodiment, an image encryption hardware accelerator based on Cosine Number Transform (CNT) is described, such as... Figure 1As shown, it includes: a modulus extraction module, a CNT transformation module, a selection module, and a transpose module; wherein, the transpose module includes a first RAM and a second RAM;

[0051] like Figure 2 As shown, the CNT transformation module receives an externally input image of size k×k pixels and performs block processing to obtain several image blocks of size 8×8 pixels. In this embodiment, k = 512, that is, the externally input image size is 512×512 pixels. Each image block is subjected to j 1D-CNT row transformations, processing 8 data x0 to x7 each time, and finally obtaining j sets of C′0 to C′7, realizing the transformation from temporal domain pixel values ​​to finite domain pixel values. In this embodiment, j = 4, that is, each image block is subjected to 4 1D-CNT row transformations.

[0052] The modulus module divides each data point in the t-bit intermediate data of the CNT transformation module into a low t / 2 bit data and a high t / 2 bit data. The high t / 2 bit data is multiplied by negative one and then added to the low t / 2 bit data to obtain the modulus result of each data point, which is then returned to the CNT transformation module. If the modulus result is negative, the modulus q is added to the negative modulus result to obtain the final modulus result. In this embodiment, t = 16 and the modulus q is 257.

[0053] The intermediate data includes: preprocessed data a0~a3, preliminary CNT row transformation results y0~y7, and a set of 1D-CNT coefficients C0~C7; the modulus results include: preprocessed data a′0~a′3 after modulus, preliminary CNT row transformation results y′0~y′7 after modulus, and a set of 1D-CNT coefficients C′0~C′7 after modulus.

[0054] like Figure 3 As shown, taking preprocessed data a0 as an example, the integer a0 with a bit width of 16 bits is input into the modulo module, and after the following modulo operation, the integer a′0 with a bit width of 9 bits is output, where the modulus q = 257.

[0055] When a0≥0 and a0[15:8]>a0[7:0], a′0 a0[7:0]-a0[15:8]q;

[0056] When a0≥0 and a0[15:8]≤a0[7:0], a′0=a0[7:0]-a0[15:8];

[0057] When a0 < 0, a′0 = a0[7:0] - a0[15:8] + q - 1.

[0058] like Figure 4As shown, it takes 27 cycles to perform a CNT transformation on 8 data points x0 to x7. After 19 clock cycles, a set of 1D-CNT coefficients C′0 to C′7 after modulo is generated. In each subsequent clock cycle, a set of 1D-CNT coefficients after modulo is output. Thus, it takes 262,163 cycles to perform a CNT transformation on an image of size 512×512.

[0059] like Figure 5 As shown, the selection module receives j sets of 1D-CNT coefficients after modulo operation simultaneously through j-1 shift registers, and selects a set of 1D-CNT coefficients after modulo operation as a row of data I0 to I7 of 1D-CNT image block coefficient I according to the first key received from the outside. Thus, after 8 operations on each image block, the 1D-CNT image block coefficient I of 8×8 pixels corresponding to each image block is obtained. In this embodiment, j = 4.

[0060] like Figure 6 As shown, after receiving the 1D-CNT image block coefficients I, the transpose module uses the first RAM to convert the 1D-CNT image block coefficients I into 1D-CNT image block transpose coefficients I in a row-write, column-read manner. T When reading data in the first RAM by column, the 1D-CNT image block coefficients of the next image block are written to the second RAM by row. When reading data in the second RAM by column, the 1D-CNT image block coefficients of the next image block are written to the first RAM by row, thereby realizing the alternating reading and writing of the first RAM and the second RAM until the transpose of the 1D-CNT image block coefficients of all image blocks is completed.

[0061] The CNT transformation module receives the transpose coefficient I of an 8×8 pixel 1D-CNT image block. T and to I T The data in a row i0 to i7 are subjected to four CNT column transformations and several modulo operations to obtain four sets of 2D-CNT coefficients after modulo operation.

[0062] The modulus extraction module extracts the modulus of some intermediate data from the CNT transformation module and returns it to the CNT transformation module.

[0063] The selection module simultaneously receives four sets of 2D-CNT coefficients after modulo operation through three shift registers, and selects one set of 2D-CNT coefficients as a row of data M0 to M7 of the 2D-CNT image block coefficients M based on the externally received second key. T After eight calculations, the coefficients M of the 8×8 pixel 2D-CNT image block are obtained to encrypt the 512×512 pixel image.

[0064] In this embodiment, an image encryption hardware acceleration method based on cosine transform is applied to an accelerator composed of a modulus extraction module, a CNT transform module, a selection module, and a transpose module. The CNT transform module includes a hybrid addition / subtraction module, an even coefficient generation module, and an odd coefficient generation module. The transpose module includes a first RAM and a second RAM with a depth of 8×8. The image encryption hardware acceleration method is performed according to the following steps:

[0065] Step 1: The CNT transformation module acquires an image of size k×k pixels and performs block processing to obtain several image blocks of size 8×8 pixels. In this embodiment, k=512, that is, the size of the external input image is 512×512 pixels. After block processing, 64×64 image blocks of size 8×8 pixels are obtained. Any one of these image blocks is denoted as A.

[0066] Step 2: The CNT transformation module sends the 8 pixels x0 to x7 in image block A to its own hybrid addition and subtraction operation module. The hybrid addition and subtraction operation module performs addition or subtraction operations on x0 to x7 respectively according to the external enable signal en to obtain preprocessed data a0 to a3.

[0067] If en is high, then addition is performed on x0 to x7, that is:

[0068] a0=x0+x7, a1=x1+x6, a2=x2+x5, a3=x3+x4;

[0069] If en is low, then subtraction is performed on x0 to x7, that is:

[0070] a0=x0-x7, a1=x1-x6, a2=x2-x5, a3=x3-x4;

[0071] Step 3: The modulo module divides the preprocessed data a0 to a3, each with a bit width of t, into low t / 2 bits and high t / 2 bits. The high t / 2 bits are multiplied by negative one and then added to the low t / 2 bits to obtain the modulo result a′0 to a′3 for each data. If the modulo result is negative, the modulo result of the negative number is added to the modulo number q to obtain the final modulo result. In this embodiment, the data bit width t = 16 and the modulo number q = 257.

[0072] Step 4: If en is high, the modulo result a′0~a′3 of the preprocessed data is sent to the even coefficient generation module. The first adder in the even coefficient generation module performs addition operation on a′0~a′3 and outputs two coefficients b0 and b1, where b0=a′0+a′3 and b1=a′1+a′2.

[0073] Meanwhile, the four shift-addition / subtraction modules SAU1, SAU2, SAU3, and SAU4 in the even coefficient generation module perform shift and addition / subtraction operations on a′0 to a′3 respectively, obtaining two coefficients output by each shift-addition / subtraction module. Specifically, as follows: Figure 2 As shown in part (a) of the diagram, in this embodiment, the shift addition / subtraction module SAU1 in the even coefficient generation module receives the preprocessed data a′0, shifts it left by 6 bits to obtain 64a′0, shifts it left by 3 bits to obtain 8a′0, shifts it left by 2 bits to obtain 4a′0, then subtracts 64a′0 from a′0 to output the coefficient 63a′0, and adds 8a′0 to 4a′0 to output the coefficient 12a′0; similarly, as... Figure 2 As shown in parts (b), (c), and (d), the other three shift and addition / subtraction modules SAU2, SAU3, and SAU4 in the even coefficient generation module perform shift and addition / subtraction operations on a′1 to a′3 respectively, to obtain two coefficients output by each shift and addition / subtraction module.

[0074] Step 5: If en is low, then send a′0 to a′3 to the odd coefficient generation module, such as... Figure 2 As shown in parts (e), (f), (g), and (h), the four shift addition and subtraction modules SAU5, SAU6, SAU7, and SAU8 perform shift and addition / subtraction operations on a′0 to a′3 respectively, resulting in four coefficients output by each shift addition and subtraction module.

[0075] Step 6: The second adder in the even coefficient generation module receives two coefficients b0 and b1 and performs an addition operation to obtain the 0th term y0 of the preliminary CNT row transformation result;

[0076] Step 7: Multiply the two coefficients b0 and b1 by 227 and 30 respectively, and then send them to the third adder in the even coefficient generation module for addition operation to obtain the fourth term y4 of the preliminary CNT row transformation result;

[0077] Step 8: The fourth adder in the even coefficient generation module receives a coefficient 63a′0 output from the shift addition / subtraction module SAU1 and a coefficient 194a′3 output from SAU4, and performs an addition operation to obtain an intermediate addition value c. 00 ;

[0078] The fifth adder in the even coefficient generation module receives a coefficient 12a′1 output from the shift addition / subtraction module SAU2 and a coefficient 245a′2 output from SAU3, and performs an addition operation to obtain an intermediate addition value c. 10 ;

[0079] Step 9: The fourth and fifth adders in the multiplexed even coefficient generation module receive the coefficients output by the shift addition and subtraction modules SAU1 to SAU4 respectively and perform addition operations to obtain two intermediate addition values ​​c respectively. 01 ,c 11 , where: c 01 =12a′0+245a′3,c 11 =194a′1+63a′2;

[0080] The fourth and fifth adders in the multiplexed fourth-order even coefficient generation module receive the coefficients output by the shift addition and subtraction modules SAU5 to SAU8 respectively and perform addition operations to obtain eight intermediate addition values ​​c. 02 ,c 12 ,c 03 ,c 13 ,c 04 ,c 14 ,c 05 ,c 15 ,in:

[0081]

[0082] Step 10: The sixth adder in the even coefficient generation module receives two intermediate addition values ​​c. 00 ,c 10 The addition operation is then performed to obtain the second term y2 of the preliminary CNT row transformation result; the seventh adder in the even coefficient generation module and the eighth to eleventh adders in the odd coefficient generation module each receive two intermediate addition values ​​and perform addition operations to obtain the remaining terms y6, y1, y3, y5, y7 of the preliminary CNT row transformation result, respectively, where:

[0083] y6=c 01 +c 11 ,y1=c 02 +c 12 y3=c 03 +c 13 y5=c 04 +c 14 y7=c 05 +c 15 ;

[0084] Step 11: The modulus extraction module extracts the modulus of the preliminary CNT row transformation results y0~y7 to obtain the modulo-extracted preliminary CNT row transformation results y′0~y′7;

[0085] Step 12: Multiply the initial 1D-CNT row transformation results y′0~y′7 after taking the modulus by the corresponding normalization factors β0~β7 respectively to obtain a set of 1D-CNT coefficients C0~C7, where β0=15 and the values ​​of β1~β7 are all 1 / 2;

[0086] Step 13: The modulus extraction module extracts the modulus of a set of 1D-CNT coefficients C0 to C7 to obtain a set of 1D-CNT coefficients C′0 to C′7 after the modulus extraction.

[0087] Step 14: The selection module receives j sets of 1D-CNT coefficients after modulo operation simultaneously through j-1 shift registers, and selects a set of 1D-CNT coefficients after modulo operation as a row of data I0 to I7 of 1D-CNT image block coefficient I according to the first key received from the outside. Thus, after 8 operations on image block A, the 8×8 pixel 1D-CNT image block coefficient I is obtained. In this embodiment, j = 4.

[0088] Step 15: The transpose module writes a row of data I0 to I7 from the 1D-CNT image block coefficients I into the first RAM row by row until all 8 rows are written; then, it reads a column of data i0 to i7 from the first RAM column by column until all 8 columns are read, thus obtaining the 8×8 1D-CNT image block transpose coefficients I. T Simultaneously, write one row of data J0 to J7 from the coefficients J of the 1D-CNT image block corresponding to the next image block B into the second RAM row by row until all 8 rows have been written.

[0089] Then, a column of data j0 to j7 in the second RAM is read out column by column until all 8 columns are read; at the same time, a row of data in the 1D-CNT image block coefficients corresponding to the next image block C is written into the first RAM row by row until all 8 rows are written, thereby realizing the alternating reading and writing of the first RAM and the second RAM until the transpose of the 1D-CNT image block coefficients of all image blocks is completed.

[0090] Step 16: The CNT transformation module receives the transpose coefficient I of an 8×8 pixel 1D-CNT image block. T and to I T The data in a row i0 to i7 are subjected to four CNT column transformations and several modulo operations to obtain four sets of 2D-CNT coefficients after modulo operation.

[0091] Step 17: The modulus extraction module extracts the modulus of some intermediate data from the CNT transformation module and returns it to the CNT transformation module;

[0092] Step 18: The selection module simultaneously receives four sets of 2D-CNT coefficients after modulo operation through three shift registers, and selects one set of 2D-CNT coefficients after modulo operation as a row of data M0 to M7 of the 2D-CNT image block coefficients M, thereby adjusting the 1D-CNT image block transpose coefficients I. TAfter eight calculations, the coefficients M of the 2D-CNT image block of 8×8 pixels are obtained to encrypt the 512×512 pixel image.

Claims

1. A hardware accelerator for image encryption based on cosine transform, characterized in that, include: The system includes a modulus extraction module, a CNT transformation module, a selection module, and a transpose module; wherein the transpose module includes a first RAM and a second RAM. The CNT transformation module receives an externally input image of size k×k pixels and performs block processing to obtain several image blocks of size 8×8 pixels. For each image block, j CNT row transformations and several modulo operations are performed on 8 pixels x0 to x7 to obtain j sets of 1D-CNT coefficients after modulo operation. The modulus-taking module divides each data point in the t-bit-wide intermediate data of the CNT transformation module into low t / 2 bits and high t / 2 bits. It then multiplies the high t / 2 bits by -1 and adds them to the low t / 2 bits to obtain the modulus result for each data point, which is returned to the CNT transformation module. If the modulus result is negative, the modulus q is added to the negative modulus result to obtain the final modulus result. The intermediate data includes: preprocessed data a0~a3, preliminary CNT row transformation results y0~y7, and a set of 1D-CNT coefficients C0~C7. The modulus result includes: preprocessed data a′0~a3′ after modulus taking, preliminary CNT row transformation results y′0~y′7 after modulus taking, and a set of 1D-CNT coefficients C0′~C7′ after modulus taking. The selection module simultaneously receives j sets of 1D-CNT coefficients after modulo operation through j-1 shift registers, and selects a set of 1D-CNT coefficients after modulo operation as a row of data I0 to I7 of 1D-CNT image block coefficient I according to the first key received from the outside. Thus, after 8 operations on each image block, the 1D-CNT image block coefficient I of 8×8 pixels corresponding to each image block is obtained. After receiving the 1D-CNT image block coefficient I, the transpose module uses the first RAM to convert the 1D-CNT image block coefficient I into the 1D-CNT image block transpose coefficient I in a row-write and column-read manner. T When reading data in the first RAM by column, the 1D-CNT image block coefficients of the next image block are written to the second RAM by row. When reading data in the second RAM by column, the 1D-CNT image block coefficients of the next image block are written to the first RAM by row, thereby realizing the alternating reading and writing of the first RAM and the second RAM until the transpose of the 1D-CNT image block coefficients of all image blocks is completed. The CNT transformation module receives the transpose coefficient I of an 8×8 pixel 1D-CNT image block. T and to I T A row of data i0 to i7 undergoes j CNT column transformations and several modulo operations to obtain j sets of 2D-CNT coefficients after modulo operations; The modulus extraction module extracts a portion of the intermediate data from the CNT transformation module and returns it to the CNT transformation module. The selection module simultaneously receives j sets of modulo-digested 2D-CNT coefficients through j-1 shift registers, and selects one set of modulo-digested 2D-CNT coefficients as a row of data M0 to M7 of the 2D-CNT image block coefficients M, thereby controlling I. T After eight calculations, the coefficients M of the 8×8 pixel 2D-CNT image block are obtained to encrypt the k×k pixel image.

2. A hardware acceleration method for image encryption based on cosine transform, characterized in that, It is applied in an accelerator composed of a modulus extraction module, a CNT transformation module, a selection module, and a transpose module. The CNT transformation module includes a hybrid addition / subtraction module, an even coefficient generation module, and an odd coefficient generation module. The transpose module includes a first RAM and a second RAM with a depth of 8×8. The image encryption hardware acceleration method is performed according to the following steps: Step 1: The CNT transformation module acquires an image of size k×k pixels and performs block processing to obtain several image blocks of size 8×8 pixels. Any one of these image blocks is denoted as A. Step 2: The CNT transformation module sends the 8 pixels x0 to x7 in image block A to its own hybrid addition and subtraction operation module. The hybrid addition and subtraction operation module performs addition or subtraction operations on x0 to x7 respectively according to the external enable signal en to obtain preprocessed data a0 to a3. If en is high, then add operations are performed on x0 to x7; If en is low, then subtraction is performed on x0 to x7; Step 3: The modulo module divides the preprocessed data a0 to a3, each with a bit width of t, into low t / 2 bits and high t / 2 bits respectively. The high t / 2 bits are multiplied by negative one and then added to the low t / 2 bits to obtain the modulo result a′0 to a3′ for each data. If the modulo result is negative, the modulo result of the negative number is added to the modulus q to obtain the final modulo result. Step 4: If en is high, the modulo result a′0~a3′ of the preprocessed data is sent to the even coefficient generation module. The first adder in the even coefficient generation module performs addition operations on a′0~a3′ and outputs two coefficients b0 and b1. At the same time, the four shift addition and subtraction modules SAU1, SAU2, SAU3 and SAU4 in the even coefficient generation module perform shift and addition and subtraction operations on a′0~a3′ respectively to obtain two coefficients output by each shift addition and subtraction module. Step 5: If en is low, then a′0~a3′ is sent to the odd coefficient generation module. The four shift addition and subtraction modules SAU5, SAU6, SAU7, and SAU8 perform shift and addition / subtraction operations on a′0~a3′ respectively, and obtain the four coefficients output by each shift addition and subtraction module. Step 6: The second adder in the even coefficient generation module receives two coefficients b0 and b1 and performs an addition operation to obtain the 0th term y0 of the preliminary CNT row transformation result; Step 7: The two coefficients b0 and b1 are multiplied by different numbers and then sent to the third adder in the even coefficient generation module for addition to obtain the fourth term y4 of the preliminary CNT row transformation result; Step 8: The fourth adder in the even coefficient generation module receives a coefficient output from the shift addition and subtraction modules SAU1 and SAU4 respectively and performs an addition operation to obtain an intermediate addition value c. 00 ; The fifth adder in the even coefficient generation module receives a coefficient output by shift addition and subtraction modules SAU2 and SAU3 respectively and performs an addition operation to obtain an intermediate addition value c. 10 ; Step 9: Reuse the fourth and fifth adders in the even coefficient generation module described five times to receive the coefficients output by the eight shift addition and subtraction modules SAU and perform addition operations to obtain 10 intermediate addition values ​​c. 01 ,c 11 ,c 02 ,c 12 ,c 03 ,c 13 ,c 04 ,c 14 ,c 05 ,c 15 ; Step 10: The sixth adder in the even coefficient generation module receives two intermediate addition values ​​c respectively. 00 ,c 10 Then perform an addition operation to obtain the second term y2 of the preliminary CNT row transformation result; The seventh adder in the even coefficient generation module and the eighth to eleventh adders in the odd coefficient generation module each receive two intermediate addition values ​​and perform addition operations, thereby obtaining the remaining terms y6, y1, y3, y5, y7 of the preliminary CNT row transformation result, where y6 = c 01 +c 11 y1=c 02 +c 12 y3=c 03 +c 13 y5=c 04 +c 14 y7 = c 05 +c 15 ; Step 11: The modulus extraction module performs modulus extraction on the preliminary CNT row transformation results y0~y7 to obtain the modulo-extracted preliminary CNT row transformation results y′0~y′7; Step 12: Multiply the initial 1D-CNT row transformation results y′0~y′7 after modulo by the corresponding normalization factors β0~β7 respectively to obtain a set of 1D-CNT coefficients C0~C7; Step 13: The modulus extraction module extracts the modulus of a set of 1D-CNT coefficients C0 to C7 to obtain a set of 1D-CNT coefficients C0′ to C7′ after the modulus extraction. Step 14: The selection module receives j sets of 1D-CNT coefficients after modulo operation through j-1 shift registers simultaneously, and selects a set of 1D-CNT coefficients after modulo operation as a row of data I0 to I7 of 1D-CNT image block coefficient I according to the first key received from the outside. Thus, after 8 operations on image block A, the 8×8 pixel 1D-CNT image block coefficient I is obtained. Step 15: The transpose module writes a row of data I0 to I7 from the 1D-CNT image block coefficients I into the first RAM row by row until all 8 rows are written; then, it reads a column of data i0 to i7 from the first RAM column by column until all 8 columns are read, thereby obtaining the 8×8 1D-CNT image block transpose coefficients I. T Simultaneously, write one row of data J0 to J7 from the coefficient J of the 1D-CNT image block corresponding to the next image block B into the second RAM row by row until all 8 rows have been written. Then, a column of data j0 to j7 in the second RAM is read out column by column until all 8 columns are read; at the same time, a row of data in the 1D-CNT image block coefficients corresponding to the next image block C is written into the first RAM row by row until all 8 rows are written, thereby realizing the alternating reading and writing of the first RAM and the second RAM until the transpose of the 1D-CNT image block coefficients of all image blocks is completed. Step 16: The CNT transformation module receives the transpose coefficient I of an 8×8 pixel 1D-CNT image block. T and to I T A row of data i0 to i7 undergoes j CNT column transformations and several modulo operations to obtain j sets of 2D-CNT coefficients after modulo operations; Step 17: The modulus extraction module performs modulus extraction on a portion of the intermediate data in the CNT transformation module and returns it to the CNT transformation module; Step 18: The selection module simultaneously receives j sets of modulo-digested 2D-CNT coefficients through j-1 shift registers, and selects a set of modulo-digested 2D-CNT coefficients as a row of data M0 to M7 of the 2D-CNT image block coefficients M, thereby adjusting the 1D-CNT image block transpose coefficients I. T After eight calculations, the coefficients M of the 2D-CNT image block of 8×8 pixels are obtained, which can be used to encrypt the image of k×k pixels.

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