Flip-flop conversion method and device based on data input end setup time margin

Abstract

The application relates to a flip-flop conversion method and device based on a data input end establishment time margin. The method comprises the following steps: after the layout of an integrated circuit is completed, the flip-flops in the integrated circuit are traversed to obtain the establishment time timing margin of the data input end of each flip-flop and the average value of the establishment time of the flip-flops in the integrated circuit. A flip-flop replacement interval is set. The upper limit and the lower limit of the flip-flop replacement interval are determined according to the average value of the establishment time and a preset ratio. If the establishment time timing margin of the data input end of the current flip-flop is within the flip-flop replacement interval, the current flip-flop is replaced by a high-performance flip-flop. The high-performance flip-flop refers to a flip-flop with an establishment time smaller than that of the current flip-flop. The method can reduce the area and power consumption of a chip, and further reduce the high-performance computing cost.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and in particular to a flip-flop conversion method and apparatus based on establishing a time margin at the data input terminal. Background Technology

[0002] With the rapid development of social informatization and artificial intelligence, supercomputers are moving from the post-P-level era to the E-level. High-performance computing power has become a crucial foundation for human productivity. Research from Stanford University has found that since 2012, the computing power demand of artificial intelligence has doubled every 3.4 months, a rate exceeding Moore's Law (the number of transistors in a chip doubles every 18 months). However, relying on advanced process technology to improve chip energy efficiency is becoming increasingly difficult, while carbon neutrality and energy conservation requirements are becoming increasingly stringent. Currently, the world's fastest supercomputer, Supercomputer Fugaku, uses a 7nm manufacturing process, with a peak performance of approximately 0.5 Eflops, a power consumption of approximately 30MW, and a double-precision floating-point computing energy efficiency ratio of approximately 16 Gflops / W. Based on an electricity cost of 0.6 yuan / kWh, Supercomputer Fugaku's annual electricity cost could reach 160 million yuan. This demonstrates the enormous cost of high-performance computing and the urgent need for advanced chip design methods to reduce its cost.

[0003] However, the core computing part of most high-performance computing chips is currently synchronous circuit. Its basic structure includes emit and capture flip-flops (i.e., UFF0 and UFF1), combinational logic, and clock tree. Synchronous circuits work under the drive of the clock and are required to meet setup time constraints. Otherwise, the circuit will malfunction. When setup time constraints are violated, additional buffers and inverters need to be inserted to reduce data path delay. This will increase the chip area and power consumption, thus increasing the cost of high-performance computing. Summary of the Invention

[0004] Therefore, it is necessary to provide a trigger conversion method and apparatus that can dynamically adjust the performance of the trigger based on the time margin established at the data input terminal, in order to address the above-mentioned technical problems.

[0005] A trigger conversion method based on establishing a time margin at the data input terminal, the method comprising:

[0006] After the integrated circuit layout is completed, the flip-flops in the integrated circuit are traversed to obtain the setup time timing margin of each flip-flop's data input terminal and the average setup time of the flip-flops in the integrated circuit.

[0007] Set the trigger replacement interval. The upper and lower limits of the trigger replacement interval are determined based on the average setup time and a preset ratio.

[0008] If the setup time margin at the current trigger's data input is within the trigger replacement interval, then the current trigger will be replaced with a high-performance trigger. A high-performance trigger is one whose setup time is shorter than that of the current trigger.

[0009] In one embodiment, the method further includes: after the integrated circuit is laid out through the integrated circuit development process, traversing the flip-flops in the integrated circuit, constructing the setup time timing margin of the flip-flop data input terminal, and obtaining the average setup time of the flip-flops in the integrated circuit.

[0010] In one embodiment, the preset ratio β is the ratio of the preset setup time of the high-performance trigger to the setup time of the current trigger.

[0011] In one embodiment, the method further includes: defining the trigger replacement interval as [N, M], and determining the lower limit N of the trigger replacement interval as avg(T) by taking the negative of the average setup time and a pre-set ratio. setup )*(β-1). Based on the average establishment time and a pre-set ratio, a positive number is taken to determine the upper limit M value of the trigger replacement interval as avg(T). setup )*(1-β). Where, T setup This refers to the trigger setup time.

[0012] In one embodiment, the method further includes: traversing the integrated circuit composed of the current triggers to obtain power consumption data; and performing iterative optimization based on the power consumption data to determine the layout of the high-performance integrated circuit.

[0013] In one embodiment, it further includes:

[0014] setup slack=T capture +T cycle -T setup -(T launch +T ck2q +T dp )

[0015] Where setup slack is the setup time timing margin at the trigger data input, T capture To capture the clock delay, T cycle T is the clock period. setup T is the setup time of the trigger. launch T is the delay of the transmit clock. ck2q T is the delay from the clock input to the output of the emitter trigger.dp This is the delay for combinational logic.

[0016] In one embodiment, the integrated circuit development process includes: RTL design, logic synthesis, insertion scan chain, chip placement, standard cell placement, clock tree synthesis, routing, and area and power consumption assessment.

[0017] In one embodiment, the integrated circuit includes: a flip-flop, combinational logic, and a clock tree.

[0018] A trigger conversion device based on a time margin established at the data input terminal, the device comprising:

[0019] The setup time module is used to traverse the flip-flops in the integrated circuit after the integrated circuit layout is completed, and obtain the setup time timing margin of each flip-flop's data input terminal and the average setup time of the flip-flops in the integrated circuit.

[0020] The replacement interval setting module is used to set the trigger replacement interval. The upper and lower limits of the trigger replacement interval are determined based on the average setup time and a preset ratio.

[0021] The trigger replacement module is used to replace the current trigger with a high-performance trigger if the setup time margin at the current trigger's data input is within the trigger replacement interval. A high-performance trigger is a trigger whose setup time is shorter than that of the current trigger.

[0022] In one embodiment, the high-performance trigger is made of an extremely low threshold transistor or is custom-designed.

[0023] The aforementioned method and apparatus for flip-flop conversion based on setup time margin at the data input terminal obtains the relationship between the setup time of each flip-flop in the integrated circuit and the setup time margin of the high-performance flip-flop, and combines this with the setup time margin at the data input terminal of the flip-flop. This relationship serves as the basis for determining flip-flop replacement, constructing a replacement interval for the flip-flop. When the setup time margin at the data input terminal of the flip-flop is within the replacement interval, the flip-flop is converted into a high-performance flip-flop. The power consumption data corresponding to the replaced flip-flop is statistically analyzed. Based on the availability of computing resources, the replacement interval range of the flip-flop can be iteratively optimized in real time to determine the flip-flop with the lowest power consumption and its corresponding integrated circuit layout. Based on this, a high-performance integrated circuit with the lowest power consumption can be designed. Attached Figure Description

[0024] Figure 1 This represents a typical structural composition of digital circuits in existing technologies;

[0025] Figure 2This is a flowchart illustrating a trigger conversion method and apparatus for establishing a time margin based on a data input terminal in one embodiment.

[0026] Figure 3 This is a schematic diagram of the process of integrated circuit development in the prior art;

[0027] Figure 4 As an example of the setup time timing margin at the data input terminal of the capture trigger in another embodiment, the setup time timing margin at the data input terminal D of the capture trigger UFF1 is -70ps;

[0028] Figure 5 This is the circuit after the capture trigger UFF1 is replaced with a high-performance trigger in another embodiment;

[0029] Figure 6 As an example of the setup time timing margin at the data input terminal of the capture trigger in another embodiment, the setup time timing margin at the data input terminal D of the capture trigger UFF1 is 100ps;

[0030] Figure 7 This is a flowchart illustrating a trigger conversion method for establishing timing margin based on data input in one embodiment.

[0031] Figure 8 This is a structural block diagram of a trigger conversion device that establishes a time margin based on the data input terminal in one embodiment. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0033] The trigger conversion method based on establishing a time margin at the data input terminal provided in this application can be applied to, for example... Figure 1 In the digital integrated circuit shown, the core computing part of the digital integrated circuit for high-performance computer chips is a synchronous circuit. The digital integrated circuit includes at least an emit flip-flop UFF0 and a capture flip-flop UFF1, combinational logic, and a clock tree.

[0034] In one embodiment, such as Figure 2 As shown, a trigger conversion method based on establishing a time margin at the data input terminal is provided, which can be applied to... Figure 1 Taking digital integrated circuits as an example, the explanation includes the following steps:

[0035] Step 202: After the integrated circuit layout is completed, traverse the flip-flops in the integrated circuit to obtain the setup time timing margin of each flip-flop data input terminal and the average setup time of the flip-flops in the integrated circuit.

[0036] The core computing components of high-performance computing chips are all digital synchronous circuits, and their basic structure is as follows: Figure 1 As shown, this includes flip-flops (UFF0 and UFF1), combinational logic, and a clock tree, where flip-flop UFF0 is an emitter flip-flop and flip-flop UFF1 is a capture flip-flop. Specifically, as... Figure 3 As shown, the layout of the digital integrated synchronous circuit is performed through the integrated circuit development flow. The layout is completed in the following order: RTL design, logic synthesis, insertion of scan chains, chip placement, standard cell placement, clock tree synthesis, routing, and area and power consumption assessment, while satisfying the setup time timing constraint T. launch +T ck2q +T dp <T capture +T cycle -T setup Specifically, it is required that the data emitted by the launch flip-flop UFF0, after a delay of combinational logic, can be stably established for a period of time before the capture clock arrives at the capture flip-flop UFF1. Furthermore, the capture clock lags behind the launch clock by one clock cycle, ensuring that the data can be correctly sampled by the capture clock. Then, the setup time T before the data arrives at each capture flip-flop is obtained by traversing the already laid-out digital synchronous circuit. setup To build the setup time timing margin at the data input of the capture trigger, use setup slack:

[0037] setup slack=T capture +T cycle -T setup -(T launch +T ck2q +T dp )

[0038] Where setup slack is the setup time timing margin at the trigger data input, T capture To capture the clock delay, T cycle T is the clock period. setup T is the setup time of the trigger. launch T is the delay of the transmit clock. ck2q T is the delay from the clock input to the output of the emitter trigger. dpThis is the delay for combinational logic. Based on the number of capture flip-flops in the digital integrated synchronous circuit, the average setup time avg(T) of the capture flip-flops is calculated. setup ).

[0039] Step 204: Set the trigger replacement interval. The upper and lower limits of the trigger replacement interval are determined based on the average setup time and a preset ratio.

[0040] The preset ratio β is the ratio of the preset setup time of the high-performance trigger to the setup time of the current trigger. The setup time T of the high-performance trigger and the ordinary trigger under different transition times and load conditions can be obtained through the circuit simulator SPICE. setup The ratio β.

[0041] Specifically, the trigger replacement interval is [N, M]. The lower limit N of the trigger replacement interval is determined by taking the negative value of the average setup time and a pre-set ratio. A typical value for this lower limit N is avg(T). setup )*(β-1). Based on the average establishment time and a pre-set ratio, a positive number is taken to determine the upper limit M of the trigger replacement interval. The typical value is avg(T). setup )*(1-β). Where, T setup This refers to the trigger setup time.

[0042] Step 206: If the setup time timing margin of the current trigger is within the trigger replacement interval, then replace the current trigger with a high-performance trigger. A high-performance trigger is a trigger whose setup time is shorter than that of the current trigger.

[0043] High-performance capture flip-flops can be constructed from ultra-low threshold transistors or obtained through custom design. Specifically, for each capture flip-flop, it is determined whether the setup slack at its data input is within the flip-flop replacement interval [N, M]. If the setup slack is within the interval, the capture flip-flop is replaced with a high-performance flip-flop; otherwise, it remains unchanged. After this replacement, the digital synchronization circuit consisting of the current flip-flop, combinational logic, and clock tree is calculated to obtain its corresponding chip area and power consumption data. Depending on the availability of computing resources, the area and power consumption data of the digital integrated synchronization circuit are iteratively optimized. N and M can be fine-tuned near their typical values ​​to obtain the new setup slack corresponding to the flip-flop replacement interval [N, M]. The circuit design with the smallest area and power consumption is then selected as the final design, resulting in the layout of the high-performance integrated circuit.

[0044] The aforementioned method and apparatus for flip-flop conversion based on setup time margin at the data input terminal obtains the relationship between the setup time of each flip-flop in the integrated circuit and the setup time margin of the high-performance flip-flop, and combines this with the setup time margin at the data input terminal of the flip-flop. This relationship serves as the basis for determining flip-flop replacement, constructing a replacement interval for the flip-flop. When the setup time margin at the data input terminal of the flip-flop is within the replacement interval, the flip-flop is converted into a high-performance flip-flop. The power consumption data corresponding to the replaced flip-flop is statistically analyzed. Based on the availability of computing resources, the replacement interval range of the flip-flop can be iteratively optimized in real time to determine the flip-flop with the lowest power consumption and its corresponding integrated circuit layout. Based on this, a high-performance integrated circuit with the lowest power consumption can be designed.

[0045] For register-to-register timing paths with a negative setup slack, the data path delay T dp The corresponding values ​​are often large, which can cause the setup time timing constraints to be unmet. Therefore, EDA tools insert additional buffers and inverters during the placement and routing phase to reduce the data path latency T. dp The additional buffers and inverters increase chip area and power consumption, thus raising the cost of high-performance computing. Converting the capture triggers of such timing paths to setup times T... setup Smaller, high-performance capture triggers make it easier to meet setup time constraints, thereby reducing the number of additional buffers and inverters required, which in turn reduces chip area and power consumption.

[0046] In one embodiment, after the integrated circuit is laid out through the integrated circuit development process, the flip-flops in the integrated circuit are traversed to construct the setup time timing margin of the flip-flop data input terminal and obtain the average setup time of the flip-flops in the integrated circuit.

[0047] It is worth noting that for register-to-register timing paths with a negative setup time margin at the capture trigger data input, the data path delay T dp The corresponding values ​​are often large, which can cause the setup time timing constraints to be unmet. Therefore, EDA tools insert additional buffers and inverters during the placement and routing phase to reduce the data path latency T. dp The additional buffers and inverters increase the chip area and power consumption, thus increasing the cost of high-performance computing. Replacing the capture triggers in such timing paths with setup times T setup Smaller, high-performance flip-flops make it easier to meet setup time constraints, which reduces the number of additional buffers and inverters needed, thereby reducing chip area and power consumption.

[0048] In one embodiment, the preset ratio β is the ratio of the preset setup time of the high-performance trigger to the setup time of the current trigger.

[0049] It is worth noting that the setup time (Tsetup) of the high-performance capture trigger is shorter than that of the ordinary capture trigger. The high-performance capture trigger can be constructed from ultra-low threshold transistors or obtained through custom design. Therefore, the high-performance capture trigger can flexibly adjust its hardware characteristics in real time according to the functional requirements of high-performance computing chips, thus making the method of this invention more adaptable.

[0050] In one embodiment, the trigger replacement interval is [N, M]. The lower limit N of the trigger replacement interval is determined by taking the negative of the average setup time and a preset ratio, and then setting it to avg(T). setup )*(β-1). Based on the average establishment time and a pre-set ratio, a positive number is taken to determine the upper limit M value of the trigger replacement interval as avg(T). setup )*(1-β). Where, T setup This refers to the trigger setup time.

[0051] In one embodiment, the integrated circuit composed of the current flip-flops is traversed to obtain power consumption data. Based on the power consumption data, iterative optimization is performed to determine the layout of the high-performance integrated circuit.

[0052] In one embodiment,

[0053] setup slack=T capture +T cycle -T setup -(T launch +T ck2q +T dp )

[0054] Where setup slack is the setup time timing margin at the trigger data input, T capture To capture the clock delay, T cycle T is the clock period. setup T is the setup time of the trigger. launch T is the delay of the transmit clock. ck2q T is the delay from the clock input to the output of the emitter trigger. dp This is the delay for combinational logic.

[0055] In one embodiment, the integrated circuit development process includes: RTL design, logic synthesis, insertion scan chain, chip placement, standard cell placement, clock tree synthesis, routing, and area and power consumption assessment.

[0056] In one embodiment, the integrated circuit includes: a flip-flop, combinational logic, and a clock tree.

[0057] It is worth noting that, such as Figure 3 As shown, the development process for digital integrated synchronous circuits includes RTL design, logic synthesis, scan chain insertion, chip placement, standard cell placement, clock tree synthesis, and routing. The power consumption assessment circuit includes standard cell placement, clock tree synthesis, and routing.

[0058] In another embodiment, such as Figure 7 As shown, based on the existing integrated circuit development process, a flip-flop conversion method is added to establish a timing margin based on the flip-flop data input terminal. The specific steps are as follows:

[0059] The first step is to prepare a high-performance capture trigger. A high-performance capture trigger refers to a trigger with a setup time T. setup A high-performance capture trigger with a shorter setup time than a standard capture trigger can be constructed from extremely low threshold transistors or custom-designed. The high-performance and standard capture triggers Tf are compared using the SPICE circuit simulator under different transition times and load conditions. setup The ratio β.

[0060] The second step, after the chip layout is completed, is to iterate through the setup time timing margins of each flip-flop's data input in the design to obtain the setup time timing margins (setup slack and T) for each flip-flop. setup The average value of avg(T) setup ).

[0061] The third step is to set the transition range [N, M] for the capture trigger. When the setup slack established at the data input of the capture trigger is within this range, the capture trigger is replaced with a high-performance trigger. A typical value for N is avg(T). setup )*(β-1), the typical value of M is avg(T) setup )*(1-β).

[0062] The fourth step is to determine whether the timing margin of the data input is within the transition range [N,M] of the capture trigger for each capture trigger. If the timing margin of the data input is within the transition range [N,M] of the capture trigger, then the capture trigger is replaced with a high-performance trigger; otherwise, it remains unchanged.

[0063] The fifth step involves completing the subsequent standard cell placement, clock tree synthesis, and routing to obtain the chip's area and power consumption data.

[0064] Step 6: Based on the availability of computing resources, N and M can be fine-tuned near their typical values ​​to obtain the new capture trigger transition range [N,M]. Repeat steps 4 and 5 to obtain the chip area and power consumption data corresponding to the transition range [N,M] of each capture trigger.

[0065] Step 7: Based on the area and power consumption data of the chip corresponding to the transition range [N,M] of each capture flip-flop, select the capture flip-flop design with the smallest area and power consumption as the final design of the digital integrated synchronous circuit.

[0066] It should be understood that, although Figure 2 , Figure 3 , Figure 7 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 , Figure 3 , Figure 7 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0067] In one embodiment, such as Figure 4 As shown, the data input of the emit trigger UFF0 needs to pass through two inverters and one AND gate to reach the next capture trigger, which is a relatively long path. The setup time timing margin of the capture trigger UFF1 data input is -70ps. Figure 5 As shown, if the transition range [N,M] of the capture trigger UFF1 is [-80ps, 80ps], because Figure 3 The setup time margin at the data input of the capture trigger UFF1 shown is -70ps, which falls within the transition range [N,M] of the capture trigger UFF1. Therefore, the capture trigger UFF1 is replaced from a normal capture trigger to a high-performance capture trigger. Since the setup time T of the high-performance capture trigger... setup Compared to the setup time of a regular capture trigger, which is 70ps shorter, the setup time timing margin at the data input of the high-performance capture trigger UFF1 becomes 0ps.

[0068] In another embodiment, such as Figure 6As shown, the emit trigger UFF0 only needs to pass through one inverter to reach the next capture trigger, which is a short path. The setup time margin of the data input terminal of the capture trigger UFF1 is 100ps. Therefore, the setup time margin of the data input terminal of the capture trigger UFF1 does not fall within the transition range [-80ps, 80ps] of the capture trigger. Thus, the capture trigger UFF1 remains a normal capture trigger and does not need to be replaced with a high-performance trigger.

[0069] In one embodiment, such as Figure 8 As shown, a trigger conversion device based on a timing margin established at a data input terminal is provided, comprising: an acquisition setup time module, a replacement interval setting module, and a trigger replacement module, wherein:

[0070] The setup time module is used to traverse the flip-flops in the integrated circuit after the integrated circuit layout is completed, and obtain the setup time timing margin of each flip-flop's data input terminal and the average setup time of the flip-flops in the integrated circuit.

[0071] The replacement interval setting module is used to set the trigger replacement interval. The upper and lower limits of the trigger replacement interval are determined based on the average setup time and a preset ratio.

[0072] The trigger replacement module is used to replace the current trigger with a high-performance trigger if the setup time margin at the current trigger's data input is within the trigger replacement interval. A high-performance trigger is a trigger whose setup time is shorter than that of the current trigger.

[0073] In one embodiment, the high-performance trigger is made of an extremely low threshold transistor or is custom-designed.

[0074] Specific limitations regarding the trigger conversion device for establishing time margins based on data input terminals can be found in the limitations of the trigger conversion method for establishing time margins based on data input terminals described above, and will not be repeated here. Each module in the aforementioned trigger conversion device for establishing time margins based on data input terminals can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0075] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0076] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0077] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A trigger conversion method based on establishing a time margin at the data input terminal, characterized in that, When applied to integrated circuits, the method includes: After the integrated circuit layout is completed, the flip-flops in the integrated circuit are traversed to obtain the setup time timing margin of each flip-flop data input terminal and the average setup time of the flip-flops in the integrated circuit; after the integrated circuit is laid out through the integrated circuit development process, the flip-flops in the integrated circuit are traversed to construct the setup time timing margin of the flip-flop data input terminal and obtain the average setup time of the flip-flops in the integrated circuit. Set a trigger replacement interval; the upper and lower limits of the trigger replacement interval are determined based on the average establishment time and a preset ratio; The trigger replacement interval is [N, M]. The lower limit N of the trigger replacement interval is determined by taking the negative of the average setup time and a pre-set ratio. The upper limit M value of the trigger replacement interval is determined by taking a positive number from the average establishment time and a preset ratio. ;in, The setup time of the trigger; If the setup time margin of the current trigger data input is within the trigger replacement interval, then the current trigger will be replaced with a high-performance trigger; the high-performance trigger refers to a trigger whose setup time is less than that of the current trigger.

2. The method according to claim 1, characterized in that, The preset ratio This is a pre-defined ratio of the setup time of a high-performance trigger to the setup time of the current trigger.

3. The method according to claim 2, characterized in that, If the setup time margin of the current trigger data input is within the trigger replacement interval, then the current trigger is replaced with a high-performance trigger. Following this step, the following steps are also included: The power consumption data is obtained by traversing the integrated circuit composed of the current triggers; the layout of the high-performance integrated circuit is determined by iterative optimization based on the power consumption data.

4. The method according to claim 3, characterized in that, The steps for constructing the setup time timing margin of the trigger data input terminal include: in, This is the setup time margin for the data input terminal of the trigger. To capture clock delay, For clock cycles, The setup time of the trigger. For the delay of the transmit clock, This is the delay from the clock input of the emitter trigger to the output. This is the delay for combinational logic.

5. The method according to any one of claims 1 to 4, characterized in that, The development process of the integrated circuit includes: RTL design, logic synthesis, insertion scan chain, chip placement, standard cell placement, clock tree synthesis, routing, and area and power consumption assessment.

6. The method according to any one of claims 1 to 4, characterized in that, The integrated circuit includes: flip-flops, combinational logic, and clock trees.

7. A trigger conversion device with a time margin established based on the data input terminal, characterized in that, The apparatus for implementing the method according to any one of claims 1 to 6, the apparatus comprising: The setup time acquisition module is used to traverse the flip-flops in the integrated circuit after the integrated circuit layout is completed, and obtain the setup time timing margin of each flip-flop data input terminal and the average setup time of the flip-flops in the integrated circuit. The replacement interval setting module is used to set the trigger replacement interval; the upper and lower limits of the trigger replacement interval are determined based on the average establishment time and a preset ratio. The trigger replacement module is used to replace the current trigger with a high-performance trigger if the setup time margin of the current trigger data input terminal is within the trigger replacement interval; the high-performance trigger refers to a trigger whose setup time is less than that of the current trigger.

8. The apparatus according to claim 7, characterized in that, The high-performance trigger is composed of extremely low threshold transistors or is custom-designed.

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