Display device

Abstract

Provided is a display device in which a left ripple transistor provided in a left stage to remove a ripple occurring in a Q node of the left stage and a right ripple transistor provided in a right stage to remove a ripple occurring in a Q node of the right stage repeatedly and simultaneously perform turn-on and turn-off operations.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0186121, filed on December 23, 2021, which is incorporated herein by reference as fully set forth herein. Technical Field

[0003] This disclosure relates to display devices. Background Technology

[0004] Display devices include liquid crystal display (LCD) devices and light-emitting display devices, both of which include a display panel for displaying images.

[0005] The display device includes a gate driver that includes a stage for outputting gate signals to gate lines included in the display panel.

[0006] The duration of the stage's output gate cutoff signal is longer than the duration of the output gate pulse. While the output gate cutoff signal is being output, the gate clock for the output gate pulse is continuously supplied to the stage, which may cause ripple that affects the stage's drive.

[0007] To eliminate the adverse effects of ripple, existing technologies include ripple removal transistors.

[0008] However, when the ripple removal transistor deteriorates, it is difficult to remove ripple properly. A dummy transistor should be added to determine the degree of deterioration of the ripple removal transistor, and the voltage supplied to the ripple removal transistor should vary based on the deterioration of the ripple removal transistor. Therefore, various additional components are required. Summary of the Invention

[0009] Therefore, this disclosure is intended to provide a display device that substantially eliminates one or more problems caused by the limitations and drawbacks of related technologies.

[0010] One aspect of this disclosure aims to provide a display device in which a left ripple transistor disposed in a left stage to remove ripple appearing in the Q node of the left stage and a right ripple transistor disposed in a right stage to remove ripple appearing in the Q node of the right stage repeatedly and simultaneously perform an on-operation and an off-operation.

[0011] Additional advantages and features of this disclosure will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon review of the following description, or may be learned from practice of this disclosure. The purposes and other advantages of this disclosure may be realized and obtained by means of structures particularly pointed out in the draft specification, its claims, and the accompanying drawings.

[0012] To achieve these and other advantages and for the purposes of this disclosure, as embodied and broadly described herein, a display device is provided, comprising: a display panel including a display area and a non-display area surrounding the display area and including gate lines; a left gate driver disposed in a first non-display area of ​​the non-display area to output a left gate pulse and a left gate cutoff signal to the gate lines; and a right gate driver disposed in a second non-display area of ​​the non-display area to output a right gate pulse and a right gate cutoff signal to the gate lines. In this configuration, the left gate driver includes an nth left stage that outputs the nth left gate pulse, and the right gate driver includes an nth right stage that outputs the nth right gate pulse (where n is a natural number). The outputs of the nth left gate pulse and the nth right gate pulse are controlled by the Q nodes included in the nth left stage and the nth right stage, respectively. The nth left ripple transistor in the nth left stage, configured to remove ripple appearing in the nth left Q node of the nth left stage, and the nth right ripple transistor in the nth right stage, configured to remove ripple appearing in the nth right Q node of the nth right stage, repeatedly perform turn-on and turn-off operations.

[0013] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0014] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0015] Figure 1 This is a diagram illustrating the configuration of a display device according to this disclosure;

[0016] Figure 2A and Figure 2B This is a diagram illustrating the structure of pixels applied to a display device according to this disclosure;

[0017] Figure 3 This is a diagram illustrating the structure of a controller applied to a display device according to this disclosure;

[0018] Figure 4 This is a diagram illustrating the structure of each gate driver in a gate driver used in a display device according to this disclosure;

[0019] Figure 5 It is shown schematically. Figure 4 A diagram showing the structure of each level in the hierarchy;

[0020] Figure 6 It is shown in detail Figure 4 A diagram showing the structure of each level in the hierarchy;

[0021] Figure 7 It is a diagram showing the waveforms applied to a display device based on the disclosed content;

[0022] Figure 8 This is a diagram illustrating a method for outputting a gate cutoff signal in a display device according to the present disclosure;

[0023] Figure 9 It is shown in detail Figure 4 Another diagram showing the structure of each level in the hierarchy; and

[0024] Figure 10 This shows the application to Figure 9 The waveform of the stage is shown in the figure. Detailed Implementation

[0025] Reference will now be made in detail to exemplary embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. Throughout the drawings, the same reference numerals will be used to refer to the same or similar parts whenever possible.

[0026] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the embodiments described below with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is defined only by the scope of the claims.

[0027] The shapes, dimensions, ratios, angles, and numbers disclosed in the accompanying drawings to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Similar reference numerals always refer to similar elements. In the following description, detailed descriptions that determine relevant known functions or configurations will be omitted where such descriptions would unnecessarily obscure the essential points of this disclosure. When using the terms "comprising," "having," and "including" as described in this specification, another component may be added unless "only" is used. Unless otherwise specified, singular terms may include plural forms.

[0028] When interpreting a component, it is interpreted as including a range of errors or tolerances, even though there is no explicit description of such a range of errors or tolerances.

[0029] When describing positional relationships, for example, when the positional relationship between two components is described as "on," "above," "below," and "next to," one or more other components may be placed between the two components unless more restrictive terms such as "only" or "directly" are used.

[0030] When describing temporal relationships, such as when time sequence is described as "after", "following", "next" and "before", discontinuous situations may be included unless more restrictive terms such as "exactly", "immediately after" or "directly" are used.

[0031] It will be understood that while the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0032] In describing the elements of this disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to identify the corresponding element from other elements, and the basis, order, or number of the corresponding elements shall not be limited by these terms. Unless otherwise stated, the expression “connected,” “coupled,” or “adhered” to another element or layer means that the element or layer may be directly connected or adhered to another element or layer, or indirectly connected or adhered to another element or layer, wherein one or more intermediate elements or layers are “set” or “inserted” between the elements or layers.

[0033] The term "at least one" should be understood to include any and all combinations of one or more items listed in connection with the terms. For example, "at least one of the first, second, and third items" means a combination of all items derived from two or more of the first, second, and third items, as well as the first, second, or third item.

[0034] Features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may interoperate with each other in various ways and be technically driven, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be performed independently of each other or may be performed together in an interdependent relationship.

[0035] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 This is a diagram illustrating the configuration of a display device according to this disclosure. Figure 2A and Figure 2B This is a diagram illustrating the structure of pixels applied to a display device according to this disclosure. Figure 3 This is a diagram illustrating the structure of a controller applied to a display device according to this disclosure.

[0037] The display devices according to this disclosure can constitute various electronic devices. Electronic devices may include, for example, smartphones, tablet PCs, televisions (TVs), and monitors.

[0038] like Figure 1 As shown, the display device according to this disclosure may include: a display panel 100, which includes a display area 120 for displaying images and a non-display area 130 disposed outside the display area 120; a plurality of gate drivers 200a and 200b supplying gate signals to a plurality of gate lines GL1 to GLg disposed in the display area 120 of the display panel 100; a data driver 300 supplying data voltage to a plurality of data lines DL1 to DLd disposed in the display panel 100; a controller 400 controlling the driving of the gate drivers 200a and 200b and the data driver 300; and a power supply device 500 supplying power to the controller 400, the gate drivers 200a and 200b, the data driver 300, and the display panel 100.

[0039] First, the display panel 100 may include a display area 120 and a non-display area 130. Gate lines GL1 to GLG, data lines DL1 to DLd, and pixels 110 may be provided in the display area 120. Therefore, the display area 120 can display an image. Here, g and d can both be natural numbers. In particular, g can be an even number. The non-display area 130 may surround the display area 120.

[0040] The display panel 100 can include: Figure 2A The liquid crystal display panel with pixel 110 shown may be, or may include: Figure 2B The light-emitting display panel with pixel 110 shown.

[0041] For example, when the display panel 100 is a liquid crystal display panel, such as Figure 2A As shown, the pixels 110 included in the display panel 100 may include: a pixel driving circuit PDC, which includes a switching transistor Tsw1 and a common electrode; and liquid crystal. The liquid crystal may be included in the emission region. In FIG2, Clc may represent the liquid crystal disposed between the common electrode and the pixel electrode connected to the switching transistor Tsw1.

[0042] For example, when the display panel 100 is a light-emitting display panel, such as Figure 2B As shown, the pixels 110 included in the display panel 100 may include: a pixel driving circuit PDC, which includes a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr and a sensing transistor Tsw2; and an emitting area including a light-emitting device ED.

[0043] The structure of the pixel 110 in the liquid crystal display panel and the structure of the pixel 110 in the light-emitting display panel are not limited to... Figure 2A and Figure 2B The structure shown can therefore be implemented in various types.

[0044] In other words, the display device according to this disclosure can be an LCD device including a liquid crystal display panel or a light-emitting display device including a light-emitting display panel, but is not limited thereto, and can be a display device including various types of display panels.

[0045] In the following description, for ease of description, a display device including a light-emitting display panel will be described as an example of the present disclosure.

[0046] The data driver 300 can be mounted on an on-film chip attached to the display panel 100. In this case, the data driver 300 can be connected to the data lines DL1 to DLd included in the display panel 100 and the controller 400 mounted on the main substrate.

[0047] The data driver 300 can be directly installed in the display panel 100 and then connected to the controller 400 located in the main board.

[0048] The data driver 300 can be implemented as an integrated circuit (IC) together with the controller 400. In this case, the IC can be mounted on a chip-on-film device or can be directly integrated into the display panel 100.

[0049] The controller 400 can realign the input video data Ri, Gi, and Bi transmitted from the external system using the timing synchronization signal TSS transmitted from the external system, and can generate a data control signal DCS to be supplied to the data driver 300 and a gate control signal GCS to be supplied to the gate drivers 200a and 200b.

[0050] Therefore, such as Figure 3As shown, the controller 400 may include: a data aligner 430, which realigns input video data Ri, Gi, and Bi to generate image data Data and supplies the image data Data to the data driver 300; a control signal generator 420, which generates a gate control signal GCS and a data control signal DCS using a timing synchronization signal TSS; an input unit 410, which receives the timing synchronization signal TSS and input video data Ri, Gi, and Bi transmitted from an external system and transmits the timing synchronization signal TSS and input video data Ri, Gi, and Bi to the data aligner 430 and the control signal generator 420, respectively; and an output unit 440, which supplies the image data Data generated by the data aligner 430 and the data control signal DCS generated by the control signal generator 420 to the data driver 300 and supplies the gate control signal GCS generated by the control signal generator 420 to the gate drivers 200a and 200b.

[0051] An external system can perform functions that drive the controller 400 and electronic devices. For example, when the electronic device is a TV, the external system can receive various audio, video, and audio information via a communication network and can transmit the received video information to the controller 400. In this case, the image information may include input video data Ri, Gi, and Bi.

[0052] The power supply device 500 can generate various types of electricity and can supply the generated electricity to the controller 400, gate drivers 200a and 200b, data driver 300 and display panel 100.

[0053] Finally, the gate driver 200 can be implemented as an IC and can be disposed in the non-display area 130. Alternatively, the gate driver 200 can be directly embedded in the non-display area 130 using a gate-in-panel (GIP) type. When using the GIP type, the transistors constituting the gate driver 200 can be disposed in the non-display area using the same process as the transistors included in each pixel 110.

[0054] When a gate pulse generated by each of the gate drivers 200a and 200b is supplied to the gate of the switching transistor Tsw1 included in pixel 110, the switching transistor Tsw1 can be turned on. When the switching transistor Tsw1 is turned on, the data voltage supplied through the data line DL can be supplied to pixel 110. When a gate cutoff signal generated by each of the gate drivers 200a and 200b is supplied to the switching transistor Tsw1, the switching transistor Tsw1 can be turned off. When the switching transistor Tsw1 is turned off, the data voltage Vdata can no longer be supplied to pixel 110. The gate signal GS supplied to the gate line GL can include a strobe pulse and a gate cutoff signal.

[0055] In this public disclosure, such as Figure 1 As shown, two gate drivers 200a and 200b can be configured.

[0056] A gate driver 200a may be disposed in a first non-display region 131 of the non-display region 130, which is disposed to the left of the gate line GL. In the following description, the gate driver disposed in the first non-display region 131 may be simply referred to as the left gate driver 200a.

[0057] Another gate driver 200b may be disposed in a second non-display region 132 of the non-display region 130, which is disposed to the right of the gate line GL. In the following description, the gate driver disposed in the second non-display region 132 may be simply referred to as the right gate driver 200b.

[0058] In this configuration, the second non-display area 132 can be positioned facing the first non-display area 131, but is not limited thereto. That is, the positions of the first non-display area 131 and the second non-display area 132 can vary depending on the type of gate line used. Furthermore, in the following description, left and right can refer to one side and the other side of the gate line, and are therefore not limited to the left and right sides used to represent a compass point.

[0059] The following will refer to Figures 4 to 10 The detailed structure and function of the left gate driver 200a and the right gate driver 200b are described below. In the following description, the gate driver 200 can be used in all the cases described in the description of the left gate driver 200a and the right gate driver 200b.

[0060] Figure 4 This is a diagram illustrating the structure of each gate driver in a gate driver used in a display device according to this disclosure. Figure 4In the accompanying drawings, reference numerals L_GCS and R_GCS can refer to the left gate control signal supplied to the left gate driver 200a and the right gate control signal supplied to the right gate driver 200b. The left gate control signal L_GCS and the right gate control signal R_GCS can be generated by the control signal generator 420.

[0061] As described above, the display panel 100 may include a display area 120 and a non-display area 130 surrounding the display area 120, and gate lines GL1 to GLg may be included in the display panel 100.

[0062] The left gate driver 200a can be located in the first non-display area 131 within the non-display area 130 and can output left gate pulses L_GP1 to L_GPg and left gate cutoff signals L_Goff1 to L_Goffg to gate lines GL1 to GLg. Figure 4 In the accompanying drawings, reference numerals L_GS1 to L_GSg can refer to the first left gate signal to the g-th left gate signal. For example, the first left gate signal L_GS1 may include a first left gate pulse L_GP1 and a first left gate cutoff signal L_Goff1, and the g-th left gate signal L_GSg may include the g-th left gate pulse L_GPg and the g-th left gate cutoff signal L_Goffg.

[0063] The right gate driver 200b can be located in the second non-display area 132 within the non-display area 130 and can output right gate pulses R_GP1 to R_GPg and right gate cutoff signals R_Goff1 to R_Goffg to gate lines GL1 to GLg. Figure 4 In the accompanying drawings, reference numerals R_GS1 to R_GSg can refer to the first right gate signal to the g-th right gate signal. For example, the first right gate signal R_GS1 may include a first right gate pulse R_GP1 and a first right gate cutoff signal R_Goff1, and the g-th right gate signal R_GSg may include the g-th right gate pulse R_GPg and the g-th right gate cutoff signal R_Goffg.

[0064] At least one gate line may also be disposed on a first gate line GL1 in the non-display area 130, and at least one gate line may also be disposed on a g-th gate line GLg in the non-display area 130. Figure 1 The image shows a display panel 100, in which two dummy gate lines GL-1 and GL-2 are provided on the first gate line GL1, and two dummy gate lines GL+1 and GL+2 are provided below the g-th gate line GLg.

[0065] In this case, the left gate driver 200a and the right gate driver 200b can output gate pulses and gate cutoff signals to the dummy gate line.

[0066] The left gate driver 200a may include first left gate stages L_Stage 1 to g-th left gate stages L_Stage g. Each left gate stage in the first left gate stages L_Stage 1 to g-th left gate stages L_Stage g can output at least one gate pulse. In the following description, when all gate pulses should be described, the order of the gate pulses is not required, or the gate driver that limits the output gate pulses is not required, the term "gate pulse" may be used as a simple expression. When a general name is required for all stages or the order of the gate pulses is not required, the term "stage" may be used as a simple expression. When a general name is required for all gate cutoff signals or the order of the gate cutoff signals is not required, the term "gate cutoff signal" may be used as a simple expression. Furthermore, in the following description, the stage that outputs the n-th left gate pulse L_GPn and the n-th left gate cutoff signal L_Goffn may be referred to as the n-th left stage L_Stage n. Here, n may be a natural number less than or equal to g.

[0067] The right gate driver 200b may include first right gate stages R_Stage 1 to g-th right gate stages R_Stage g. Each of the first right gate stages R_Stage 1 to g-th right gate stages R_Stage g can output at least one gate pulse. In the following description, the stage that outputs the n-th right gate pulse R_GPn and the n-th right gate cutoff signal R_Goffn may be referred to as the n-th right stage R_Stage n.

[0068] In the following description, the contents of this disclosure will be referred to with reference to the nth left stage L_Stage n and the nth right stage R_Stage n. The description of the nth left stage L_Stage n and the nth right stage R_Stage n below can be applied in the same way to the other stages.

[0069] Figure 5 It is shown schematically. Figure 4 The diagram shows the structure of each level in the hierarchy, and in particular, Figure 5 This is a schematic diagram showing the nth left-hand stage L_Stage n and the nth right-hand stage R_Stage n.

[0070] Each stage in the series may include multiple transistors, and a gate control signal GCS may be supplied to each stage. Each stage may generate a gate pulse using various signals and voltages, and the gate pulse may be sequentially supplied to gate lines GL1 to GLg.

[0071] Therefore, such as Figure 5As shown, the nth left stage L_Stage n may include: an nth left signal generator 210a, which includes an nth left ripple transistor L_Trpn; and an nth left signal output unit 220a, which outputs an nth left gate cutoff signal L_Goffn and an nth left gate pulse L_GPn based on the nth left control signal generated by the nth left signal generator 210a.

[0072] The nth right stage R_Stage n may include: an nth right signal generator 210b, which includes an nth right ripple transistor R_Trpn; and an nth right signal output unit 220b, which outputs an nth right gate cutoff signal R_Goffn and an nth right gate pulse R_GPn based on the nth right control signal generated by the nth right signal generator 210b.

[0073] In this case, the nth left gate cutoff signal L_Goffn and the nth right gate cutoff signal R_Goffn can be alternately output to the nth gate line GLn.

[0074] The nth left signal output unit 220a may include an nth left pull-up transistor L_Tun that outputs the nth left gate pulse L_GPn and an nth left pull-down transistor L_Tdn that outputs the nth left gate cutoff signal L_Goffn. A capacitor C may be provided between the output terminal and the gate of the nth left pull-up transistor L_Tun for stabilizing the output.

[0075] The nth left signal generator 210a can generate signals for driving the nth left pull-up transistor L_Tun and the nth left pull-down transistor L_Tdn.

[0076] The nth right signal output unit 220b may include an nth right pull-up transistor R_Tun that outputs the nth right gate pulse R_GPn and an nth right pull-down transistor R_Tdn that outputs the nth right gate cutoff signal R_Goffn. A capacitor C may be provided between the output terminal and the gate of the nth right pull-up transistor R_Tun for stabilizing the output.

[0077] The nth right signal generator 210b can generate signals for driving the nth right pull-up transistor R_Tun and the nth right pull-down transistor R_Tdn.

[0078] First, the nth left signal generator 210a may include multiple transistors. Figure 5In order to describe the basic structure and basic function of the nth left signal generator 210a applied to this disclosure, an nth left signal generator 210a including three transistors Tst, Trs, and L_Trpn and an inverter IN is shown. That is, in Figure 5 An example of the nth left signal generator 210a applied to the present disclosure is illustrated schematically.

[0079] The start-up transistor Tst can be turned on by the start-up signal Vst and can supply a high voltage VD to the left signal output unit 220a through the nth left Q node L_Qn. The high voltage VD of the start-up transistor Tst can be converted into a voltage lower than the high voltage by the inverter IN and can be transmitted to the nth left Qb node L_Qbn.

[0080] When the power-on transistor Tst is turned on and the reset transistor Trs is turned on via the reset signal Rest, the low voltage GVSS can be supplied to the nth left Qb node L_Qbn through the reset transistor Trs. The low voltage GVSS can be converted to a voltage higher than the low voltage by the inverter IN and can be supplied to the nth left Qb node L_Qbn. The inverter IN can be formed in various structures including at least one transistor to perform the functions described above.

[0081] The first terminal of the nth left ripple transistor L_Trpn can be connected to the nth left Q node L_Qn, the second terminal of the nth left ripple transistor L_Trpn can be connected to the first voltage terminal, and the gate of the nth left ripple transistor L_Trpn can be connected to the gate of the nth left pull-down transistor L_Tdn, which controls the output of the nth left gate cutoff signal L_Goffn.

[0082] Here, the first voltage terminal can be supplied with a low voltage GVSS. That is, the first voltage terminal can be supplied with a low voltage GVSS to turn off the nth left pull-up transistor L_Tun.

[0083] The gates of the nth left-side ripple transistor L_Trpn and the nth left-side pull-down transistor L_Tdn can be connected to the terminal supplied with the nth left-side ripple clock L_DCLK(n). Therefore, the gates of the nth left-side ripple transistor L_Trpn and the nth left-side pull-down transistor L_Tdn can be supplied with the nth left-side ripple clock L_DCLK(n).

[0084] Secondly, the nth right signal generator 210b may include multiple transistors. Figure 5In order to describe the basic structure and basic function of the nth right signal generator 210b applied to this disclosure, an nth right signal generator 210b including three transistors Tst, Trs, and L_Trpn and an inverter IN is shown. That is, in Figure 5 An example of the nth right signal generator 210b applied to the present disclosure is illustrated schematically.

[0085] The start-up transistor Tst can be turned on by the start-up signal Vst and can supply a high voltage VD to the right signal output unit 220b through the nth right Q node R_Qn.

[0086] When the startup transistor Tst is turned off and the reset transistor Trs is turned on via the reset signal Rest, a low voltage GVSS can be supplied to the nth right Q node R_Qn through the reset transistor Trs. The inverter IN can be formed in various structures including at least one transistor.

[0087] The first terminal of the nth right ripple transistor R_Trpn can be connected to the nth right Q node R_Qn, the second terminal of the nth right ripple transistor R_Trpn can be connected to the first voltage terminal, and the gate of the nth right ripple transistor R_Trpn can be connected to the terminal supplied with the nth right ripple clock R_DCLK(n).

[0088] Therefore, the nth right ripple clock R_DCLK(n) can be supplied to the gate of the nth right ripple transistor R_Trpn.

[0089] As described above, the gate of the nth left ripple transistor L_Trpn can be connected to the gate of the nth left pull-down transistor L_Tdn, which controls the output of the nth left gate cutoff signal L_Goffn.

[0090] However, the gate of the nth right ripple transistor R_Trpn may not be connected to the gate of the nth right pull-down transistor R_Tdn, which controls the output of the nth right gate cutoff signal R_Goffn. The gate of the nth right pull-down transistor R_Tdn may be connected to the gate of the (n+1)th right ripple transistor included in the next stage (e.g., the (n+1)th right stage) of the nth right stage R_Stage n. In this case, the gate of the nth right ripple transistor R_Trpn may be connected to the gate of the (n-1)th right pull-down transistor included in the stage preceding (e.g., the (n-1)th right stage) relative to the nth right stage R_Stage n.

[0091] For further description, the outputs of the nth left gate cutoff signal L_Goffn and the nth right gate cutoff signal R_Goffn can be controlled by the Qb nodes included in the nth left stage L_Stage n and the nth right stage R_Stage n. In this case, the gate of the nth left ripple transistor L_Trpn included in the nth left stage L_Stage n and the nth left Qb node L_Qbn can be connected to each other, and the nth right Qb node R_Qbn included in the nth right stage R_Stage n can be connected to the gate of the (n+1)th right ripple transistor included in the (n+1)th right stage.

[0092] Third, the nth left signal output unit 220a may include the nth left pull-up transistor L_Tun that outputs the nth left gate pulse L_GPn, and the gate of the nth left pull-up transistor L_Tun may be connected to the nth left Q node L_Qn.

[0093] The nth left signal output unit 220a may include an nth left pull-down transistor L_Tdn that outputs the nth left gate cutoff signal L_Goffn, and the gate of the nth left pull-down transistor L_Tdn may be connected to the gate of the nth left ripple transistor L_Trpn.

[0094] Fourth, the nth right signal output unit 220b may include the nth right pull-up transistor R_Tun that outputs the nth right gate pulse R_GPn, and the gate of the nth right pull-up transistor R_Tun may be connected to the nth right Q node R_Qn.

[0095] The nth right signal output unit 220b may include the nth right pull-down transistor R_Tdn, which outputs the nth right gate cutoff signal R_Goffn, and the gate of the nth right pull-down transistor R_Tdn may be connected to the gate of the (n+1)th right ripple transistor included in the next stage (e.g., the (n+1)th right stage) of the nth right stage R_Stage n.

[0096] Figure 6 It is shown in detail Figure 4 The diagram shows the structure of each level in the hierarchy. The basic structure of each of the (n-1)th left level L_Stage n-1 to the (n+1)th left level L_Stage n+1 and the (n-1)th right level R_Stage n-1 to the (n+1)th right level R_Stage n+1 can be compared with the above reference. Figure 5 The basic structure of each of the nth left-hand stage L_Stage n and the nth right-hand stage R_Stage n described is the same. Therefore, in the following text, the references above will be omitted or will be briefly given. Figure 5 The given descriptions are the same or similar.

[0097] first, Figure 6The left-hand L_Stage n-1 to the (n+1)th left-hand L_Stage n+1 shown can be implemented as the same type. Therefore, the structure of the nth left-hand L_Stage n will be described below. Figure 5 The nth left-hand comparison shown is in Figure 6 The structure of inverter IN is shown in detail in the nth left stage L_Stage n.

[0098] For example, Figure 6 The inverter IN in the nth left stage L_Stage n shown can include the first transistor T1 through the fourth transistor T4.

[0099] The first terminal and gate of the first transistor T1 can be connected to the terminal to which the nth left ripple clock L_DCLK(n) is input, and the second terminal of the first transistor T1 can be connected to the first terminal of the second transistor T2.

[0100] The first terminal of the second transistor T2 can be connected to the second terminal of the first transistor T1, the gate of the second transistor T2 can be connected to the nth left Q node L_Qn, and the second terminal of the second transistor T2 can be connected to the terminal supplied with a low voltage GVSS.

[0101] The first terminal of the third transistor T3 can be connected to the terminal to which the nth left ripple clock L_DCLK(n) is input, the second terminal of the third transistor T3 can be connected to the first terminal of the fourth transistor T4, and the gate of the third transistor T3 can be connected to the second terminal of the first transistor T1 and the first terminal of the second transistor T2.

[0102] The first terminal of the fourth transistor T4 can be connected to the second terminal of the third transistor T3, the gate of the fourth transistor T4 can be connected to the nth left Q node L_Qn, and the second terminal of the fourth transistor T4 can be connected to the terminal supplied with a low voltage GVSS.

[0103] In addition to the structure described above, the inverter IN in the nth left-hand L_Stage n can also be implemented in various types.

[0104] The first terminal and gate of the start-up transistor Tst in the nth left stage L_Stage n can be supplied with the (n-1)th left gate signal L_GS(n-1) output from the previous stage (e.g., the (n-1)th left stage L_Stage n-1).

[0105] The left gate signal L_GS(n+1) output from the next stage (e.g., the (n+1)th left stage L_Stage n+1) can be input to the gate of the reset transistor Trs in the (n)th left stage L_Stage n.

[0106] Apart from the differences described above, the structure and characteristics of each element in the other elements of the nth left-hand L_Stage n can be compared with those described above. Figure 5 The structure and features of the nth left-hand level are the same, and therefore its detailed description is omitted.

[0107] Secondly Figure 6 The (n-1)th right-hand R_Stage n-1 to the (n+1)th right-hand R_Stage n+1 shown can be implemented as the same type. Therefore, the structure of the nth right-hand R_Stage n will be described below. Figure 5 The nth right-hand comparison shown is in Figure 6 The structure of inverter IN is shown in detail in the nth right stage R_Stage n shown.

[0108] For example, Figure 6 The inverter IN in the nth right-hand stage R_Stage n shown can include the first transistor T1 through the fourth transistor T4.

[0109] The first terminal and gate of the first transistor T1 can be connected to the terminal to which the nth right ripple clock R_DCLK(n) is input, and the second terminal of the first transistor T1 can be connected to the first terminal of the second transistor T2.

[0110] The first terminal of the second transistor T2 can be connected to the second terminal of the first transistor T1, the gate of the second transistor T2 can be connected to the nth right Q node R_Qn, and the second terminal of the second transistor T2 can be connected to the terminal supplied with a low voltage GVSS.

[0111] The first terminal of the third transistor T3 can be connected to the terminal to which the nth right ripple clock R_DCLK(n) is input, the second terminal of the third transistor T3 can be connected to the first terminal of the fourth transistor T4, and the gate of the third transistor T3 can be connected to the second terminal of the first transistor T1 and the first terminal of the second transistor T2.

[0112] The first terminal of the fourth transistor T4 can be connected to the second terminal of the third transistor T3, the gate of the fourth transistor T4 can be connected to the nth right Q node R_Qn, and the second terminal of the fourth transistor T4 can be connected to the terminal supplied with a low voltage GVSS.

[0113] In addition to the structure described above, the inverter IN in the nth right-hand R_Stage n can also be implemented in various types.

[0114] In this case, the arrangement of the first transistor T1 to the fourth transistor T4 included in the inverter IN in the nth right stage R_Stage n can be the same as the arrangement of the first transistor T1 to the fourth transistor T4 included in the inverter IN in the nth left stage L_Stage n.

[0115] The first terminal and gate of the start-up transistor Tst in the nth right stage R_Stage n can be supplied with the (n-1)th right gate signal R_GS(n-1) output from the previous stage (e.g., the (n-1)th right stage R_Stage n-1).

[0116] The (n+1)th right gate signal R_GS(n+1) output from the next stage (e.g., the (n+1)th right stage R_Stage n+1) can be input to the gate of the reset transistor Trs in the (n)th right stage R_Stage n.

[0117] Apart from the differences described above, the structure and characteristics of each element in the other elements of the nth right-hand R_Stage n can be compared with those described above. Figure 5 The structure and features of the nth right-hand level are the same, and therefore its detailed description is omitted.

[0118] In the following text, reference will be made to Figures 1 to 8 Describes a driving method for a display device according to this disclosure.

[0119] Figure 7 It is a diagram showing the waveform applied to a display device according to the disclosed content, and Figure 8 This is a diagram illustrating a method for outputting a gate cutoff signal in a display device according to the present disclosure. In the following description, the present disclosure will be described with reference to the nth left stage L_Stage n and the nth right stage R_Stage n. In the following description, references to the above-mentioned stages will be omitted or will be briefly given. Figures 1 to 6 The given descriptions are the same or similar.

[0120] First, in the first process A, the (n-1)th gate signal GSn-1 with a high level can be input as the start signal for each of the nth left stage L_Stage n and the nth right stage R_Stage n.

[0121] Therefore, the nth left Q node L_Qn and the nth right Q node R_Qn can be charged.

[0122] In the second process B, the nth left gate clock L_SCCLK(n) and the nth right gate clock R_SCCLK(n) can be high. That is, the phase of the nth left gate clock L_SCCLK(n) can be the same as the phase of the nth right gate clock R_SCCLK(n). Therefore, in Figure 7In the diagram, the nth left gate clock L_SCCLK(n) and the nth right gate clock R_SCCLK(n) are shown as the nth gate clock SCCLK(n). In the following description, the nth gate clock SCCLK(n) can be used when it is not necessary to distinguish between the nth left gate clock L_SCCLK(n) and the nth right gate clock R_SCCLK(n).

[0123] Therefore, the levels of the nth left Q node L_Qn and the nth left gate clock L_SCCLK(n) can be increased, and thus, the nth left pull-up transistor L_Tun can be turned on.

[0124] Therefore, the nth gate pulse GPn can be output to the nth gate line GLn through the nth left pull-up transistor L_Tun.

[0125] In this case, the nth gate pulse GPn can be output from the nth right-hand stage R_Stage n using the same method.

[0126] Subsequently, in the third process C, a high-level gate signal GSn+1 can be input as the reset signal for each of the nth left stage L_Stage n and the nth right stage R_Stage n. Therefore, the nth left pull-up transistor L_Tun can be turned off. In this case, the nth right pull-up transistor R_Tun can also be turned off.

[0127] Subsequently, in the third process C, the (n+1)th right ripple clock R_DCLK(n+1) with a high level can be input from the (n+1)th right stage R_Stage n+1 to the nth right Qb node R_Qbn.

[0128] Therefore, the n_1st right gate cutoff signal R_Goffn_1st can be output from the nth right stage R_Stage n to the nth gate line GLn. The n_1st right gate cutoff signal R_Goffn_1st can be configured with the nth right gate cutoff signal R_Goffn.

[0129] In this case, since the nth left ripple clock L_DCLK(n) with a low level is input to the nth right stage R_Stage n, the gate cutoff signal does not need to be output from the nth right stage R_Stage n.

[0130] Subsequently, in the fourth process D, the nth left ripple clock L_DCLK(n) with a high level can be input to the nth left Qb node L_Qbn.

[0131] Therefore, the nth left gate cutoff signal L_Goffn_2nd can be output from the nth left stage L_Stage n to the nth gate line GLn. The nth left gate cutoff signal L_Goffn_2nd can be configured with the nth left gate cutoff signal L_Goffn.

[0132] In this case, a low level can be continuously supplied to the nth left Q node L_Qn.

[0133] However, the nth left gate clock L_SCCLK(n) with a high level can be input to the first terminal of the nth left pull-up transistor L_Tun. Therefore, ripple may occur in the nth left Q node due to the nth left gate clock L_SCCLK(n) with a high level.

[0134] In this case, since the nth left ripple clock L_DCLK(n) with a high level is supplied to the nth left Qb node L_Qbn, the nth left ripple transistor L_Trpn can be turned on. Therefore, the ripple appearing in the nth left Q node L_Qn can be released to the terminal supplied with a low voltage GVSS through the nth left ripple transistor L_Trpn.

[0135] In this case, the nth right ripple transistor R_Trpn can be driven using the same method as the nth left ripple transistor L_Trpn. Therefore, the ripple appearing in the nth right Q node R_Qn can be released to the terminal supplied with a low voltage GVSS through the nth right ripple transistor R_Trpn.

[0136] In other words, since the phase of the nth left ripple clock L_DCLK(n) is the same as the phase of the nth right ripple clock R_DCLK(n), and the phase of the nth left gate clock L_SCCLK(n) is the same as the phase of the nth right gate clock R_SCCLK(n), as described above, the nth left stage L_Stage n and the nth right stage R_Stage n can perform the same operation.

[0137] Subsequently, in the fifth process E, the (n+1)th right ripple clock R_DCLK(n+1) with a high level can be input from the (n+1)th right stage R_Stage n+1 to the nth right Qb node R_Qbn.

[0138] Therefore, the n_3rd right gate cutoff signal R_Goffn_3rd can be output from the nth right stage R_Stage n to the nth gate line GLn. The n_3rd right gate cutoff signal R_Goffn_3rd can be configured with the nth right gate cutoff signal R_Goffn.

[0139] Finally, in the sixth process F, the nth left ripple clock L_DCLK(n) with a high level can be input to the nth left Qb node L_Qbn.

[0140] Therefore, the n_4th left gate cutoff signal L_Goffn_4th can be output from the nth left stage L_Stage n to the nth gate line GLn. The n_4th left gate cutoff signal L_Goffn_4th can be configured with the nth left gate cutoff signal L_Goffn.

[0141] In this case, a low level can be supplied to the nth left Q node L_Qn. However, the nth left gate clock L_SCCLK(n) with a high level may be input to the first terminal of the nth left pull-up transistor L_Tun. Therefore, ripple may occur in the nth left Q node due to the high level of the nth left gate clock L_SCCLK(n).

[0142] In this case, since the nth left ripple clock L_DCLK(n) with a high level is supplied to the nth left Qb node L_Qbn, the nth left ripple transistor L_Trpn can be turned on. Therefore, the ripple appearing in the nth left Q node L_Qn can be released to the terminal supplied with a low voltage GVSS through the nth left ripple transistor L_Trpn.

[0143] In this case, the nth right ripple transistor R_Trpn can be driven using the same method as the nth left ripple transistor L_Trpn. Therefore, the ripple appearing in the nth right Q node R_Qn can be released to the terminal supplied with a low voltage GVSS through the nth right ripple transistor R_Trpn.

[0144] The third process C to the sixth process F can be repeated until another nth gate pulse is output from the nth left stage L_Stage n and the nth right stage R_Stagen, and therefore, the nth gate cutoff signal can be continuously output to the nth gate line GLn.

[0145] In other words, through the process described above, the nth gate pulse GPn can be output from the nth left stage L_Stage n and the nth right stage R_Stage n to the nth gate line GLn.

[0146] In addition, such as Figure 8As shown, the n_1 right gate cutoff signal R_Goffn_1st and the n_3 right gate cutoff signal R_Goffn_3rd can be output from the nth right stage R_Stage n to the nth gate line GLn, and the n_2 left gate cutoff signal L_Goffn_2nd and the n_4 left gate cutoff signal L_Goffn_4th can be output from the nth left stage L_Stage n to the nth gate line GLn.

[0147] In this case, the n_1 right gate cutoff signal R_Goffn_1st, the n_3 right gate cutoff signal R_Goffn_3rd, the n_2 left gate cutoff signal L_Goffn_2nd, and the n_4 left gate cutoff signal L_Goffn_4th can be configured to supply the nth gate cutoff signal Goffn to the nth gate line GLn.

[0148] In this case, Figure 8 For ease of description, the n_1st right gate cutoff signal R_Goffn_1st, the n_3rd right gate cutoff signal R_Goffn_3rd, the n_2nd left gate cutoff signal L_Goffn_2nd, and the n_4th left gate cutoff signal L_Goffn_4th are shown as high-level pulses. However, in the embodiments described above, the n_1st right gate cutoff signal R_Goffn_1st, the n_3rd right gate cutoff signal R_Goffn_3rd, the n_2nd left gate cutoff signal L_Goffn_2nd, and the n_4th left gate cutoff signal L_Goffn_4th can be substantially continuous signals with low levels.

[0149] In other words, the nth left stage L_Stage n and the nth right stage R_Stage n can sequentially output the nth gate cutoff signal Goffn to the nth gate line GLn. Therefore, the nth gate cutoff signal Goffn can be continuously output to the nth gate line GLn.

[0150] In this disclosure, the output of the nth left gate pulse L_GPn and the output of the nth right gate pulse R_GPn can be controlled by the Q nodes included in the nth left stage L_Stage n and the nth right stage R_Stage n.

[0151] In this case, the nth left ripple transistor L_Trpn, which is set in the nth left stage L_Stage n to remove the ripple appearing in the nth left Q node L_Qn of the nth left stage L_Stage n, and the nth right ripple transistor R_Trpn, which is set in the nth right stage R_Stage n to remove the ripple appearing in the nth right Q node R_Qn of the nth right stage R_Stage n, can perform turn-on and turn-off operations simultaneously and continuously.

[0152] Since each of the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn repeatedly performs turn-on and turn-off operations, the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn do not degrade, and the rate of degradation of the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn can be reduced. Therefore, the reliability of the display device including the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn according to this disclosure can be improved.

[0153] The features of this disclosure will be described below.

[0154] First, in this disclosure, the phase of the nth left gate clock L_SCCLK(n) supplied to the nth left stage L_Stage n to generate the nth left gate pulse L_GPn can be the same as the phase of the nth left ripple clock L_DCLK(n) supplied to drive the nth left ripple transistor L_Trpn, and the phase of the nth right gate clock R_SCCLK(n) supplied to the nth right stage R_Stage n to generate the nth right gate pulse R_GPn can be the same as the phase of the nth right ripple clock R_DCLK(n) supplied to drive the nth right ripple transistor R_Trpn.

[0155] In other words, the nth left ripple transistor L_Trpn can be turned on only when ripple appears in the nth left Q node L_Qn, via the nth left gate clock L_SCCLK(n) with a high level, and the nth right ripple transistor R_Trpn can be turned on only when ripple appears in the nth right Q node R_Qn, via the nth right gate clock R_SCCLK(n) with a high level. Therefore, as described above, the degradation rate of the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn can be reduced.

[0156] Secondly, the phase of the nth left ripple clock L_DCLK(n) supplied to drive the nth left ripple transistor L_Trpn can be the same as the phase of the nth right ripple clock R_DCLK(n) supplied to drive the nth right ripple transistor R_Trpn.

[0157] In other words, the nth left ripple clock L_DCLK(n) can be supplied to the gate of the nth left ripple transistor L_Trpn, and the nth right ripple clock R_DCLK(n) can be supplied to the gate of the nth right ripple transistor R_Trpn. The phase of the nth left ripple clock L_DCLK(n) can be the same as the phase of the nth right ripple transistor R_Trpn.

[0158] Therefore, the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn can perform turn-on and turn-off operations simultaneously.

[0159] Third, when the nth left ripple transistor L_Trpn is turned on, the nth left gate cutoff signal L_Goffn can be output from the nth left stage L_Stage n to the nth gate line GLn, and when the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn are turned off, the nth right gate cutoff signal R_Goffn can be output from the nth right stage R_Stage n to the nth gate line GLn.

[0160] In other words, the nth left gate cutoff signal L_Goffn, which is output from the nth left stage L_Stage n, and the nth right gate cutoff signal R_Goffn, which is output from the nth right stage R_Stage n, can be alternately output to the nth gate line GLn.

[0161] For further description, in this disclosure, since gate cutoff signals are alternately output from two stages disposed on both sides of the gate line, a gate cutoff signal can be continuously supplied to the gate line. Therefore, the gate line is not floating, and consequently, the switching transistor connected to the gate line is not abnormally driven. Thus, the reliability of the display device can be improved.

[0162] Figure 9 It is shown in detail Figure 4 Another diagram showing the structure of each level in the hierarchy. Figure 9 The basic structure of each of the (n-1)th left-level L_Stage n-1 to (n+1)th left-level L_Stage n+1 and the (n-1)th right-level R_Stage n-1 to (n+1)th right-level R_Stage n+1 shown above can be compared with the above reference. Figure 5 The basic structure of each of the nth left-hand stage L_Stage n and the nth right-hand stage R_Stage n described is the same. Therefore, in the following text, the references above will be omitted or will be briefly given. Figure 5 and Figure 6 The given descriptions are the same or similar, and in particular, a brief description will be provided. Figure 9 The characteristics of the level shown. In Figure 9 In this case, n can be a natural number less than or equal to g / 2 and can be an even number.

[0163] first, Figure 9 The structure of the nth left signal generator 210a in the nth left stage L_Stage n shown can be compared with... Figure 6 The structure of the nth left signal generator 210a in the nth left stage L_Stage n shown is the same.

[0164] Secondly Figure 6 The nth left signal output unit 220a shown may consist of only the nth left pull-up transistor L_Tun.

[0165] However, Figure 9 The nth left signal output unit 220a shown may include the nth left pull-up transistor L_Tun and the n_2nd left pull-up transistor L_Tun_2.

[0166] In description Figure 9 When the nth left signal output unit 220a is shown, the nth left pull-up transistor L_Tun can be called the n_1th left pull-up transistor L_Tun_1. That is to say, Figure 9 The gate of the n_1 left pull-up transistor L_Tun_1 shown can be connected to the nth left Q node.

[0167] The gate of the n_2nd left pull-up transistor L_Tun_2 can also be connected to the nth left Q node.

[0168] third, Figure 6 The nth left signal output unit 220a shown may consist of only the nth left pull-down transistor L_Tdn.

[0169] However, Figure 9 The nth left signal output unit 220a shown may include an nth left pull-down transistor L_Tdn and an n_2nd left pull-down transistor L_Tdn_2. The n_2nd left pull-down transistor L_Tdn_2 may be connected to the nth left pull-up transistor L_Tun.

[0170] In description Figure 9 When the nth left signal output unit 220a is shown, the nth left pull-down transistor L_Tdn can be called the n_1th left pull-down transistor L_Tdn_1. That is to say, Figure 9 The gate of the n_1 left pull-down transistor L_Tdn_1 shown can be connected to the nth left Qb node L_Qbn.

[0171] The gate of the n_2nd left pull-down transistor L_Tdn_2 can also be connected to the nth left Qb node L_Qbn. Therefore, the gate of the n_2nd left pull-down transistor L_Tdn_2 can also be connected to the gate of the nth left ripple transistor L_Trpn.

[0172] fourth, Figure 9 The structure of the nth right signal generator 210b in the nth right stage R_Stage n shown can be compared with... Figure 6 The structure of the nth right signal generator 210b in the nth right stage R_Stage n shown is the same.

[0173] fifth, Figure 6The nth right signal output unit 220b shown may consist of only the nth right pull-up transistor R_Tun.

[0174] However, Figure 9 The nth right signal output unit 220b shown may include the nth right pull-up transistor R_Tun and the n_2nd right pull-up transistor R_Tun_2.

[0175] In description Figure 9 When the nth right signal output unit 220b is shown, the nth right pull-up transistor R_Tun can be called the n_1th right pull-up transistor R_Tun_1. That is to say, Figure 9 The gate of the n_1 right pull-up transistor R_Tun_1 shown can be connected to the nth right Q node R_Qn.

[0176] The gate of the n_2nd right pull-up transistor R_Tun_2 can also be connected to the nth right Q node R_Qn.

[0177] sixth, Figure 6 The nth right signal output unit 220b shown may consist of only the nth right pull-down transistor R_Tdn.

[0178] However, Figure 9 The nth right signal output unit 220b shown may include an nth right pull-down transistor R_Tdn and an n_2nd right pull-down transistor R_Tdn_2. The n_2nd right pull-down transistor R_Tdn_2 may be connected to the n_2nd right pull-up transistor R_Tun_2.

[0179] In description Figure 9 When the nth right signal output unit 220b is shown, the nth right pull-down transistor R_Tdn can be referred to as the n_1th right pull-down transistor R_Tdn_1. In this case... Figure 9 The gate of the n_1 right pull-down transistor R_Tdn_1 shown can be connected to the gate of the (n+1)th right ripple transistor R_Trpn+1 included in the (n+1)th stage.

[0180] The gate of the n_2nd right pull-down transistor R_Tdn_2 can be connected to the gate of the (n-1)th right ripple transistor R_Trpn-1 included in the (n-1)th right stage R_Stage n-1.

[0181] In other words, Figure 9 The nth left stage L_Stage n and the nth right stage R_Stage n shown can be connected to two gate lines GL2n-1 and GL2n, and can output gate pulse and gate cut-off signal to each of the two gate lines GL2n-1 and GL2n.

[0182] In the following text, reference will be made to Figure 9 and Figure 10 Descriptions based on this disclosure include Figure 9 The driving method for the display device shown is as follows.

[0183] Figure 10 This shows the application to Figure 9 The waveform of the stage is shown in the diagram. In the following description, this disclosure will be described with reference to the nth left stage L_Stage n and the nth right stage R_Stage n. In the following description, references to the above will be omitted or briefly given. Figures 1 to 9 The given descriptions are the same or similar.

[0184] First, in the first process H, a gate signal GSn-1 with a high level can be input as the start signal for each of the nth left stage L_Stage n and the nth right stage R_Stage n.

[0185] Therefore, the nth left Q node L_Qn and the nth right Q node R_Qn can be charged.

[0186] In the second process I, the nth left gate clock L_SCCLK(n) and the (n+1)th left gate clock L_SCCLK(n+1) can be sequentially switched to a high level, and the nth right gate clock R_SCCLK(n) and the (n+1)th right gate clock R_SCCLK(n+1) can also be sequentially switched to a high level. That is, the phase of the nth left gate clock L_SCCLK(n) can be the same as the phase of the nth right gate clock R_SCCLK(n), and the phase of the (n+1)th left gate clock L_SCCLK(n+1) can be the same as the phase of the (n+1)th right gate clock R_SCCLK(n+1). Therefore, in Figure 9 In the diagram, the nth left gate clock L_SCCLK(n) and the nth right gate clock R_SCCLK(n) are shown as the nth gate clock SCCLK(n), and the (n+1)th left gate clock L_SCCLK(n+1) and the (n+1)th right gate clock R_SCCLK(n+1) are shown as the (n+1)th gate clock SCCLK(n+1). In the following description, the nth gate clock SCCLK(n) can be used when it is not necessary to distinguish between the nth left gate clock L_SCCLK(n) and the nth right gate clock R_SCCLK(n), and the (n+1)th gate clock SCCLK(n+1) can be used when it is not necessary to distinguish between the (n+1)th left gate clock L_SCCLK(n+1) and the (n+1)th right gate clock R_SCCLK(n+1).

[0187] Therefore, the level of the nth left Q node L_Qn can be boosted together with the nth left gate clock L_SCCLK(n) and the (n+1)th left gate clock L_SCCLK(n+1), and thus, the n_1th left pull-up transistor L_Tun_1 and the n_2th left pull-up transistor L_Tun_2 can be turned on.

[0188] Therefore, the (2n-1)th gate pulse GP2n-1 and the 2nth gate pulse GP2n can be sequentially output to the (2n-1)th gate line GL2n-1 and the 2nth gate line GL2n through the nth left pull-up transistor L_Tun.

[0189] In this case, the 2n-1th gate pulse GP2n-1 and the 2nth gate pulse GP2n can be output from the nth right stage R_Stage n using the same method.

[0190] Subsequently, in the third process J, a high-level gate signal GSn+1 can be input as the reset signal for each of the nth left stage L_Stage n and the nth right stage R_Stage n. Therefore, the n_1th left pull-up transistor L_Tun_1 and the n_2th left pull-up transistor L_Tun_2 can be turned off.

[0191] In this case, the n_1st right pull-up transistor R_Tun_1 and the n_2nd right pull-up transistor R_Tun_2 can also be turned off.

[0192] Subsequently, in the third process J, the (n+1)th right ripple clock R_DCLK(n+1) with a high level can be input from the (n+1)th right stage R_Stage n+1 to the nth right Qb node R_Qbn. Therefore, the (2n-1)th right gate cutoff signal R_Goff2n-1_1st can be output from the nth right stage R_Stage n to the (2n-1)th gate line GL2n-1. The (2n-1)th right gate cutoff signal R_Goff2n-1_1st can be configured as the (2n-1)th right gate cutoff signal.

[0193] In this configuration, the (n-1)th right ripple clock R_DCLK(n-1) with a high level can be input from the (n-1)th right stage R_Stage n-1 to the (n_2)th right Qb node R_Qbn_2. Therefore, the 2n_1st right gate cutoff signal R_Goff2n_1st can be output from the nth right stage R_Stage n to the 2nth gate line GL2n. The 2n_1st right gate cutoff signal R_Goff2n_1st can be configured as the 2nth right gate cutoff signal.

[0194] In this case, since the nth left-side ripple clock L_DCLK(n) with a low level is supplied to the nth left-side stage R_Stage n, the gate cutoff signal does not need to be output from the nth left-side stage R_Stage n.

[0195] Subsequently, in the fourth process K, the nth left-side ripple clock L_DCLK(n) with a high level can be input to the nth left-side Qb node L_Qbn. Therefore, the 2n-1_2nd left-side gate cutoff signal L_Goff2n-1_2nd can be output from the nth left-side R_Stage n to the (2n-1)th gate line GL2n-1. The 2n-1_2nd left-side gate cutoff signal L_Goff2n-1_2nd can configure the (2n-1)th left-side gate cutoff signal.

[0196] In this case, the 2n_2nd left gate cutoff signal L_Goff2n_2nd can be output from the nth left stage R_Stage n to the 2nth gate line GL2n. The 2n_2nd left gate cutoff signal L_Goff2n_2nd can be configured as the 2nth left gate cutoff signal.

[0197] In this scenario, a low level can be continuously supplied to the nth left Q node L_Qn. However, the nth left gate clock L_SCCLK(n) and the (n+1)th left gate clock L_SCCLK(n+1), both of which are high, may be sequentially input to the first terminals of the n_1th left pull-up transistor L_Tun_1 and the n_2th left pull-up transistor L_Tun_2. Therefore, ripple may occur in the nth left Q node L_Qn due to the nth left gate clock L_SCCLK(n) and the (n+1)th left gate clock L_SCCLK(n+1), both of which are high.

[0198] In this case, since the high-level nth left ripple clock L_DCLK(n) is supplied to the nth left Qb node L_Qbn, the nth left ripple transistor L_Trpn can be turned on. Therefore, the ripple appearing in the nth left Q node L_Qn can be released through the nth left ripple transistor L_Trpn to the terminal supplied with a low voltage GVSS.

[0199] In this case, the nth right ripple transistor R_Trpn can be driven using the same method as the nth left ripple transistor L_Trpn. Therefore, the ripple appearing in the nth right Q node R_Qn can be released to the terminal supplied with a low voltage GVSS through the nth right ripple transistor R_Trpn.

[0200] Subsequently, in the fifth process L, the (n+1)th right ripple clock R_DCLK(n+1) with a high level can be input from the (n+1)th right stage R_Stage n+1 to the (n_1)th right Qb node R_Qbn_1. Therefore, the (2n-1)th right gate cutoff signal R_Goff2n-1_3rd can be output from the nth right stage R_Stage n to the (2n-1)th gate line GL2n-1. The (2n-1)th right gate cutoff signal R_Goff2n-1_3rd can configure the (2n-1)th right gate cutoff signal.

[0201] In this configuration, the (n-1)th right ripple clock R_DCLK(n-1) with a high level can be input from the (n-1)th right stage R_Stage n-1 to the (n_2)th right Qb node R_Qbn_2. Therefore, the 2n_3rd right gate cutoff signal R_Goff2n_3rd can be output from the nth right stage R_Stage n to the 2nth gate line GL2n. The 2n_3rd right gate cutoff signal R_Goff2n_3rd can be configured as the 2nth right gate cutoff signal.

[0202] Finally, in the sixth process M, the nth left ripple clock L_DCLK(n) with a high level can be input to the nth left Qb node L_Qbn.

[0203] Therefore, the left gate cutoff signal L_Goff2n-1_4th can be output from the nth left stage L_Stage n to the (2n-1)th gate line GL2n-1. The left gate cutoff signal L_Goff2n-1_4th can be configured with the (2n-1)th gate cutoff signal.

[0204] Furthermore, a 2n_4th left gate cutoff signal L_Goff2n_4th can be output from the nth left stage to the 2nth gate line GL2n. The 2n_4th left gate cutoff signal L_Goff2n_4th can be configured as a 2n left gate cutoff signal.

[0205] In this scenario, a low level can be continuously supplied to the nth left Q node L_Qn. However, the nth left gate clock L_SCCLK(n) with a high level may be input to the first terminal of the n_1th left pull-up transistor L_Tun_1, and the (n+1)th left gate clock L_SCCLK(n+1) with a high level may be input to the first terminal of the n_2th left pull-up transistor L_Tun_2. Therefore, ripple may occur in the nth left Q node L_Qn due to the nth left gate clock L_SCCLK(n) and the (n+1)th left gate clock L_SCCLK(n+1) both having high levels.

[0206] In this case, because the high-level nth left ripple clock L_DCLK(n) is supplied to the nth left Qb node L_Qbn, the nth left ripple transistor L_Trpn can be turned on. Therefore, the ripple appearing in the nth left Q node L_Qn can be released through the nth left ripple transistor L_Trpn to the terminal supplied with a low voltage GVSS.

[0207] In this case, the nth right ripple transistor R_Trpn can be driven using the same method as the nth left ripple transistor L_Trpn. Therefore, the ripple appearing in the nth right Q node R_Qn can be released to the terminal supplied with a low voltage GVSS through the nth right ripple transistor R_Trpn.

[0208] The third process J to the sixth process M can be repeated until another nth gate pulse is output from the nth left stage L_Stage n and the nth right stage R_Stage n. Therefore, the 2n-1th gate cutoff signal can be continuously output to the 2n-1th gate line GL2n-1, and the 2nth gate cutoff signal can be continuously output to the 2nth gate line GL2n.

[0209] In this case, the 2n-1_1 right gate cutoff signal R_Goff2n-1_1st, the 2n-1_3 right gate cutoff signal R_Goff2n-1_3rd, the 2n-1_2 left gate cutoff signal L_Goff2n-1_2nd, and the 2n-1_4 left gate cutoff signal L_Goff2n-1_4th can be configured with the 2n-1 gate cutoff signal, which is supplied to the 2n-1 gate line.

[0210] In other words, the nth left stage L_Stage n and the nth right stage R_Stage n can sequentially output the (2n-1)th gate cutoff signal to the (2n-1)th gate line GL2n-1. Therefore, the (2n-1)th gate cutoff signal can be continuously output to the (2n-1)th gate line GL2n-1.

[0211] In this case, the 2n_1 right gate cutoff signal R_Goff2n_1st, the 2n_3 right gate cutoff signal R_Goff2n_3rd, the 2n_2 left gate cutoff signal L_Goff2n_2nd, and the 2n_4 left gate cutoff signal L_Goff2n_4th can be configured to provide a 2n gate cutoff signal, which is supplied to the 2n gate line.

[0212] In other words, the nth left stage L_Stage n and the nth right stage R_Stage n can sequentially output the 2nth gate cutoff signal to the 2nth gate line GL2n. Therefore, the 2nth gate cutoff signal can be continuously output to the 2nth gate line GL2n.

[0213] In this case, the nth left ripple transistor L_Trpn, which is set in the nth left stage L_Stage n to remove the ripple appearing in the nth left Q node L_Qn of the nth left stage L_Stage n, and the nth right ripple transistor R_Trpn, which is set in the nth right stage R_Stage n to remove the ripple appearing in the nth right Q node R_Qn of the nth right stage R_Stage n, can perform turn-on and turn-off operations simultaneously and continuously.

[0214] Since each of the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn repeatedly performs turn-on and turn-off operations, the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn do not degrade, and the rate of degradation of the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn can be reduced. Therefore, the reliability of the display device including the nth left ripple transistor L_Trpn and the nth right ripple transistor R_Trpn according to this disclosure can be improved.

[0215] According to this disclosure, the ripple transistor used to remove ripple appearing in the Q node can repeatedly perform turn-on and turn-off operations based on a ripple clock. Therefore, degradation of the ripple transistor can be prevented, and thus the reliability of the display device can be improved.

[0216] According to this disclosure, the phase of the gate clock supplied to the pull-up transistor connected to the Q node can be the same as the phase of the ripple clock used to drive the ripple transistor. Therefore, even when the gate clock is supplied to the pull-up transistor, abnormal signals caused by ripple will not be supplied to the Q node. Thus, the pull-up transistor connected to the Q node will not operate abnormally, thereby improving the reliability of the display device.

[0217] According to this disclosure, since gate cutoff signals are alternately output from two stages disposed on both sides of the gate line, a gate cutoff signal can be continuously supplied to the gate line. Therefore, the gate line will not be floating, and consequently, the switching transistor connected to the gate line will not be abnormally driven. Thus, the reliability of the display device can be improved.

[0218] The features, structures, and effects described above in this disclosure are included in at least one embodiment of this disclosure, but are not limited to only one embodiment. Furthermore, those skilled in the art can implement the features, structures, and effects described in at least one embodiment of this disclosure through combinations or modifications of other embodiments. Therefore, any content associated with combinations and modifications should be interpreted as being within the scope of this disclosure.

[0219] It will be apparent to those skilled in the art that various modifications and variations may be made to this disclosure without departing from the spirit or scope thereof. Therefore, this disclosure is intended to cover modifications and variations thereof, provided that such modifications and variations fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A display panel, the display panel including a display area and a non-display area surrounding the display area and including gate lines; A left gate driver is disposed in a first non-display area of ​​the non-display area to output a left gate pulse and a left gate cutoff signal to the gate line; as well as A right gate driver, disposed in a second non-display region of the non-display area, outputs a right gate pulse and a right gate cutoff signal to the gate line. The left gate driver includes an nth left stage that outputs the nth left gate pulse, and the right gate driver includes an nth right stage that outputs the nth right gate pulse, where n is a natural number. The output of the nth left gate pulse and the output of the nth right gate pulse are controlled by the nth left Q node included in the nth left stage and the nth right Q node included in the nth right stage. The nth left ripple transistor, configured in the nth left stage to remove ripple appearing in the nth left Q node of the nth left stage, and the nth right ripple transistor, configured in the nth right stage to remove ripple appearing in the nth right Q node of the nth right stage, repeatedly perform turn-on and turn-off operations, and Specifically, the nth left gate cutoff signal output from the nth left stage and the nth right gate cutoff signal output from the nth right stage are alternately output to the nth gate line.

2. The display device according to claim 1, wherein, The phase of the nth left gate clock supplied to the nth left stage to generate the nth left gate pulse is the same as the phase of the nth left ripple clock supplied to drive the nth left ripple transistor, and The phase of the nth right gate clock supplied to the nth right stage to generate the nth right gate pulse is the same as the phase of the nth right ripple clock supplied to drive the nth right ripple transistor.

3. The display device according to claim 1, wherein, The phase of the nth left ripple clock supplied to drive the nth left ripple transistor is the same as the phase of the nth right ripple clock supplied to drive the nth right ripple transistor.

4. The display device according to claim 1, wherein, The first terminal of the nth left ripple transistor is connected to the nth left Q node, the second terminal of the nth left ripple transistor is connected to the first voltage terminal, and the gate of the nth left ripple transistor is connected to the gate of the nth left pull-down transistor. The nth left pull-down transistor controls the output of the nth left gate cutoff signal. The first terminal of the nth right ripple transistor is connected to the nth right Q node, the second terminal of the nth right ripple transistor is connected to the first voltage terminal, and the gate of the nth right ripple transistor is connected to the terminal supplied with the nth right ripple clock.

5. The display device according to claim 4, wherein, The phase of the nth left gate clock supplied to the nth left stage to generate the nth left gate pulse is the same as the phase of the nth left ripple clock supplied to drive the nth left ripple transistor, and The phase of the nth right gate clock supplied to the nth right stage to generate the nth right gate pulse is the same as the phase of the nth right ripple clock supplied to the gate of the nth right ripple transistor.

6. The display device according to claim 4, wherein, The nth left ripple clock is supplied to the gate of the nth left ripple transistor. The nth right-hand ripple clock is supplied to the gate of the nth right-hand ripple transistor, and The phase of the nth left ripple clock is the same as the phase of the nth right ripple clock.

7. The display device according to claim 4, wherein, The gate of the nth left ripple transistor is connected to the gate of the nth left pull-down transistor, and the nth left pull-down transistor controls the output of the nth left gate cutoff signal. The gate of the nth right ripple transistor is not connected to the gate of the nth right pull-down transistor, and the nth right pull-down transistor controls the output of the nth right gate cutoff signal.

8. The display device according to claim 7, wherein, The gate of the nth right pull-down transistor is connected to the gate of the (n+1)th right ripple transistor included in the (n+1)th right stage.

9. The display device according to claim 1, wherein, When the nth left-hand ripple transistor is turned on, the nth left-hand gate cutoff signal is output from the nth left-hand stage to the nth gate line, and When the nth right ripple transistor is turned off, the nth right gate cutoff signal is output from the nth right stage to the nth gate line.

10. The display device according to claim 1, wherein, The outputs of the nth left gate cutoff signal and the nth right gate cutoff signal are controlled by the nth left Qb node included in the nth left stage and the nth right Qb node included in the nth right stage. The gate of the nth left ripple transistor and the nth left Qb node included in the nth left stage are connected to each other, and The nth right Qb node included in the nth right stage is connected to the gate of the (n+1)th right ripple transistor included in the (n+1)th right stage.

11. A display device, comprising: A display panel, the display panel including a display area and a non-display area surrounding the display area and including gate lines; A left gate driver is disposed in a first non-display area of ​​the non-display area to output a left gate pulse and a left gate cutoff signal to the gate line; as well as A right gate driver, disposed in a second non-display region of the non-display area, outputs a right gate pulse and a right gate cutoff signal to the gate line. The left gate driver includes an nth left stage that outputs the nth left gate pulse, and the right gate driver includes an nth right stage that outputs the nth right gate pulse, where n is a natural number. The output of the nth left gate pulse and the output of the nth right gate pulse are controlled by the nth left Q node included in the nth left stage and the nth right Q node included in the nth right stage. The nth left ripple transistor, configured in the nth left stage to remove ripple appearing in the nth left Q node of the nth left stage, and the nth right ripple transistor, configured in the nth right stage to remove ripple appearing in the nth right Q node of the nth right stage, repeatedly perform turn-on and turn-off operations, and The nth left stage includes: an nth left signal generator, which includes the nth left ripple transistor; and an nth left signal output unit, which outputs an nth left gate cutoff signal and the nth left gate pulse based on the nth left control signal generated by the nth left signal generator. The nth right stage includes: an nth right signal generator, the nth right signal generator including the nth right ripple transistor; and an nth right signal output unit, the nth right signal output unit outputting an nth right gate cutoff signal and the nth right gate pulse based on an nth right control signal generated by the nth right signal generator, and The nth left gate cutoff signal and the nth right gate cutoff signal are output alternately.

12. The display device according to claim 11, wherein, The nth left signal output unit includes an nth left pull-up transistor that outputs the nth left gate pulse, the gate of the nth left pull-up transistor being connected to the nth left Q node, and The nth right signal output unit includes an nth right pull-up transistor that outputs the nth right gate pulse, and the gate of the nth right pull-up transistor is connected to the nth right Q node.

13. The display device according to claim 12, wherein, The nth left signal output unit includes an nth left pull-down transistor that outputs the nth left gate cutoff signal. The gate of the nth left pull-down transistor is connected to the gate of the nth left ripple transistor. The nth right signal output unit includes an nth right pull-down transistor that outputs the nth right gate cutoff signal, and the gate of the nth right pull-down transistor is connected to the gate of the (n+1)th right ripple transistor included in the (n+1)th right stage.

14. The display device according to claim 13, wherein, The nth left signal output unit further includes an n-2nd left pull-up transistor, the gate of which is connected to the nth left Q node, where g is an even number and n is a natural number g / 2. The nth right signal output unit further includes an n-2nd right pull-up transistor, the gate of which is connected to the nth right Q node.

15. The display device according to claim 14, wherein, The nth left signal output unit also includes an nth (2)th left pull-down transistor connected to the nth (2)th left pull-up transistor. The gate of the n-2nd left pull-down transistor is connected to the gate of the nth left ripple transistor. The nth right signal output unit further includes an nth (2)th right pull-down transistor connected to the n-2nd right pull-up transistor, and The gate of the n-2nd right pull-down transistor is connected to the gate of the (n-1)th right ripple transistor included in the (n-1)th right stage.

16. A display device, comprising: A display panel, the display panel including a display area and a non-display area surrounding the display area and including gate lines; A left gate driver is disposed in a first non-display area of ​​the non-display area to output a left gate pulse and a left gate cutoff signal to the gate line; as well as A right gate driver, disposed in a second non-display region of the non-display area, outputs a right gate pulse and a right gate cutoff signal to the gate line. The left gate driver includes an nth left stage that outputs the nth left gate pulse, and the right gate driver includes an nth right stage that outputs the nth right gate pulse, where n is a natural number. The output of the nth left gate pulse and the output of the nth right gate pulse are controlled by the nth left Q node included in the nth left stage and the nth right Q node included in the nth right stage. The nth left ripple transistor, configured in the nth left stage to remove ripple appearing in the nth left Q node of the nth left stage, and the nth right ripple transistor, configured in the nth right stage to remove ripple appearing in the nth right Q node of the nth right stage, repeatedly perform turn-on and turn-off operations. Specifically, when the nth left-side ripple transistor is turned on, the nth left-side gate cutoff signal is output from the nth left-side stage to the nth gate line, and When the nth right ripple transistor is turned off, the nth right gate cutoff signal is output from the nth right stage to the nth gate line.

Images