Circuit structure, chip and module of radiation hardened latch based on polarity reinforcement

Abstract

The application relates to a circuit structure, a chip and a module of a polar reinforcement-based anti-radiation latch. The circuit structure comprises a multiple-input C unit, a transmission gate, two SRAM units and two transmission units. The second SRAM unit is symmetrically structured with the first SRAM unit and is cross-coupled to form storage nodes S0-S7. When WL is low, internal data is connected to an output port Q through the multiple-input C unit. When WL is high, data is transmitted through a direct transmission path of the transmission gate. Storage nodes S0, S3, S4 and S7 are input by a D input signal through the first transmission unit, and storage nodes S1, S2, S5 and S6 are input by a DN input signal through the second transmission three-input. The application adopts a transmission gate fast input, reduces transmission delay and power consumption of the latch, and shields voltage fluctuation generated by internal nodes through the multiple-input C unit, so that the Q signal cannot be flipped, and the application has higher anti-SEU, DNU and TNU capabilities.

Description

Technical Field

[0001] This invention relates to a circuit structure of a latch, and more particularly to a circuit structure of a polarity-hardened radiation-resistant latch, a circuit chip of a polarity-hardened radiation-resistant latch, and a circuit module of a polarity-hardened radiation-resistant latch. Background Technology

[0002] With the continuous advancement of Complementary Metal Oxide Semiconductor (CMOS) technology, electronic devices are becoming increasingly smaller and more integrated. Factors such as the space radiation environment in which they operate further impact device stability. Furthermore, the use of lower supply voltages to reduce energy loss poses a significant challenge to device stability. Single-event effects can cause both hard and soft errors in electronic devices. Hard errors can lead to physical-level damage, resulting in catastrophic consequences. Soft errors primarily affect the operating state of electronic devices, preventing them from transmitting correct information. Because the energy of space radiation particles is limited, the probability of them causing soft errors is far greater than that of causing hard errors. Among soft errors, Single Event Upsets (SEUs) are far more likely to occur than other types of errors.

[0003] To improve the SEU (Single Event Flip) resistance of a circuit, the following three principles must be followed when designing circuits for SEU resistance. First, information must be stored in two different locations. This provides redundant nodes, which can serve as a source of data recovery if one node experiences a SEU. Second, the feedback from undamaged stored data bits after a particle impact must ensure data recovery from errors. Finally, the current caused by the particle impact should diffuse from the N-type to the P-type. While existing latches possess SEU and even DNU (Dual Event Flip) resistance capabilities, they are insufficient against TNU (Turning Event Flip), and achieving SEU and DNU resistance in latches increases power consumption. Summary of the Invention

[0004] Therefore, it is necessary to provide a circuit structure, chip, and module for a radiation-resistant latch based on polarity hardening, which addresses the problems of insufficient TNU resistance and high power consumption of existing latches.

[0005] The present invention is achieved through the following technical solution: a circuit structure of a polarity-hardened radiation-resistant latch includes a multi-input C unit, a transmission gate, two SRAM units and two transmission units.

[0006] The second SRAM cell is symmetrically structured and cross-coupled with the first SRAM cell, forming memory nodes S0 to S7. One end of the multi-input C cell is electrically connected to memory nodes S1, S2, S5, and S6, and the other end is electrically connected to the output port Q. The transmission gates include PMOS transistor P17 and NMOS transistor N25. The gate of P17 is controlled by the word line WLB. The gate of N25 is controlled by the word line WL. One end of the transmission gate is electrically connected to the output port Q, and the other end is electrically connected to node D. One end of the first transmission unit is electrically connected to memory nodes S0, S3, S4, and S7, and the other end is electrically connected to node D. The first transmission unit is controlled by the word line WL. One end of the second transmission unit is electrically connected to memory nodes S1, S2, S5, and S6, and the other end is electrically connected to node DN. The second transmission unit is also controlled by the word line WL.

[0007] In data transmission mode, the word line WL of the latch is high, and both the first and second transmission units are enabled. If the initial stored data of the latch is "1", i.e., storage nodes S0 = S3 = S4 = S7 = "1" and storage nodes S1 = S2 = S5 = S6 = "0", and if the node D signal is low at this time, i.e., the data "0" is transmitted to the unit, the signal transmits a low-level signal to the internal nodes S0S3S4S7 through the first transmission unit, and a high-level signal to the internal nodes S1S2S5S6 through the second transmission unit. The value of the internal nodes becomes S0 = S3 = S4 = S7 = "0" and S1 = S2 = S5 = S6 = "1". At the same time, the transmission gate opens, and the input of the latch is directly transmitted to the output port Q through the transmission gate.

[0008] The circuit structure of the polarity-hardened radiation-resistant latch described above has basic data transmission and hold functions. The input of the latch is quickly transmitted to the output port Q via a transmission gate, significantly reducing the latch's transmission delay and power consumption. The data stored in the latch circuit at this time is the "0" input from the D signal. Through the multi-input C unit connected to the internal nodes of the latch, voltage fluctuations generated by the internal nodes can be effectively shielded, preventing Q signal flipping and providing high resistance to SEU, DNU, and TNU.

[0009] In one embodiment, when the latch is in data holding state, the word line WL is low, the first transmission unit, the second transmission unit, and the transmission gate are all closed, and the data stored in the latch is output to the output port Q through the multi-input C unit, and the output of the multi-input C unit is high level "1".

[0010] In one embodiment, the first SRAM cell includes PMOS transistors P1-P6 and NMOS transistors N1-N10. P1 and P2 act as pull-up transistors, and N1 and N2 act as pull-down transistors, forming memory node S0. P3 and N3 act as pull-up transistors, and N4 and N5 act as pull-down transistors, forming memory node S2. P4 and N6 act as pull-up transistors, and N7 and N8 act as pull-down transistors, forming memory node S3. P5 and P6 act as pull-up transistors, and N9 and N10 act as pull-down transistors, forming memory node S3. Furthermore, the gates of N4, N6, and N10 are controlled by memory node S0. The gates of N2, N3, and N7 are controlled by memory node S1. The gates of N1, N8, and P4 are controlled by memory node S2. The gates of N5, N9, and P3 are controlled by memory node S3. The gate of P6 is controlled by memory node S4. The gate of P2 is controlled by memory node S5. The gate of P1 is controlled by memory node S6. The gate of P5 is controlled by memory node S7. The sources or drains of P1, P3, P4, and P5 are electrically connected to the power supply VDD. The sources or drains of N2, N5, N8, and N10 are electrically grounded.

[0011] In one embodiment, the second SRAM cell includes PMOS transistors P7-P12 and NMOS transistors N11-N20. P7 and P8 act as pull-up transistors, and N11 and N12 act as pull-down transistors, forming memory node S4. P9 and N13 act as pull-up transistors, and N14 and N15 act as pull-down transistors, forming memory node S6. P10 and N16 act as pull-up transistors, and N17 and N18 act as pull-down transistors, forming memory node S7. P11 and P12 act as pull-up transistors, and N19 and N20 act as pull-down transistors, forming memory node S5. Furthermore, the gates of N14, N16, and N20 are controlled by memory node S4. The gates of N12, N13, and N17 are controlled by memory node S5. The gates of N11, N18, and P10 are controlled by memory node S6. The gates of N15, N19, and P9 are controlled by memory node S7. The gate of P12 is controlled by memory node S0. The gate of P8 is controlled by memory node S1. The gate of P7 is controlled by memory node S2. The gate of P11 is controlled by memory node S3. The source or drain of P7, P9, P10, and P11 is electrically connected to the power supply VDD. The source or drain of N12, N15, N18, and N20 is electrically grounded.

[0012] In one embodiment, the multi-input C unit includes PMOS transistors P13-P16 and NMOS transistors N21-N24. The gates of P16 and N21 are electrically connected to memory node S1. P15 and N22 are electrically connected to memory node S2. P14 and N23 are electrically connected to memory node S5. P13 and N24 are electrically connected to memory node S6. P13-P16 and N21-N24 are sequentially electrically connected to output port Q.

[0013] In one embodiment, the first transmission unit includes NMOS transistors N26 to N29. The gates of N26, N27, N28, and N29 are electrically connected to word lines WL, respectively. Each of N26, N27, N28, and N29 has one end electrically connected to node D, and the other end is sequentially electrically connected to memory nodes S0, S3, S4, and S7.

[0014] In one embodiment, the second transmission unit includes NMOS transistors N30 to N33. The gates of N30, N31, N32, and N33 are electrically connected to word lines WL, respectively. Each of N30, N31, N32, and N33 has one end electrically connected to node DN, and the other end is sequentially electrically connected to memory nodes S1, S2, S5, and S6.

[0015] This invention also provides a circuit chip based on a polarity-hardened radiation-hardened latch. This circuit chip is packaged using the aforementioned circuit structure of a polarity-hardened radiation-hardened latch and includes seven pins. The first pin is electrically connected to the transmission gate, the first transmission unit, and the second transmission unit via word line WL. The second pin is electrically connected to the transmission gate via word line WLB. The third pin is electrically connected to the transmission gate and the first transmission unit via node D. The fourth pin is electrically connected to the second transmission unit via node DN. The fifth pin is electrically connected to the transmission gate and the multi-input C unit via output port Q. The sixth pin is electrically connected to the first SRAM unit, the second SRAM unit, and the multi-input C unit via power supply VDD. The seventh pin is electrically connected to the first SRAM unit, the second SRAM unit, and the multi-input C unit via ground.

[0016] In one embodiment, word line WL is electrically connected to the gates of N25 to N33, and then electrically connected to a first pin. Word line WLB is electrically connected to the gate of P17, and then electrically connected to a second pin.

[0017] This invention also provides a circuit module for a polarity-hardened radiation-resistant latch. This circuit module adopts the circuit structure layout of the aforementioned polarity-hardened radiation-resistant latch and includes seven connection terminals. Specifically, the word line WL is electrically connected to the transmission gate, the first transmission unit, and the second transmission unit, thus leading to the first connection terminal. The word line WLB is electrically connected to the transmission gate, thus leading to the second connection terminal. Node D is electrically connected to the transmission gate and the first transmission unit, thus leading to the third connection terminal. Node DN is electrically connected to the second transmission unit, thus leading to the fourth connection terminal. The output port Q is electrically connected to the transmission gate and the multi-input C unit, thus leading to the fifth connection terminal. The power supply VDD is electrically connected to the first SRAM unit, the second SRAM unit, and the multi-input C unit, thus leading to the sixth connection terminal. The ground line is electrically connected to the first SRAM unit, the second SRAM unit, and the multi-input C unit, thus leading to the seventh connection terminal.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The polarity-hardened radiation-resistant latch of this invention has basic data transmission and hold functions. The input of the latch is quickly transmitted to the output port Q via a transmission gate, greatly reducing the latch's transmission delay and power consumption. The data stored in the latch circuit at this time is the "0" input by the D signal. Through a multi-input C unit connected to the internal nodes of the latch, voltage fluctuations generated by the internal nodes can be effectively shielded, preventing Q signal flipping and providing high resistance to SEU, DNU, and TNU. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the circuit structure of the polarity-hardened radiation-resistant latch according to Embodiment 1 of the present invention;

[0021] Figure 2 for Figure 1 Timing waveforms of a polarity-hardened radiation-resistant latch circuit structure resisting single-particle bombardment and two-node bombardment.

[0022] Figure 3 for Figure 1 Timing waveform diagram of the anti-three-node flip-flop circuit structure based on polarity-hardened radiation-resistant latch;

[0023] Figure 4 To adopt Figure 1 A schematic diagram of a circuit chip packaged with a polarity-hardened radiation-resistant latch. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0027] Example 1

[0028] Please see Figure 1 This is a schematic diagram of the circuit structure of the polarity-hardened radiation-resistant latch according to Embodiment 1 of the present invention. The circuit structure of the polarity-hardened radiation-resistant latch includes a multi-input C unit, a transmission gate, two SRAM units, and two transmission units.

[0029] Two identical SRAM cells are cross-coupled, forming the basic circuit structure of a polarity-hardened radiation-resistant latch (LPDL). Each SRAM cell has four internal nodes, and the latch has eight internal nodes S0 to S7. Internal nodes S2, S3, S6, and S7 are polarity-hardened using NMOS transistors. When WL is low, internal data is connected to the output port Q through a multi-input C cell. Internal nodes S1, S2, S5, and S6 output data to Q through the multi-input C cell, storing the data at the output port. When WL is high, a direct transmission path for the transmission gate is added to reduce propagation delay. The transmission gate consists of an NMOS transmission transistor N25 and a PMOS transmission transistor P17, which transmits data to Q simultaneously with the input signal D. Internal storage nodes S0, S3, S4, and S7 are input via the D input signal through the NMOS transmission transistor controlled by WL. Internal storage nodes S1, S2, S5, and S6 are input via the DN input signal through the NMOS transmission transistor controlled by WL.

[0030] Two SRAM cells are symmetrically arranged, denoted as the first SRAM cell and the second SRAM cell, respectively. The first SRAM cell includes six PMOS transistors P1–P6 and ten NMOS transistors N1–N10. The specific connection relationship of the first SRAM cell is as follows:

[0031] The pull-up transistors of memory node S0 are PMOS transistors P1 and P2, and the pull-down transistors are NMOS transistors N1 and N2. The gate of the pull-up PMOS transistor P1 is controlled by internal node S6, the gate of the pull-up PMOS transistor P2 is controlled by internal node S5, the gate of the pull-down NMOS transistor N1 is controlled by internal node S2, and the gate of the pull-down NMOS transistor N2 is controlled by internal node S1.

[0032] The S2 memory node has two pull-up transistors: PMOS P3 and NMOS N3, and two pull-down transistors: NMOS N4 and N5. The gates of the pull-up PMOS P3 and pull-down NMOS N5 are controlled by internal node S3, the gate of the pull-up NMOS N3 is controlled by internal node S1, and the gate of the pull-down NMOS N4 is controlled by internal node S0.

[0033] The S3 memory node has two pull-up transistors: PMOS P4 and NMOS N6, and two pull-down transistors: NMOS N7 and N8. The gates of the pull-up PMOS P4 and pull-down NMOS N8 are controlled by internal node S2, the gate of the pull-up NMOS N6 is controlled by internal node S0, and the gate of the pull-down NMOS N7 is controlled by internal node S1.

[0034] The S1 memory node uses PMOS transistors P5 and P6 as pull-up transistors and NMOS transistors N9 and N10 as pull-down transistors. The gate of the pull-up PMOS transistor P5 is controlled by internal node S7, the gate of the pull-up PMOS transistor P6 is controlled by internal node S4, the gate of the pull-down NMOS transistor N9 is controlled by internal node S3, and the gate of the pull-down NMOS transistor N2 is controlled by internal node S0.

[0035] The second SRAM cell includes six PMOS transistors P7 to P12 and ten NMOS transistors N11 to N20. The specific connection relationship of the second SRAM cell is as follows:

[0036] The S4 memory node uses PMOS transistors P7 and P8 as pull-up transistors and NMOS transistors N11 and N12 as pull-down transistors. The gate of the pull-up PMOS transistor P7 is controlled by internal node S2, the gate of the pull-up PMOS transistor P8 is controlled by internal node S1, the gate of the pull-down NMOS transistor N11 is controlled by internal node S6, and the gate of the pull-down NMOS transistor N12 is controlled by internal node S5.

[0037] The S6 memory node uses PMOS transistor P9 and NMOS transistor N13 as pull-up transistors and NMOS transistors N14 and N15 as pull-down transistors. The gates of the pull-up PMOS transistor P9 and the pull-down NMOS transistor N15 are controlled by internal node S7, the gate of the pull-up NMOS transistor N13 is controlled by internal node S5, and the gate of the pull-down NMOS transistor N14 is controlled by internal node S4.

[0038] The S7 memory node uses PMOS transistor P10 and NMOS transistor N16 as pull-up transistors and NMOS transistors N17 and N18 as pull-down transistors. The gates of the pull-up PMOS transistor P10 and the pull-down NMOS transistor N18 are controlled by internal node S6, the gate of the pull-up NMOS transistor N16 is controlled by internal node S4, and the gate of the pull-down NMOS transistor N17 is controlled by internal node S5.

[0039] The S5 memory node uses PMOS transistors P11 and P12 for pull-up and NMOS transistors N19 and N20 for pull-down. The gate of the pull-up PMOS transistor P11 is controlled by internal node S3, the gate of the pull-up PMOS transistor P12 is controlled by internal node S0, the gate of the pull-down NMOS transistor N19 is controlled by internal node S7, and the gate of the pull-down NMOS transistor N20 is controlled by internal node S4.

[0040] The specific connection relationship of the transmission gates is as follows: the gate of P17 is controlled by word line WLB, and the gate of N25 is controlled by word line WL. One end of the source and drain of P17 and N25 is electrically connected to node D, and the other end is electrically connected to node Q.

[0041] The multi-input C cell includes PMOS transistors P13-P16 and NMOS transistors N21-N24. The gates of P16 and N21 are electrically connected to storage node S1. The gates of P15 and N22 are electrically connected to storage node S2. The gates of P14 and N23 are electrically connected to storage node S5. The gates of P13 and N24 are electrically connected to storage node S6. P13-P16 and N21-N24 are sequentially electrically connected to the output port Q.

[0042] The first transmission unit includes NMOS transistors N26 to N29. The gates of N26, N27, N28, and N29 are electrically connected to word lines WL, respectively. Each of N26, N27, N28, and N29 has one end electrically connected to node D, and the other end is sequentially electrically connected to memory nodes S0, S3, S4, and S7.

[0043] The second transmission unit includes NMOS transistors N30 to N33. The gates of N30, N31, N32, and N33 are electrically connected to word lines WL, respectively. Each of N30, N31, N32, and N33 has one end electrically connected to node DN, and the other end is sequentially electrically connected to memory nodes S1, S2, S5, and S6.

[0044] In this embodiment, the specific connection relationship of the latch is as follows:

[0045] In the first SRAM cell, the sources of P1, P3, P4, and P5 are electrically connected to the power supply VDD. The drains of P1 and P2 are electrically connected, as are the drains of P3 and N3, P4 and N6, and P5 and P6. The drains of N1 and N2 are electrically connected, as are the drains of N4 and N5, N7 and N8, and N9 and N10. The sources of N2, N5, N8, and N10 are electrically grounded. The sources of N1 and P2 are electrically connected to the gates of N4, N6, and N10, forming memory node S0. The gates of N2, N3, and N7 are electrically connected to the sources of P6 and N9, forming memory node S1. The sources of N3 and N4 are electrically connected to the gates of N1, P4, and N8, forming memory node S2. The gates of P3, N5, and N9 are electrically connected to the sources of N6 and N7, forming memory node S3. The gate of P6 is electrically connected to memory node S4. The gate of P2 is electrically connected to memory node S5. The gate of P1 is electrically connected to memory node S6. The gate of P5 is electrically connected to memory node S7.

[0046] In the second SRAM cell, the sources of P7, P9, P10, and P11 are electrically connected to the power supply VDD. The drains of P7 and P8 are electrically connected, as are the drains of P9 and N13, P10 and N16, and P11 and P12. The drains of N11 and N12 are electrically connected, as are the drains of N14 and N15, N17 and N18, and N19 and N20. The sources of N12, N15, N18, and N20 are electrically grounded. The sources of N11 and P8 are electrically connected to the gates of N14, N16, and N20, forming memory node S4. The gates of N12, N13, and N17 are electrically connected to the sources of P12 and N19, forming memory node S5. The sources of N13 and N14 are electrically connected to the gates of N11, P10, and N18, forming memory node S6. The gates of P9, N15, and N19 are electrically connected to the sources of N16 and N17, forming memory node S7. The gate of P12 is electrically connected to memory node S0. The gate of P8 is electrically connected to memory node S1. The gate of P7 is electrically connected to memory node S2. The gate of P11 is electrically connected to memory node S3.

[0047] In the transmission gate, the gate of N25 is electrically connected to word line WL, and the gate of P17 is electrically connected to word line WLB. The sources of N25 and P17 are electrically connected to form node D, and the drains of N25 and P17 are electrically connected to output interface Q.

[0048] In the multi-input C cell, the source of P13 is electrically connected to the power supply VDD. The drains of P13 and P14 are electrically connected; the sources of P14 and P15 are electrically connected; the drains of P15 and P16 are electrically connected; the sources of P16 and N21 are electrically connected to the output interface Q; the drains of N21 and N22 are electrically connected; the sources of N22 and N23 are electrically connected; the drains of N23 and N24 are electrically connected; and the source of N24 is electrically grounded. The gates of P13 and N24 are electrically connected to memory node S6; the gates of P14 and N23 are electrically connected to memory node S5; the gates of P15 and N22 are electrically connected to memory node S2; and the gates of P16 and N21 are electrically connected to memory node S1.

[0049] In the first transmission unit, the gates of N26, N27, N28, and N29 are electrically connected to word lines WL. The sources of N26, N27, N28, and N29 are electrically connected to node D. The drain of N26 is electrically connected to memory node S0, the drain of N27 is electrically connected to memory node S3, the drain of N28 is electrically connected to memory node S4, and the drain of N29 is electrically connected to memory node S7.

[0050] In the second transmission unit, the gates of N30, N31, N32, and N33 are electrically connected to word lines WL. The sources of N30, N31, N32, and N33 are electrically connected to node DN. The drain of N30 is electrically connected to memory node S1, the drain of N31 is electrically connected to memory node S2, the drain of N32 is electrically connected to memory node S5, and the drain of N33 is electrically connected to memory node S6.

[0051] In other embodiments, the source and drain of each transistor in the LPDL latch can be interchanged, as long as the connection relationship between the transistors is maintained.

[0052] In this embodiment, the PMOS transistors inside the latch (two SRAM cells) have a size of 80nm / 65nm, and the NMOS transistors have a size of 280nm / 65nm. The external input signal D is written to the circuit through four transfer transistors N26-N29, and the input signal D is written through four transfer transistors N30-N33. The external NMOS transfer transistors have a size of 140nm / 65nm. In the multi-input C cell of the latch, both the NMOS and PMOS transistors have a size of 140nm / 65nm. Of course, in other embodiments, the NMOS and PMOS transistors in the latch can be larger or smaller.

[0053] The latch in this embodiment operates as follows:

[0054] 1. When the clock signal WL is high, the eight transmission transistors N26 to N33 controlled by this signal are turned on, and the latch is in data transmission mode (Transparent mode). Internal data is no longer output through the multi-input C unit. Assume the initial stored data of the latch unit is "1", i.e., storage nodes S0 = S3 = S4 = S7 = "1", and storage nodes S1 = S2 = S5 = S6 = "0". In data transmission mode, if the signal at node D is low, i.e., data "0" is transmitted to the unit, the signal transmits a low-level signal to storage nodes S0, S3, S4, and S7 through transmission transistors N26 to N29, and a high-level signal to storage nodes S1, S2, S5, and S6 through transmission transistors N30 to N33. Simultaneously, transistors N1, N2, N3, N7, N8, N11, N12, N13, N17, N18, and P3, P5, P6, P9, P11, and P12 are turned on, while transistors P1, P2, P4, P7, P8, P10, N4, N5, N6, N9, N10, N14, N15, N16, N19, and N20 are turned off. At this point, the values ​​of the internal storage nodes become S0 = S3 = S4 = S7 = "0", and S1 = S2 = S5 = S6 = "1". Simultaneously, under the control of the clock signal WL, the transmission gate opens. Therefore, the latch input is quickly transmitted to the output port Q through the transmission gate, greatly reducing the latch's transmission delay. The data stored in the latch circuit at this time is the "0" input by the D signal. When the latch is bombarded by particles, the data stored in the node will be quickly restored without flipping.

[0055] 2. When the clock signal WL is low, the transmission transistors N26-N33 are turned off, the transmission gate is closed, the channel between input D and output Q is cut off, and the latch LPDL is in hold mode. The feedback loop in the circuit starts working, and the data stored in the latch is output to the Q terminal through the multi-input C unit. At this time, the output of the multi-input C unit is high level "1". When the latch unit is bombarded by particles, the C unit may be in a high-impedance state, which ensures that the correct data is output to the Q terminal, and the internal structure of the circuit also ensures that the data will not be flipped after being bombarded by particles.

[0056] Based on the above analysis, the latch LPDL of this embodiment has basic data transmission and holding functions. Furthermore, through the multi-input C unit connected to the internal nodes of the latch, the voltage fluctuations generated by the internal nodes can be effectively shielded, preventing the Q signal from flipping. In data transmission mode, the input signal can be quickly transmitted to the output signal through a transmission gate.

[0057] Simulation Verification 1

[0058] The LPDL cell was functionally simulated using Cadence circuit simulation software. The simulation conditions were: Corner: TT; Temperature: 27℃; VDD: 1.2V. The resulting timing diagram is shown below. Figure 2 , Figure 3 As shown. Please refer to [the original text]. Figure 2 and Figure 3 , Figure 2 for Figure 1 Timing waveforms of a polarity-hardened radiation-resistant latch circuit structure resisting single-particle bombardment and two-node bombardment. Figure 3 for Figure 1 The timing waveform diagram of the circuit structure based on polarity-hardened radiation-resistant latch, demonstrating resistance to three-node flip-flops. Specifically, Figure 2 The left half of the diagram shows the timing waveforms of the LPDL latch storage circuit under different times and at different nodes when it is subjected to pulse injection from a double exponential current source to resist single-particle bombardment. Figure 2 The right half of the diagram shows the timing waveforms of the LPDL latch storage circuit under different times and different dual-node pairs when subjected to pulse injection from a dual-exponential current source to resist dual-node bombardment.

[0059] As can be seen from the timing diagram, when the clock signal is high, the latch RHPDL circuit completes the data transmission function, and when the clock signal is low, it completes the data retention function.

[0060] Specifically, the LPDL circuit in this embodiment has eight internal storage nodes (S0 to S7), four of which employ a polarity-hardened scheme, meaning nodes S2, S3, S6, and S7 are surrounded by all NMOS transistors. Based on the characteristics of single-event effects in CMOS integrated circuits, the drain terminals of transistors in the off state are sensitive nodes in the circuit. Therefore, polarity-hardened technology is used to reduce the number of sensitive nodes. When the stored data inside the latch is "1", internal storage nodes S0 = S3 = S4 = S7 = "1", storage nodes S1 = S2 = S5 = S6 = "0", and Q = "1". At this time, the sensitive nodes in the circuit include six internal storage nodes S0, S3, S4, S7, S1, and S5, and one output node Q. Nodes S2 and S6 are not sensitive nodes in this case because the data stored in S2 and S6 is "0" and they are hardened by being surrounded by NMOS transistors. They will not generate a voltage pulse from 0 to 1 when bombarded by particles, and therefore will not flip.

[0061] Similarly, for another scenario (internal storage nodes S0 = S3 = S4 = S7 = "0", storage nodes S1 = S2 = S5 = S6 = "1", Q = "0"), the sensitive nodes in the circuit include six internal storage nodes S0, S2, S4, S6, S1, and S5, and one output node Q. Nodes S3 and S7 are not sensitive nodes in this case because the data stored in S3 and S7 is "0" and they are reinforced by NMOS transistors. Therefore, they will not generate a voltage pulse from 0 to 1 when bombarded by particles, and thus will not flip.

[0062] As can be seen from the above analysis, the circuit structure of the latch LPDL in this embodiment can effectively resist single-event upsets, and all sensitive nodes can recover automatically when bombarded by a single event. Figure 2 As can be seen from the left half, all internal sensitive nodes can recover to their initial state after being bombarded by high-energy charged particles, and this will not affect other nodes or the output. After a single-particle bombardment of the output node, only a transient voltage pulse is generated, and the output node remains in the correct state.

[0063] Simulation of LPDL latch anti-dual node flipping as follows Figure 2 As shown, the simulation is implemented by simultaneously injecting error pulses into two sensitive nodes to simulate charge sharing. Figure 2 As can be seen from the right half, the dual-node flipping caused by charge sharing has no effect on the output node of the latch. Furthermore, all dual-node bombardments can recover on their own. And when the internal storage node and the output node are bombarded simultaneously, it manifests as only a transient pulse at the output. Therefore, the LPDL circuit structure has the ability to resist dual-node flipping.

[0064] Simulation of the LPDL latch's resistance to three-node flipping, as shown below Figure 3 As shown, the simulation is implemented by simultaneously injecting error pulses into three sensitive nodes to simulate charge sharing. Figure 3 It can be seen that the three-node flipping caused by charge sharing does not affect the output node of the latch. Although some nodes in node groups S0-S1-S3, S4-S5-S7, S0-S3-S7, and S1-S3-S5 do not return to their original state after the flipping, the latch still maintains the correct output due to the presence of the multi-input C unit. Therefore, the LPDL circuit structure has the ability to resist three-node flipping.

[0065] Simulation Verification 2

[0066] I. Simulation Conditions

[0067] Corner: TT; Temperature: 27℃; VDD: 1.2V.

[0068] II. Simulation Object

[0069] Control group: Existing latch circuits: CLCT, RFC, RHPDL, RHL, FPADRL, ShanshanLiu-latch.

[0070] Experimental group: The LPDL latch in this embodiment.

[0071] III. Simulation Results

[0072] The simulation results are shown in Tables 1 and 2.

[0073] Table 1

[0074] CLCT 57.1 184 RFC 57.4 198 RHPDL 28.3 205 RHL 12.0 58.9 FPADRL 10.8 3120 ShanshanLiu-latch 10.8 38.8 LPDL 27.4 34.08

[0075] Table 2

[0076] CLCT ＜5 RFC ＜5 RHPDL ＜5 RHL 6.6 FPADRL 45 ShanshanLiu-latch >150 LPDL >150

[0077] Table 1 is a comparison table of circuit delay and power consumption between the prior art latch unit circuit and the LPDL radiation-resistant latch memory unit circuit provided in this embodiment. Table 2 is a comparison table of critical charge between the prior art latch memory unit circuit and the LPDL radiation-resistant latch memory unit circuit provided in this embodiment.

[0078] As shown in Table 1, the power consumption of the LPDL radiation-hardened latch in this embodiment is significantly lower than that of the other six existing latch unit circuits. As shown in Table 2, the critical charge of both the LPDL radiation-hardened latch in this embodiment and the critical charge of the Shanshan-Liu-latch unit circuit exceed 150 fC, indicating that the LPDL radiation-hardened latch in this embodiment has high resistance to SEU, DNU, and TNU.

[0079] In summary, the LPDL circuit of this embodiment can improve the memory cell's resistance to SEU, DNU, and TNU, significantly improve radiation resistance while sacrificing a smaller cell area, and reduce cell power consumption and latency.

[0080] Based on the circuit structure of the LPDL radiation-hardened latch described above, this embodiment further provides a circuit chip for a polarity-hardened radiation-hardened latch, which can be packaged using the circuit structure of the LPDL radiation-hardened latch described above.

[0081] Please combine Figure 4 It is adopted Figure 1This is a schematic diagram of a circuit chip packaged based on a polarity-hardened radiation-resistant latch. Specifically, the circuit chip includes 7 pins. Pin 1 is electrically connected to the transmission gate, the first transmission unit, and the second transmission unit via word line WL. Pin 2 is electrically connected to the transmission gate via word line WLB. Pin 3 is electrically connected to the transmission gate and the first transmission unit via node D. Pin 4 is electrically connected to the second transmission unit via node DN. Pin 5 is electrically connected to the transmission gate and the multi-input C unit via output port Q. Pin 6 is electrically connected to the first SRAM unit, the second SRAM unit, and the multi-input C unit via power supply VDD. Pin 7 is electrically connected to the first SRAM unit, the second SRAM unit, and the multi-input C unit via ground.

[0082] In this embodiment, word line WL is electrically connected to the gates of N25 to N33, and then to the first pin 1. Word line WLB is electrically connected to the gate of P17, and then to the second pin 2. Node D is electrically connected to the source of N25 to N29 and the source of P17, and then to the third pin 3. Node DN is electrically connected to the source of N30 to N33, and then to the fourth pin 4. Output port Q is electrically connected to the drain of N25 and P17, and the source of P16 and N21, and then to the fifth pin 5. Power supply VDD is electrically connected to the source of P1, P3, P4, P5, P7, P9, P10, P11, and P13, and then to the sixth pin 6. The ground wire is electrically connected to the sources of N2, N5, N8, N10, N12, N15, N18, N20, and N24, respectively, and then electrically connected to pin 7. Of course, in other embodiments, the source and drain of each of the above transistors can be interchanged, as long as the connection relationship between the transistors is maintained.

[0083] Based on the circuit structure of the LPDL radiation-hardened latch described above, this embodiment further provides a circuit module for a polarity-hardened radiation-hardened latch. This circuit module adopts the circuit structure layout of the LPDL radiation-hardened latch and includes seven connection terminals. Specifically, the word line WL is electrically connected to the transmission gate, the first transmission unit, and the second transmission unit, thus leading to the first connection terminal. The word line WLB is electrically connected to the transmission gate, thus leading to the second connection terminal. Node D is electrically connected to the transmission gate and the first transmission unit, thus leading to the third connection terminal. Node DN is electrically connected to the second transmission unit, thus leading to the fourth connection terminal. The output port Q is electrically connected to the transmission gate and the multi-input C unit, thus leading to the fifth connection terminal. The power supply VDD is electrically connected to the first SRAM unit, the second SRAM unit, and the multi-input C unit, thus leading to the sixth connection terminal. The ground line is electrically connected to the first SRAM unit, the second SRAM unit, and the multi-input C unit, thus leading to the seventh connection terminal.

[0084] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A circuit structure for a radiation-hardened latch based on polarity hardening, characterized in that, It includes: First SRAM cell; The second SRAM cell is symmetrically structured and cross-coupled with the first SRAM cell to form storage nodes S0 to S7. The multi-input C unit has one end electrically connected to the storage nodes S1, S2, S5, and S6, and the other end electrically connected to the output port Q. The transmission gate includes a PMOS transistor P17 and an NMOS transistor N25; the gate of P17 is controlled by word line WLB; the gate of N25 is controlled by word line WL; one end of the transmission gate is electrically connected to the output port Q, and the other end is electrically connected to node D. The first transmission unit has one end electrically connected to the storage nodes S0, S3, S4, and S7 respectively, and the other end electrically connected to the node D; the first transmission unit is controlled by the word line WL. The second transmission unit has one end electrically connected to the storage nodes S1, S2, S5, and S6 respectively, and the other end electrically connected to node DN; the second transmission unit is also controlled by the word line WL. In data transmission mode, the word line WL of the latch is high, and both the first and second transmission units are enabled. If the initial stored data of the latch is "1", i.e., storage nodes S0 = S3 = S4 = S7 = "1" and storage nodes S1 = S2 = S5 = S6 = "0", and if the node D signal is low at this time, i.e., data "0" is transmitted to the unit, the signal transmits a low-level signal to the internal nodes S0S3S4S7 through the first transmission unit and a high-level signal to the internal nodes S1S2S5S6 through the second transmission unit. The value of the internal nodes becomes S0 = S3 = S4 = S7 = "0" and S1 = S2 = S5 = S6 = "1". At the same time, the transmission gate is opened, and the input of the latch is directly transmitted to the output port Q through the transmission gate.

2. The circuit structure of the radiation-resistant latch based on polarity hardening according to claim 1, characterized in that, When the latch is in data holding state, the word line WL is low, the first transmission unit, the second transmission unit, and the transmission gate are all closed, the data stored in the latch is output to the output port Q through the multi-input C unit, and the output of the multi-input C unit is high level "1".

3. The circuit structure of the radiation-resistant latch based on polarity hardening according to claim 1, characterized in that, The first SRAM cell includes PMOS transistors P1 to P6 and NMOS transistors N1 to N10; wherein P1 and P2 are pull-up transistors, and N1 and N2 are pull-down transistors, forming memory node S0; P3 and N3 are pull-up transistors, and N4 and N5 are pull-down transistors, forming memory node S2; P4 and N6 are pull-up transistors, and N7 and N8 are pull-down transistors, forming memory node S3; P5 and P6 are pull-up transistors, and N9 and N10 are pull-down transistors, forming memory node S3. Furthermore, the gates of N4, N6, and N10 are controlled by memory node S0; the gates of N2, N3, and N7 are controlled by memory node S1; the gates of N1, N8, and P4 are controlled by memory node S2; the gates of N5, N9, and P3 are controlled by memory node S3; the gate of P6 is controlled by memory node S4; the gate of P2 is controlled by memory node S5; the gate of P1 is controlled by memory node S6; and the gate of P5 is controlled by memory node S7. The source or drain of P1, P3, P4, and P5 is electrically connected to the power supply VDD; the source or drain of N2, N5, N8, and N10 is electrically grounded.

4. The circuit structure of the radiation-resistant latch based on polarity hardening according to claim 3, characterized in that, The second SRAM cell includes PMOS transistors P7 to P12 and NMOS transistors N11 to N20; wherein P7 and P8 are pull-up transistors, and N11 and N12 are pull-down transistors, forming memory node S4; P9 and N13 are pull-up transistors, and N14 and N15 are pull-down transistors, forming memory node S6; P10 and N16 are pull-up transistors, and N17 and N18 are pull-down transistors, forming memory node S7; and P11 and P12 are pull-up transistors, and N19 and N20 are pull-down transistors, forming memory node S5. Furthermore, the gates of N14, N16, and N20 are controlled by memory node S4; the gates of N12, N13, and N17 are controlled by memory node S5; the gates of N11, N18, and P10 are controlled by memory node S6; the gates of N15, N19, and P9 are controlled by memory node S7; the gate of P12 is controlled by memory node S0; the gate of P8 is controlled by memory node S1; the gate of P7 is controlled by memory node S2; and the gate of P11 is controlled by memory node S3. The source or drain of P7, P9, P10, and P11 is electrically connected to the power supply VDD; the source or drain of N12, N15, N18, and N20 is electrically grounded.

5. The circuit structure of the radiation-resistant latch based on polarity hardening according to claim 1, characterized in that, The multi-input C unit includes PMOS transistors P13 to P16 and NMOS transistors N21 to N24; wherein, the gates of P16 and N21 are electrically connected to storage node S1; P15 and N22 are electrically connected to storage node S2; P14 and N23 are electrically connected to storage node S5; P13 and N24 are electrically connected to storage node S6; P13 to P16 and N21 to N24 are sequentially electrically connected to the output port Q.

6. The circuit structure of the radiation-resistant latch based on polarity hardening according to claim 1, characterized in that, The first transmission unit includes NMOS transistors N26 to N29; the gates of N26, N27, N28, and N29 are electrically connected to the word line WL respectively; each of N26, N27, N28, and N29 has one end electrically connected to node D, and the other end is sequentially electrically connected to memory nodes S0, S3, S4, and S7.

7. The circuit structure of the radiation-resistant latch based on polarity hardening according to claim 6, characterized in that, The second transmission unit includes NMOS transistors N30 to N33; the gates of N30, N31, N32, and N33 are electrically connected to the word line WL respectively; each of N30, N31, N32, and N33 has one end electrically connected to node DN, and the other end is sequentially electrically connected to memory nodes S1, S2, S5, and S6.

8. A circuit chip based on a polarity-hardened radiation-hardened latch, packaged using the circuit structure of a polarity-hardened radiation-hardened latch as described in any one of claims 1 to 7, characterized in that, The circuit chip includes: The first pin is electrically connected to the transmission gate, the first transmission unit, and the second transmission unit via the word line WL; The second pin is electrically connected to the transmission gate via the word line WLB; The third pin is electrically connected to the transmission gate and the first transmission unit via node D; The fourth pin is electrically connected to the second transmission unit via node DN; The fifth pin is electrically connected to the transmission gate and the multi-input C unit via the output port Q; The sixth pin is electrically connected to the first SRAM cell, the second SRAM cell, and the multi-input C cell via the power supply VDD; The seventh pin is electrically connected to the first SRAM cell, the second SRAM cell, and the multi-input C cell via a ground line.

9. The circuit chip of the radiation-hardened latch based on polarity hardening according to claim 8, characterized in that, The word line WL is electrically connected to the gates of N25 to N33 respectively, and then electrically connected to the first pin; the word line WLB is electrically connected to the gate of P17, and then electrically connected to the second pin.

10. A circuit module based on a polarity-hardened radiation-hardened latch, which adopts the circuit structure layout of the polarity-hardened radiation-hardened latch as described in any one of claims 1 to 7, characterized in that, The circuit module includes: The word line WL is electrically connected to the transmission gate, the first transmission unit, and the second transmission unit, and the first connection terminal is derived from there. The word line WLB is electrically connected to the transmission gate, and a second connection terminal is drawn from there; Node D is electrically connected to the transmission gate and the first transmission unit, and a third connection terminal is derived therefrom. The node DN is electrically connected to the second transmission unit, from which the fourth connection terminal is derived; The output port Q is electrically connected to the transmission gate and the multi-input C unit, thus forming the fifth connection terminal; The power supply VDD is electrically connected to the first SRAM cell, the second SRAM cell, and the multi-input C cell, and a sixth connection terminal is derived from there; The ground wire is electrically connected to the first SRAM cell, the second SRAM cell, and the multi-input C cell, thus leading to the seventh connection terminal.

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