Match line sensing device

Abstract

The application discloses a matching line induction device, which charges the matching line by using a charging module, limits the voltage during the charging of the matching line to be equal to the reference voltage of a first comparison module by using the first comparison module, detects the voltage change of the matching line by using a second comparison module, and outputs the corresponding level value according to the voltage change, and determines the matching state of the matching line according to the output level value change of the second comparison module by using an output module. Therefore, the application can realize full swing output of the induction voltage and avoid the problem of read interference influence on the storage unit.

Description

Technical Field

[0001] This application relates to the field of in-memory search and matching technology, and in particular to a matching line sensing device. Background Technology

[0002] The development of the internet has led to network capacity becoming a scarce resource. In the past, network capacity was primarily limited by link speed. Now, due to advancements in transmission technology and the introduction of fiber optics, the bottleneck is shifting from links to routers. The main function of a router is to forward IP packets to their final destination. First, it looks up the routing table entry based on the destination IP address. Then, based on the address of the most matching routing table entry, it forwards the packet to the next router. Traditional methods rely on the longest prefix matching algorithm used by the network processor to look up the routing table, requiring multiple memory accesses for each lookup, making parallel searching impossible and resulting in low efficiency. Tri-state Content Addressing Memory (TCAM) is an in-memory search device that can search all routing table entries in parallel within a single cycle. This fast search operation has led to the widespread application of TCAM in various packet processing hardware devices, such as IP lookup routing and network switches.

[0003] One of the most crucial steps in the TCAM search operation is the matching line sensing process. This involves using a matching line sensing circuit to detect minute changes in the voltage amplitude on the matching line, thereby distinguishing different levels of matching and finding the best match. Because the voltage variation on the matching line is small, most current matching line sensing schemes use full-swing sensing to ensure the reliability of the voltage signal detection process. This can cause read interference to the memory cells. Furthermore, there is the problem of increased dynamic power consumption due to excessive activity of the search line switch.

[0004] During the search for an entry, TCAM utilizes a matching line sensing amplifier to detect differences in voltage signal changes across different matching lines. To improve reliability, the matching line sensing scheme needs further optimization. Existing matching line sensing schemes, during the pre-charging phase, require switching the search line to ground to de-conduct the transistors in order to charge all matching lines to the power supply voltage, resulting in a significant increase in dynamic power consumption. This scheme directly detects changes in the matching line voltage, which is limited by read interference from memory cells, resulting in a less pronounced voltage swing and a narrower sensing margin, making it more difficult to design a high-precision matching line sensing scheme. Summary of the Invention

[0005] This application provides a matching line sensing device that can achieve full-swing output of the induced voltage while avoiding read interference to the storage unit.

[0006] This application provides a matching line sensing device, comprising: a charging module connected to a matching line for charging the matching line; a first comparison module, with its input terminal connected to the matching line and the charging module, and its output terminal connected to the charging module, for limiting the voltage of the matching line during charging to be equal to a reference voltage of the first comparison module; a second comparison module, with its input terminal connected to the matching line, for detecting voltage changes in the matching line and outputting a corresponding level value based on the voltage changes; and an output module connected to the output terminal of the second comparison module for determining the matching state of the matching line based on changes in the output level value of the second comparison module.

[0007] Optionally, in one embodiment of this application, the first comparison module includes: a first comparator, the positive input terminal of the first comparator being connected to a reference voltage, and the negative input terminal being connected to the matching line; and an isolation transistor, the first terminal of the isolation transistor being connected to the charging module, the second terminal being connected to the matching line, and the third terminal being connected to the output terminal of the first comparator, wherein the isolation transistor is used to bias the isolation transistor in the cutoff region when the matching line voltage is greater than the reference voltage of the first comparator.

[0008] Optionally, in one embodiment of this application, the charging module includes: a power supply; a charging transistor, wherein a first terminal of the charging transistor is connected to the power supply, a second terminal is connected to the first terminal of the isolation transistor, a third terminal is connected to a low level during the charging process of the matching line to turn on the charging transistor, and the third terminal is connected to a high level when the output level of the second comparison module flips to turn off the charging transistor.

[0009] Optionally, in one embodiment of this application, the second comparison module includes: a second comparator, the positive input terminal of the second comparator being connected to a reference voltage, the inverting input terminal being connected to the first terminal of the isolation transistor, and the output terminal being connected to the output module.

[0010] Optionally, in one embodiment of this application, the output module includes: a counter clock; an inverter, the input terminal of which is connected to the output terminal of the second comparison module, and the output terminal of which is connected to the counter clock; and a counter, which is connected to the counter clock and is used to count when the output terminal of the inverter is high.

[0011] Optionally, in one embodiment of this application, the output module is further configured to calculate the current of the matching line based on the counting time of the counter, and determine the number of matched or unmatched bits of the matching line based on the current of the matching line.

[0012] Optionally, in one embodiment of this application, it further includes: a matching line parasitic capacitor, wherein a first end of the matching line parasitic capacitor is grounded and a second end is connected to the matching line, for controlling the charging and discharging speed of the matching line.

[0013] Optionally, in one embodiment of this application, it further includes: a charging capacitor, the first end of which is grounded and the second end of which is connected to the first end of the isolation transistor, for controlling the charging and discharging speed of the first end of the isolation transistor and the sensing node on the charging module path, and for changing the current range of the detectable matching line by changing the capacitance of the charging capacitor when the counter clock frequency is fixed.

[0014] Optionally, in one embodiment of this application, it further includes a reset module connected to the matching line, used to ground the matching line before the matching line begins charging.

[0015] Optionally, in one embodiment of this application, the reset module includes: a first transistor, a first terminal of the first transistor being connected to the matching line, a second terminal being grounded, and a third terminal being connected to a reset signal, the reset signal including a high level or a low level.

[0016] The matching line sensing device of this application embodiment charges the matching line through a charging module and uses a first comparison module to limit the voltage on the matching line. During charging, if the matching line voltage is greater than the reference voltage of the first comparison module, the first comparison module disconnects the matching line from the charging module, ensuring that the matching line voltage remains equal to the reference voltage of the first comparison module. During the matching search, the matching line voltage decreases when a mismatch exists. A second comparison module detects the voltage change of the matching line and outputs a corresponding level value, allowing the output module to determine the matching state of the matching line based on the level value. Thus, by clamping the matching line charging voltage to the read voltage level of the storage cell through the first comparison module, read interference to the storage cell is avoided. Simultaneously, the matching line level and the sensing level are decoupled, achieving a full-swing output of the sensing voltage and improving the sensing margin.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0019] Figure 1 This is a schematic diagram of a matching line sensing device according to an embodiment of this application;

[0020] Figure 2 This is a schematic diagram of the matching line sensing device circuit provided according to an embodiment of this application;

[0021] Figure 3 This is a waveform diagram of the matching line sensing device provided according to the embodiments of this application during the entire sensing process;

[0022] Figure 4 This is a schematic diagram of the counter results for three levels of mismatch according to embodiments of this application. Detailed Implementation

[0023] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0024] Figure 1 This is a schematic diagram of a matching line sensing device according to an embodiment of this application.

[0025] like Figure 1 As shown, the matching line sensing device 10 includes: a charging module 100, a first comparison module 200, a second comparison module 300, and an output module 400.

[0026] The charging module 100 is connected to the matching line and is used to charge the matching line. The input terminal of the first comparison module 200 is connected to the matching line and the charging module, and the output terminal is connected to the charging module. It is used to limit the voltage of the matching line during charging to be equal to the reference voltage of the first comparison module. The input terminal of the second comparison module 300 is connected to the matching line and is used to detect the voltage change of the matching line and output the corresponding level value according to the voltage change. The output module 400 is connected to the output terminal of the second comparison module and is used to determine the matching state of the matching line according to the change of the output level value of the second comparison module.

[0027] Understandably, the TCAM search operation involves providing search data on the search line (SL), comparing it in parallel with the data stored in the TCAM unit, and generating a search result on the match line (ML). Any bit mismatch between the search data provided by SL and the data stored in the TCAM unit will create a path from ML to ground (GND) through the mismatch bit cell, causing a change in voltage on ML. The TCAM detects this voltage change on the match line using a match line sensing circuit. Figure 1The dashed box shows the matching line sensing device of this application, which includes a charging module, two comparison modules, and an output module. The charging module pre-charges the matching line to the reference voltage of the comparator; the first comparison module is used to limit the charging voltage of the matching line, and the second comparison module is used to detect changes in the voltage of the matching line; the output module outputs a corresponding distinguishable signal based on the matching and non-matching results.

[0028] like Figure 2 As shown, in one embodiment of this application, the first comparison module 200 includes: a first comparator (CP1), the positive input terminal of the first comparator being connected to a reference voltage (V). REF1 The inverting input terminal is connected to the matching line (ML); the isolation transistor (N1) has its first terminal connected to the charging module, its second terminal connected to the matching line, and its third terminal connected to the output terminal of the first comparator. The isolation transistor is used to bias the transistor in the cutoff region when the matching line voltage is greater than the reference voltage of the first comparator.

[0029] In one embodiment of this application, the charging module 100 includes: a power supply (VDD); a charging transistor (P1), the first terminal of which is connected to the power supply, the second terminal of which is connected to the first terminal of the isolation transistor, the third terminal of which is connected to a low level during the charging process of the matching line to turn on the charging transistor, and the third terminal of which is connected to a high level when the output level of the second comparator module flips to turn off the charging transistor.

[0030] In one embodiment of this application, the second comparison module 300 includes: a second comparator (CP2), the positive input terminal of which is connected to a reference voltage (V). REF2 The inverting input terminal is connected to the first terminal of the isolation transistor, and the output terminal is connected to the output module.

[0031] In one embodiment of this application, the output module 400 includes a counter clock.

[0032] An inverter, the input of which is connected to the output of the second comparator module, and the output of which is connected to the counter clock;

[0033] A counter is connected to a counter clock and is used to count when the output of the inverter is high.

[0034] In one embodiment of this application, the output module 400 is further configured to calculate the current of the matching line based on the counting time of the counter, and determine the number of matched or unmatched bits of the matching line based on the current of the matching line.

[0035] In one embodiment of this application, the matching line sensing device 10 further includes: matching line parasitic capacitance (Cap). MLThe first end of the parasitic capacitance of the matching line is grounded, and the second end is connected to the matching line to control the charging and discharging speed of the matching line.

[0036] In one embodiment of this application, the matching line sensing device 10 further includes: a charging capacitor (Cap SN The first end of the charging capacitor is grounded, and the second end is connected to the first end of the isolation transistor. This is used to control the charging and discharging speed of the first end of the isolation transistor and the sensing node on the charging module path. Also, when the counter clock frequency is fixed, the current range of the detectable matching line is changed by changing the capacitance of the charging capacitor.

[0037] In one embodiment of this application, the matching line sensing device 10 further includes a reset module RST, which is connected to the matching line and is used to ground the matching line before the matching line starts charging.

[0038] In one embodiment of this application, the reset module includes: a first transistor, a first terminal of the first transistor being connected to a matching line, a second terminal being grounded, and a third terminal being connected to a reset signal, the reset signal including a high level or a low level.

[0039] like Figure 2 As shown, before the sensing process, search data is sent into the array via bit lines. A reset signal (RST) resets the matching line ML voltage to GND. At this time, the output level of the first comparator CP1 is high, the isolation transistor N1 is turned on, so the sensing node (SN) is also low. The output level of the second comparator CP2 is high, and the output node (OUT) outputs a low level. The sensing process is divided into two stages: pre-charging and comparison. The entire matching line voltage sensing process is described in detail below.

[0040] During the pre-charge phase (RST=0, PRE=0), PRE is connected to a low level, causing the charging transistor P1 to turn on, and the power supply voltage (VDD) begins to pre-charge the matching line. The pre-charge is mainly divided into two phases: (1) Charging ML to the reference level of CP1: For ML with multiple mismatches, the pre-charge current flows directly to ground, and the voltage on ML will remain at the ground level. For the cases of complete matching and fewer mismatches, the voltage on ML will be pre-charged to exceed the reference voltage of comparator CP1. Once the voltage of ML exceeds the reference voltage of CP1, the output level of CP1 will drop to a certain level, causing the isolation transistor N1 to be biased in the cutoff region. The cutoff of N1 will interrupt the pre-charge process of the power supply voltage to the matching line, so ML will eventually be pre-charged to approximately equal to the reference level of comparator CP1. (2) Pre-charging the SN node voltage to VDD: Once the ML voltage is pre-charged to the reference level of CP1, the pre-charge current from P1 will be guided to the sensing node SN to continue charging the SN node to VDD, marking the end of the pre-charge phase. At this point, because the voltage at node SN is greater than the reference voltage of comparator CP2, the output signal of CP2 flips to a low level, and OUT outputs a high level. The output level of the OUT signal controls whether the counter clock is input to the counter module. Only when the output level of the OUT signal is high can the clock be input to the counter module. In other words, the end of the precharge phase means that the counter starts counting. During the precharge phase, the isolation transistor N1 decouples the matching line level and the sensing level, which can limit the charging voltage of the matching line to the level of the memory cell read voltage, and enable the sensing level to achieve a full swing output.

[0041] During the comparison phase (RST=0, PRE=1), the ML in a perfectly matched state will maintain the pre-charge level, while the ML with mismatched bits will begin to discharge to ground through the mismatched bit cell. (1) As the voltage on the mismatched ML decreases, the output level of comparator CP1 will flip to a high level, at which point the isolation transistor N1 will turn on. (2) Since the voltage of the SN node is at the VDD level, there is a voltage difference between it and ML, and SN and ML will share charge. During the charge sharing process, the voltage of the SN node decreases. When the voltage of the SN node is lower than the reference level of comparator CP2, CP2 outputs a high level, causing the output OUT to change to a low level, so that the clock of the counter cannot be connected and the counting stops. (3) The counter result at this time can be used as a standard for judging the degree of matching: the higher the degree of matching, the slower the discharge speed, the longer the time required for the voltage of the SN node to drop to the reference level of CP2, the longer the counter counting time, and the larger the output counting result value.

[0042] Figure 3The waveforms of several important signals during the entire induction process are shown: (1) In the pre-charge phase, the voltage on ML charges to the read voltage level of the storage cell, and the voltage on the SN node charges to the power supply voltage level, causing the output OUT to change from low to high, and the counter starts working. (2) In the comparison phase, charge sharing occurs between the ML and SN nodes, causing the output OUT to change from high to low, and the counter stops working. Figure 4 You can see the counter results corresponding to the three levels of mismatch. The output counter results can be used as an indicator of the degree of mismatch.

[0043] The most important charge sharing process in the comparison process can be described by formula (1):

[0044] I ML ·T = Cap SN ·ΔV(1)

[0045] Where I ML It is the current on the matching line, T is the counting time of the counter, and Cap is the current on the matching line. SN ΔV is the capacitor that controls the charging and discharging speed of the SN sensing node on the sensing path, and ΔV is the amplitude of the voltage drop of the SN sensing node from the power supply voltage to the reference voltage. According to formula (1), once the sensing capacitor and the amplitude of the voltage drop are determined, the current is inversely related to the counting time. The current on the matching line is related to the matching degree, which can be obtained from formula (2):

[0046]

[0047] Where N is the total number of data bits, n is the number of mismatched bits, and R HRS It is the high resistance of the storage cell, R LRS It has a low resistance value, V ML To match the line voltage. Therefore, the counting time corresponds to the degree of matching, and the number of mismatched bits can be deduced from the counter result. In addition, when the counter clock frequency is constant, the maximum counting time of the counter is also determined. Then, according to formula (1), it can be found that changing the charging capacitor Cap SN The range of detected current can be changed. Therefore, this matching line induction scheme can also verify the resistance value of the storage cell and can serve as a current detection circuit.

[0048] According to the matching line sensing device proposed in this application, the matching line charging voltage is clamped to the storage cell read voltage level by a first comparison module to avoid the influence of read interference. Furthermore, the isolation transistor within the first comparison module decouples the matching line level and the sensing level, achieving a full-swing output of the sensing voltage and improving the sensing margin. After charging stops at the two charging nodes, charge sharing occurs due to the voltage difference. By adjusting the size of the charging capacitor, the counter can distinguish various current conditions, achieving resistance state verification. Therefore, while improving the sensing margin, the influence of read interference can be eliminated, enabling TCAM to achieve more reliable search operations and saving space by replacing the current detection circuit.

[0049] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0051] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

Claims

1. A matching line sensing device, characterized in that, include: A charging module, which is connected to a matching line, is used to charge the matching line; A first comparison module, the input terminal of which is connected to the matching line and the charging module, and the output terminal of which is connected to the charging module, is used to limit the voltage of the matching line during charging to be equal to the reference voltage of the first comparison module. The second comparison module has its input terminal connected to the matching line, and is used to detect the voltage change of the matching line and output the corresponding level value according to the voltage change; An output module, which is connected to the output terminal of the second comparison module, is used to determine the matching state of the matching line based on the change in the output level value of the second comparison module; The first comparison module includes: The first comparator has its positive input terminal connected to a reference voltage and its inverting input terminal connected to the matching line. An isolation transistor is provided, wherein a first terminal of the isolation transistor is connected to the charging module, a second terminal is connected to the matching line, and a third terminal is connected to the output terminal of the first comparator. The isolation transistor is used to bias the isolation transistor in the cutoff region when the voltage of the matching line is greater than the reference voltage of the first comparator. The first comparison module clamps the matching line charging voltage to the memory cell read voltage level and uses the isolation transistor in the first comparison module to decouple the matching line level and the sensed level. The second comparison module includes: The second comparator has its positive input connected to a reference voltage, its inverting input connected to the first terminal of the isolation transistor, and its output connected to the output module.

2. The apparatus according to claim 1, characterized in that, The charging module includes: power supply; The charging transistor has a first terminal connected to the power supply, a second terminal connected to the first terminal of the isolation transistor, and a third terminal connected to a low level during the charging process of the matching line to turn on the charging transistor. The third terminal is connected to a high level when the output level of the second comparator module flips, causing the charging transistor to turn off.

3. The apparatus according to claim 1, characterized in that, The output module includes: Counter clock; An inverter, the input of which is connected to the output of the second comparison module, and the output of which is connected to the clock of the counter; A counter, connected to the counter clock, is used to count when the output of the inverter is high.

4. The apparatus according to claim 3, characterized in that, The output module is further configured to calculate the current of the matching line based on the counting time of the counter, and determine the number of matched or unmatched bits of the matching line based on the current of the matching line.

5. The apparatus according to claim 1, characterized in that, Also includes: The matching line parasitic capacitance has a first end grounded and a second end connected to the matching line, used to control the charging and discharging speed of the matching line.

6. The apparatus according to claim 3, characterized in that, Also includes: A charging capacitor, with its first terminal grounded and its second terminal connected to the first terminal of the isolation transistor, is used to control the charging and discharging speed of the first terminal of the isolation transistor and the sensing node on the charging module path, and to change the current range of the detectable matching line by changing the capacitance of the charging capacitor when the counter clock frequency is fixed.

7. The apparatus according to claim 1, characterized in that, Also includes: A reset module, which is connected to the matching line, is used to ground the matching line before the matching line starts charging.

8. The apparatus according to claim 7, characterized in that, The reset module includes: A first transistor, wherein a first terminal of the first transistor is connected to the matching line, a second terminal is grounded, and a third terminal is connected to a reset signal, the reset signal including a high level or a low level.

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