Solid state drive adapter double data rate synchronous dynamic random access memory method and component

Abstract

The application discloses a solid state disk adaptive double rate synchronous dynamic random access memory method and component, relates to the solid state disk storage technical field, and includes the following steps: when receiving a power-on request, loading a preset firmware and reading type information of a to-be-trained double rate synchronous dynamic random access memory from a preset flash memory chip; determining a corresponding predefined structure body representing dynamic random access memory parameters from the preset firmware based on the type information; training the to-be-trained double rate synchronous dynamic random access memory by using the predefined structure body, obtaining a corresponding training result, so as to determine that a signal of the to-be-trained double rate synchronous dynamic random access memory is a stable signal based on the training result, and complete an adaptation process of the to-be-trained double rate synchronous dynamic random access memory. Through the scheme, the preset firmware can adapt to various solid state disks, the maintenance cost of research and development is reduced, a version is not needed to be released each time, different versions of firmware are simultaneously released, and the utilization efficiency of research and development personnel is improved.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive (SSD) storage technology, and in particular to a method and components for adapting a solid-state drive to a double-rate synchronous dynamic random access memory (DRAM). Background Technology

[0002] With the rapid development of information technology, data generation and storage are problems we face. Currently, SSDs (Solid State Disks) are widely used in various industries due to their high bandwidth and low latency characteristics. SSDs contain many hardware components that support their functionality, such as DDR (Double Data Rate Synchronous Dynamic Random Access Memory), Norflash (flash memory chips), and EEPROM (Electrically Erasable Programmable Read-Only Memory). Because the supply of various components may be scarce, SSDs are designed from the outset to be compatible with multiple materials to ensure a stable supply.

[0003] In existing management methods, during the initial SSD design phase, to avoid impacting shipment volumes due to DDR supply chain issues from vendors, multiple DDR types are selected for compatibility, with one primary and multiple backups. This is because when an SSD powers on, it needs to train the DDR to maintain stable signals, and different vendors' DDR configuration parameters may vary. Current management methods involve developing firmware that configures parameters for different DDR types using compilation options, and each firmware can only have one DDR configuration structure active at a time, preventing selection and ensuring each firmware is compatible with only one DDR type. Since the DDR model cannot be enumerated during firmware power-on, switching to a different DDR component type requires a completely new firmware from development to production, a cumbersome process that consumes significant manpower.

[0004] In summary, how to avoid the cumbersome and inefficient process of distinguishing different firmware versions to check all DDR types when powering on solid-state drives in the factory, which is caused by a single firmware being compatible with only one type of DDR, and how to achieve high-efficiency factory processing is a technical problem that needs to be solved in this field. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a method and component for adapting a solid-state drive (SSD) to Double Data Rate (DMR) synchronous dynamic random access memory (DRAM). This avoids the cumbersome and inefficient process of distinguishing different firmware versions to check all DDR types during factory power-up of SSDs, which is caused by a single firmware version only being compatible with one DDR type. The invention achieves high-efficiency factory processing. The specific solution is as follows:

[0006] In a first aspect, this application discloses a method for adapting a solid-state drive to a double-data-rate synchronous dynamic random access memory, comprising:

[0007] When a power-on request is received, the preset firmware is loaded and the type information of the double-rate synchronous dynamic random access memory to be trained is read from the preset flash memory chip;

[0008] Based on the type information, a predefined structure representing the parameters of the dynamic random access memory is determined from the preset firmware;

[0009] The predefined structure is used to train the double-rate synchronous dynamic random access memory to be trained, and the corresponding training results are obtained. Based on the training results, the signal of the double-rate synchronous dynamic random access memory to be trained is determined to be a stable signal, and the adaptation process of the double-rate synchronous dynamic random access memory to be trained is completed.

[0010] Optionally, after loading the preset firmware upon receiving a power-on request, the method further includes:

[0011] The factory parameters stored in the preset flash memory chip are used to determine whether the power-on request is a factory power-on request;

[0012] Accordingly, reading the type information of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip includes:

[0013] If the power-on request is a factory-set power-on request, then the type information of the double-rate synchronous dynamic random access memory to be trained is read from the preset flash memory chip.

[0014] Optionally, if the power-on request is a factory-defined power-on request, after reading the type information of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip in the preset firmware, the method further includes:

[0015] Determine whether the encoded information of the type information is pre-encoded information representing the type information stored in the preset flash memory chip;

[0016] Accordingly, determining the predefined structure representing the dynamic random access memory parameters from the preset firmware based on the type information includes:

[0017] If not, the standard parameter configuration information of the double-rate synchronous dynamic random access memory to be trained is obtained from the preset flash memory chip.

[0018] Optionally, after determining whether the power-on request is a factory-set power-on request using the factory parameters stored in the preset flash memory chip, the method further includes:

[0019] If the power-on request is a normal power-on request, then the training result of the double-rate synchronous dynamic random access memory to be trained is read from the preset flash memory chip, and the double-rate synchronous dynamic random access memory to be trained is initialized.

[0020] Optionally, the method for adapting a solid-state drive to double-rate synchronous dynamic random access memory further includes:

[0021] The dynamic random access memory parameters of different double rate synchronous dynamic random access memories are set to the corresponding software-defined structures and saved using a software-defined method.

[0022] Construct the correspondence between the software-defined structure and the type information of the corresponding double-rate synchronous dynamic random access memory.

[0023] Optionally, after constructing the correspondence between the software-defined structure and the corresponding type information of the double-rate synchronous dynamic random access memory, the method further includes:

[0024] The firmware package, the corresponding relationship, and the type information are burned offline to the preset firmware.

[0025] Optionally, determining the corresponding predefined structure representing the dynamic random access memory parameters from the preset firmware based on the type information includes:

[0026] Based on the type information and the correspondence, a predefined structure representing the parameters of the dynamic random access memory is determined from the preset flash memory chip.

[0027] Secondly, this application discloses a solid-state drive-adapted double-data-rate synchronous dynamic random access memory device, comprising:

[0028] The first information acquisition module is used to load the preset firmware and read the type information of the double-rate synchronous dynamic random access memory to be trained from the preset firmware when a power-on request is received.

[0029] The second information acquisition module is used to determine the corresponding predefined structure representing the parameters of the dynamic random access memory from the preset firmware based on the type information.

[0030] An adaptation module is used to train the double-rate synchronous dynamic random access memory to be trained using the predefined structure, obtain the corresponding training results, and determine the signal of the double-rate synchronous dynamic random access memory to be trained as a stable signal based on the training results, thereby completing the adaptation process of the double-rate synchronous dynamic random access memory to be trained.

[0031] Thirdly, this application discloses an electronic device, including:

[0032] Memory, used to store computer programs;

[0033] A processor is configured to execute the computer program to implement the steps of the aforementioned disclosed method for adapting a solid-state drive to double-rate synchronous dynamic random access memory.

[0034] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the aforementioned disclosed solid-state drive adaptation to double-rate synchronous dynamic random access memory method.

[0035] Therefore, this application discloses a method for adapting a solid-state drive (SSD) to a double-rate synchronous dynamic random access memory (DRAM), comprising: when receiving a power-on request, loading preset firmware and reading the type information of the DRAM to be trained from the preset flash memory chip; determining a predefined structure representing the parameters of the DRAM from the preset firmware based on the type information; training the DRAM to be trained using the predefined structure, obtaining the corresponding training results, so as to determine that the signal of the DRAM to be trained is a stable signal based on the training results, thereby completing the adaptation process of the DRAM to be trained. As can be seen, by directly utilizing the corresponding type information obtained from the preset flash memory chip, the predefined structure representing the parameters of the dynamic random access memory can be determined from the preset firmware. That is, the preset firmware can contain predefined structures corresponding to different types of information. Accordingly, different types of double-rate synchronous dynamic random access memory can be trained to adapt to different solid-state drives. This allows the preset firmware to be compatible with multiple solid-state drives, avoiding the need for multiple steps to distinguish different firmware versions of SSDs during the SSD manufacturing process, which leads to a cumbersome and inefficient manufacturing process. It also reduces the maintenance costs of R&D, as different firmware versions do not need to be released simultaneously for each release, thus improving the utilization efficiency of R&D personnel. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0037] Figure 1 This application discloses a flowchart of a method for adapting a solid-state drive to a double-speed synchronous dynamic random access memory (SRAM).

[0038] Figure 2 This application discloses a content allocation logic diagram in Norflash.

[0039] Figure 3This application discloses a specific method for adapting a solid-state drive to a double-speed synchronous dynamic random access memory (SRAM).

[0040] Figure 4 This application discloses a factory-based DDR initialization flowchart;

[0041] Figure 5 This is a schematic diagram of a solid-state drive adapted to a double-rate synchronous dynamic random access memory device disclosed in this application.

[0042] Figure 6 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0044] With the rapid development of information technology, data generation and storage are problems we face. Currently, SSDs are widely used in various industries due to their high bandwidth and low latency characteristics. SSDs have many internal hardware components to support their functions, such as DDR, Norflash, and EEPROM. Because the supply of various components may be scarce, SSDs are designed from the outset to be compatible with multiple materials to ensure normal supply.

[0045] In existing management methods, during the initial SSD design phase, to avoid impacting shipment volumes due to DDR supply chain issues from vendors, multiple DDR types are selected for compatibility, with one primary and multiple backups. This is because when an SSD powers on, it needs to train the DDR to maintain stable signals, and different vendors' DDR configuration parameters may vary. Current management methods involve developing firmware that configures parameters for different DDR types using compilation options, and each firmware can only have one DDR configuration structure active at a time, preventing selection and ensuring each firmware is compatible with only one DDR type. Since the DDR model cannot be enumerated during firmware power-on, switching to a different DDR component type requires a completely new firmware from development to production, a cumbersome process that consumes significant manpower.

[0046] To address this, this application provides a solid-state drive (SSD) adaptation scheme for double-speed synchronous dynamic random access memory (DDR), which avoids the cumbersome and inefficient process of distinguishing different firmware versions to check all DDR types when powering on an SSD during factory production, as a single firmware only adapts to one type of DDR. This achieves highly efficient factory processing.

[0047] Reference Figure 1 As shown in the figure, an embodiment of the present invention discloses a method for adapting a solid-state drive to a double-data-rate synchronous dynamic random access memory, comprising:

[0048] Step S11: When a power-on request is received, load the preset firmware and read the type information of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip.

[0049] In this embodiment, when the solid-state drive (SSD) receives a power-on request, it first loads a preset firmware from the SSD's Norflash. After the preset firmware runs normally, it reads the type information of the Double Rate Synchronous Dynamic Random Access Memory (DDR) to be trained from the Norflash. It is understood that the preset firmware resides in a preset flash memory chip (Norflash), which is located within the SSD. When the SSD powers on based on the power-on request, it immediately loads the internal preset firmware. After the preset firmware runs normally, it reads the type information of the Double Rate Synchronous Dynamic Random Access Memory (DDR) to be trained from its Norflash. It should be noted that the DDR to be trained often has several different types.

[0050] Step S12: Determine the corresponding predefined structure representing the dynamic random access memory parameters from the preset firmware based on the type information.

[0051] In this embodiment, a predefined structure representing the parameters of the dynamic random access memory is determined from the preset firmware based on type information and correspondence. It can be understood that the corresponding software-defined structure of the double-rate synchronous dynamic random access memory (DDR) to be trained is determined from the preset firmware by reading the type information and based on that type information and correspondence.

[0052] In this embodiment, the dynamic random access memory (DRAM) parameters of different Double Rate Synchronous Dynamic Random Access Memory (DRAM) systems are set to corresponding software-defined structures and saved using a software-defined approach. A correspondence is then established between these software-defined structures and the corresponding DRAM type information. It is understood that the DRAM parameters of DRAMs from different manufacturers may differ. Conventionally, different firmware would need to be compiled separately for different types of DRAMs, meaning the configuration parameter structure for a specific type of DRAM would be stored in Norflash, and each firmware would only be compatible with one type of DRAM. Therefore, the software-defined approach changes the storage of the DRAM configuration parameter structure from Norflash to software definition. This saves Norflash cost by freeing up the space previously used for storing the DDR configuration parameter structure. Since software definition has no space limitations, the number of DRAM configuration parameter structures can exceed a single design. Consequently, this software-defined structure approach allows a single firmware to be compatible with multiple types of DRAMs. Next, a correspondence is established between different software-defined structures and the corresponding type information of double-rate synchronous dynamic random access memory, so that the corresponding software-defined structure can be queried based on the obtained type information and the correspondence.

[0053] In this embodiment, after constructing the correspondence between the software-defined structure and the corresponding type information of the double-rate synchronous dynamic random access memory, the method further includes: offline burning the firmware package, the correspondence, and the type information to a preset flash memory chip. It can be understood that the firmware package representing the preset firmware, along with the aforementioned correspondence and type information, are burned offline into the preset flash memory chip (Norflash) for use by the solid-state drive (SSD) during power-on. Figure 2The diagram shows the internal allocation logic of Norflash, specifically: Norflash contains firmware packages, factory flag parameters, DDR SPD parameters and DDT parameters, DDR training results, and other board-level parameters. The original configuration parameters for Double Rate Synchronous Dynamic Random Access Memory (DDR) in the Norflash flash chip were changed to software-defined structures. Specifically, the configured DDR SPD and ODT parameter tables were made into fixed software structure definitions. For example, DDR1 was defined as a `ddr1_parameter_table` structure, and DDR2 as a `ddr2_parameter_table` structure. These structures then define the actual DDR configuration parameters used. This changes the original method of reading the DDR parameter table from Norflash for DDR training to one where the DDR type information is used to call the parameters defined in the firmware for DDR training. Additionally, a fixed address in the pre-defined Norflash flash memory chip is defined as the Double Data Rate (DDR) type. When offline burning firmware packages and board-level parameters, the DDR type is written to the Norflash as a board-level parameter. Then, the Norflash is soldered to the SSD board containing the specified DDR. It is important to note that the DDR type must match the actual DDR type information of the SSD version.

[0054] In this embodiment, a Norflash flash chip containing the preset firmware that is compatible with multiple types of Double Rate Synchronous Dynamic Random Access Memory (DDR) is soldered onto a board containing multiple solid-state drives (SSDs). This eliminates the need for one preset firmware to correspond to only one SSD, allowing one preset firmware to correspond to multiple SSDs. In other words, one preset firmware can be programmed onto both DDR type A and DDR type B SSDs, reducing the cost of developing and maintaining multiple firmware types and improving personnel utilization efficiency.

[0055] Step S13: Use the predefined structure to train the double-rate synchronous dynamic random access memory to be trained, obtain the corresponding training results, so as to determine the signal of the double-rate synchronous dynamic random access memory to be trained as a stable signal based on the training results, and complete the adaptation process of the double-rate synchronous dynamic random access memory to be trained.

[0056] In this embodiment, the corresponding Double Rate Synchronous Dynamic Random Access Memory (DDR) to be trained is initialized according to the corresponding software-defined structure queried. The stability of each signal of the DDR to be trained is maintained according to the training results. Thus, the adaptation process between the DDR and the SSD is completed. If power is applied again, the normal power-on process of the SSD is executed, that is, the DDR training results are read directly to perform the initialization activity of the DDR.

[0057] Therefore, when executing an industrial power-on request, the type information of multiple Double Rate Synchronous Dynamic Random Access Memory (DDR) to be trained can be obtained simultaneously. This makes it convenient to train the DDR using only one DDR parameter table containing the type information of all DDR to be trained, so that the preset firmware can select the DDR parameter table according to the DDR type information.

[0058] Therefore, this application discloses a method for adapting a solid-state drive (SSD) to a double-rate synchronous dynamic random access memory (DRAM), comprising: when receiving a power-on request, loading preset firmware and reading the type information of the DRAM to be trained from a preset flash memory chip; determining a predefined structure representing the parameters of the DRAM from the preset firmware based on the type information; training the DRAM to be trained using the predefined structure, obtaining the corresponding training results, so as to determine that the signal of the DRAM to be trained is a stable signal based on the training results, thereby completing the adaptation process of the DRAM to be trained. As can be seen, by directly utilizing the corresponding type information obtained from the preset flash memory chip, the predefined structure representing the parameters of the dynamic random access memory can be determined from the preset firmware. That is, the preset firmware can contain predefined structures corresponding to different types of information. Accordingly, different types of double-rate synchronous dynamic random access memory can be trained to adapt to different solid-state drives. This allows the preset firmware to be compatible with multiple solid-state drives, avoiding the need for multiple steps to distinguish different firmware versions of SSDs during the SSD manufacturing process, which leads to a cumbersome and inefficient manufacturing process. It also reduces the maintenance costs of R&D, as different firmware versions do not need to be released simultaneously for each release, thus improving the utilization efficiency of R&D personnel.

[0059] Reference Figure 3 As shown, this embodiment of the invention discloses a specific method for adapting a solid-state drive (SSD) to a double-rate synchronous dynamic random access memory (DRAM). Compared to the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically:

[0060] Step S21: When a power-on request is received, load the preset firmware.

[0061] For a more detailed description of step S21, please refer to the content disclosed in the foregoing embodiments, which will not be repeated here.

[0062] Step S22: Use the factory parameters stored in the preset flash memory chip to determine whether the power-on request is a factory power-on request.

[0063] In this embodiment, after the preset firmware is run, the factory parameters saved in the preset flash memory chip Norflash where the preset firmware is located are read to determine whether the power-on request is a factory power-on request. The factory parameters are the saved factory flag bits.

[0064] Step S23: If the power-on request is a factory power-on request, then read the type information of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip.

[0065] In this embodiment, if the power-on request is determined to be a factory-defined power-on request, then the preset firmware is loaded, and the type information of the Double Data Rate Synchronous Dynamic Random Access Memory (DDR) to be trained is read from the preset flash memory chip Norflash. This type information may or may not exist in the preset flash memory chip Norflash.

[0066] Step S24: Determine whether the encoded information of the type information is pre-encoded information representing the type information stored in the preset flash memory chip.

[0067] In this embodiment, the encoded information of the read type information is judged. Specifically, if the type information of the Double Rate Synchronous Dynamic Random Access Memory (DDR) to be trained is encoded information representing an empty address, it indicates that the type information of the preset flash memory chip Norflash has not been written to the DDR, that is, the encoded information is not pre-encoded information. For example, if the type information of the Double Rate Synchronous Dynamic Random Access Memory (DDR) to be trained is 0xFF, it indicates that the type information of the preset flash memory chip Norflash has not been written to the DDR. If the type information of the Double Rate Synchronous Dynamic Random Access Memory (DDR) to be trained is encoded information representing a certain actual address of the preset flash memory chip Norflash, it indicates that the type information of the preset flash memory chip Norflash has been written to the DDR, that is, the encoded information is pre-encoded information. Then, the parameter structure defined in the preset firmware is called according to the type information to train the Double Rate Synchronous Dynamic Random Access Memory (DDR).

[0068] Step S25: If not, obtain the standard parameter configuration information of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip.

[0069] In this embodiment, if not, the pre-saved default standard parameter configuration information is directly loaded from the preset flash memory chip Norflash, wherein the standard parameter configuration information is the configuration parameter information of DDR SPD and DDR ODT.

[0070] Step S26: Train the double-rate synchronous dynamic random access memory to be trained using the standard parameter configuration information, obtain the corresponding training results, and determine the signal of the double-rate synchronous dynamic random access memory to be trained as a stable signal based on the training results, thereby completing the adaptation process of the double-rate synchronous dynamic random access memory to be trained.

[0071] In this embodiment, the configuration parameter information of DDR SPD and DDR ODT is used to train the double-rate synchronous dynamic random access memory to be trained, obtain the corresponding training results, write the training results into the preset flash memory chip Norflash, initialize the double-rate synchronous dynamic random access memory to be trained DDR, and then power on.

[0072] Reference Figure 4 The diagram shows the factory DDR initialization process. First, the firmware package and the DDR type information of the software-defined structure are offline burned into the Norflash flash memory chip. Then, the Norflash flash memory chip is soldered onto the designated SSD board. The designated SSD board is a solid-state drive SSD board that corresponds to the various types of DDR information recorded in the Norflash flash memory chip. After the SSD is powered on, the firmware is loaded, and the factory flag is read from the Norflash flash memory to determine if this power-on is a factory power-on. If so, the firmware is loaded, and the DDR type information read from the Norflash flash memory is checked to see if it represents a type information mapped to a fixed address. If so, the parameter structure defined in the firmware is directly called to train the Double Rate Synchronous Dynamic Random Access Memory (DDR) to be trained, based on the mapping relationship. If not, the empty DDR type information is discarded, and the default configuration parameters are directly read from the Norflash flash memory to train the DDR to be trained. The training result parameters are written to the Norflash flash memory for storage, so that they can be used for subsequent power-ons. If this power-on is not a factory power-on, the power-on request is determined to be a normal power-on request, and the training result of the corresponding DDR stored in the Norflash flash memory is directly called to initialize the DDR.

[0073] Step S27: If the power-on request is a normal power-on request, then read the training result of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip, and initialize the double-rate synchronous dynamic random access memory to be trained.

[0074] In this embodiment, if the preset firmware determines that the power-on is normal, it directly reads the historical DDR training results from the Norflash flash memory chip, and then performs DDR initialization and subsequent power-on actions. Specifically, since the power-on is determined to be normal, it indicates that the solid-state drive SSD is a factory-made SSD. When it is powered on again, the normal power-on process of the solid-state drive SSD will be executed, that is, the DDR training results will be read directly to initialize the DDR.

[0075] Therefore, it can be seen that for factory production, each time a new version is released, only one firmware needs to be provided to the factory, which reduces many unnecessary processes and improves the efficiency of factory production.

[0076] Reference Figure 5 As shown, this embodiment of the invention also discloses a solid-state drive-adapted double-data-rate synchronous dynamic random access memory device, comprising:

[0077] The first information acquisition module 11 is used to load the preset firmware and read the type information of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip when a power-on request is received.

[0078] The second information acquisition module 12 is used to determine the corresponding predefined structure representing the parameters of the dynamic random access memory from the preset firmware based on the type information.

[0079] The adaptation module 13 is used to train the double-rate synchronous dynamic random access memory to be trained using the predefined structure, obtain the corresponding training results, and determine the signal of the double-rate synchronous dynamic random access memory to be trained as a stable signal based on the training results, thereby completing the adaptation process of the double-rate synchronous dynamic random access memory to be trained.

[0080] Therefore, this application discloses that when a power-on request is received, a preset firmware is loaded and the type information of the double-rate synchronous dynamic random access memory to be trained is read from a preset flash memory chip; based on the type information, a predefined structure representing the parameters of the dynamic random access memory is determined from the preset firmware; the double-rate synchronous dynamic random access memory to be trained is trained using the predefined structure, and the corresponding training results are obtained, so as to determine that the signal of the double-rate synchronous dynamic random access memory to be trained is a stable signal based on the training results, thereby completing the adaptation process of the double-rate synchronous dynamic random access memory to be trained. As can be seen, by directly utilizing the corresponding type information obtained from the preset flash memory chip, the predefined structure representing the parameters of the dynamic random access memory can be determined from the preset firmware. That is, the preset firmware can contain predefined structures corresponding to different types of information. Accordingly, different types of double-rate synchronous dynamic random access memory can be trained to adapt to different solid-state drives. This allows the preset firmware to be compatible with multiple solid-state drives, avoiding the need for multiple steps to distinguish different firmware versions of SSDs during the SSD manufacturing process, which leads to a cumbersome and inefficient manufacturing process. It also reduces the maintenance costs of R&D, as different firmware versions do not need to be released simultaneously for each release, thus improving the utilization efficiency of R&D personnel.

[0081] In some specific embodiments, the solid-state drive is adapted to a double-data-rate synchronous dynamic random access memory device, which may specifically include:

[0082] The request determination unit is used to determine whether the power-on request is a factory-defined power-on request by using the factory parameters stored in the preset flash memory chip.

[0083] In some specific embodiments, the first information acquisition module 11 may specifically include:

[0084] The information acquisition submodule is used to read the type information of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip if the power-on request is a factory-made power-on request.

[0085] In some specific implementations, the information acquisition submodule may specifically include:

[0086] An information determination unit is used to determine whether the encoded information of the type information is pre-encoded information representing the type information stored in the preset flash memory chip.

[0087] In some specific embodiments, the second information acquisition module 12 may specifically include:

[0088] The configuration information acquisition unit is used to acquire the standard parameter configuration information of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip if no.

[0089] In some specific embodiments, the first information acquisition module 11 may specifically include:

[0090] The information acquisition unit is used to read the training result of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip and initialize the double-rate synchronous dynamic random access memory to be trained if the power-on request is a normal power-on request.

[0091] In some specific embodiments, the solid-state drive is adapted to a double-data-rate synchronous dynamic random access memory device, which may specifically include:

[0092] The information pre-storage submodule is used to set the dynamic random access memory parameters of different double rate synchronous dynamic random access memories to corresponding software-defined structures and save them in a software-defined manner; and to construct the correspondence between the software-defined structures and the type information of the corresponding double rate synchronous dynamic random access memories.

[0093] In some specific embodiments, the information pre-storage submodule may specifically include:

[0094] The programming unit is used to offline program the firmware package, the corresponding relationship, and the type information to a preset flash memory chip.

[0095] In some specific embodiments, the second information acquisition module 12 may specifically include:

[0096] The structure determination unit is used to determine the corresponding predefined structure representing the dynamic random access memory parameters from the preset firmware based on the type information and the correspondence.

[0097] Furthermore, embodiments of this application also disclose an electronic device, Figure 6 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0098] Figure 6 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. Specifically, the electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the solid-state drive adaptation method for double-rate synchronous dynamic random access memory disclosed in any of the foregoing embodiments. Alternatively, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0099] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0100] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0101] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0102] The operating system 221 manages and controls the various hardware devices and computer programs 222 on the electronic device 20 to enable the processor 21 to perform calculations and processing on the massive amounts of data 223 in the memory 22. The operating system 221 can be Windows Server, Netware, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of performing the solid-state drive adaptation double-rate synchronous dynamic random access memory method disclosed in any of the foregoing embodiments, may further include computer programs capable of performing other specific tasks. The data 223 may include data received by the electronic device from external devices, as well as data collected by its own input / output interface 25.

[0103] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned method for adapting a solid-state drive to double-rate synchronous dynamic random access memory. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0104] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0105] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementation should not be considered beyond the scope of this application. The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. Software modules can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0106] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0107] The above provides a detailed description of the solid-state drive adaptation method and components for double-speed synchronous dynamic random access memory provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for adapting a solid-state drive (SSD) to a double-speed synchronous dynamic random access memory (SRAM), characterized in that, include: When a power-on request is received, the preset firmware is loaded and the type information of the double-rate synchronous dynamic random access memory to be trained is read from the preset flash memory chip; Based on the type information, a predefined structure representing the parameters of the dynamic random access memory is determined from the preset firmware; The predefined structure is used to train the double-rate synchronous dynamic random access memory to be trained, and the corresponding training results are obtained. Based on the training results, the signal of the double-rate synchronous dynamic random access memory to be trained is determined to be a stable signal, and the adaptation process of the double-rate synchronous dynamic random access memory to be trained is completed. The method further includes: The dynamic random access memory parameters of different double rate synchronous dynamic random access memories are set to the corresponding software-defined structures and saved using a software-defined method. Construct the correspondence between the software-defined structure and the type information of the corresponding double-rate synchronous dynamic random access memory; The firmware package, the corresponding relationship, and the type information are offline burned to a preset flash memory chip.

2. The method for adapting a solid-state drive to a double-speed synchronous dynamic random access memory according to claim 1, characterized in that, After loading the preset firmware upon receiving a power-on request, the process further includes: The factory parameters stored in the preset flash memory chip are used to determine whether the power-on request is a factory power-on request; Accordingly, reading the type information of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip includes: If the power-on request is a factory-set power-on request, then the type information of the double-rate synchronous dynamic random access memory to be trained is read from the preset flash memory chip.

3. The method for adapting a solid-state drive to a double-speed synchronous dynamic random access memory according to claim 2, characterized in that, If the power-on request is a factory-set power-on request, then after reading the type information of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip, the method further includes: Determine whether the encoded information of the type information is pre-encoded information representing the type information stored in the preset flash memory chip; Accordingly, determining the predefined structure representing the dynamic random access memory parameters from the preset firmware based on the type information includes: If not, the standard parameter configuration information of the double-rate synchronous dynamic random access memory to be trained is obtained from the preset flash memory chip.

4. The method for adapting a solid-state drive to a double-speed synchronous dynamic random access memory according to claim 2, characterized in that, After determining whether the power-on request is a factory-set power-on request using the factory parameters stored in the preset flash memory chip, the method further includes: If the power-on request is a normal power-on request, then the training result of the double-rate synchronous dynamic random access memory to be trained is read from the preset flash memory chip, and the double-rate synchronous dynamic random access memory to be trained is initialized.

5. The method for adapting a solid-state drive to double-speed synchronous dynamic random access memory according to claim 1, characterized in that, The step of determining the corresponding predefined structure representing the dynamic random access memory parameters from the preset firmware based on the type information includes: Based on the type information and the correspondence, a predefined structure representing the dynamic random access memory parameters is determined from the preset firmware.

6. A solid-state drive adapted to a double-data-rate synchronous dynamic random access memory device, characterized in that, include: The first information acquisition module is used to load the preset firmware and read the type information of the double-rate synchronous dynamic random access memory to be trained from the preset flash memory chip when a power-on request is received. The second information acquisition module is used to determine the corresponding predefined structure representing the parameters of the dynamic random access memory from the preset firmware based on the type information. An adaptation module is used to train the double-rate synchronous dynamic random access memory to be trained using the predefined structure, obtain the corresponding training results, and determine the signal of the double-rate synchronous dynamic random access memory to be trained as a stable signal based on the training results, thereby completing the adaptation process of the double-rate synchronous dynamic random access memory to be trained. The device is further configured to set the dynamic random access memory parameters of different double rate synchronous dynamic random access memories to corresponding software-defined structures and save them in a software-defined manner; construct a correspondence between the software-defined structures and the type information of the corresponding double rate synchronous dynamic random access memories; and offline burn the firmware package, the correspondence, and the type information to a preset flash memory chip.

7. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the solid-state drive adaptation to double-rate synchronous dynamic random access memory method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, Used for storing computer programs; wherein, when the computer program is executed by a processor, it implements the steps of the solid-state drive adaptation to double-rate synchronous dynamic random access memory method as described in any one of claims 1 to 5.

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