A carrier storage trench type bipolar transistor structure and a manufacturing method thereof

Abstract

This invention discloses a carrier storage trench bipolar transistor structure and its manufacturing method. By introducing a deep trench emitter based on the traditional CSTBT device structure, and forming a P-type layer in the peripheral region at the bottom of the trench structure below the N-type doped carrier storage layer, the problems of low breakdown voltage, high on-state power consumption, and high turn-off loss of traditional CSTBTs are effectively solved.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, specifically to a carrier storage trench bipolar transistor structure and its manufacturing method. Background Technology

[0002] Power electronics technology is the technology of changing and controlling electrical power; therefore, power electronic devices are also called power semiconductor devices. High-performance power semiconductor devices can greatly improve energy transmission efficiency and energy utilization efficiency. IGBT is a MOSFET-controlled bipolar junction transistor (BJT), which combines the advantages of low drive power of power MOSFETs and low on-state voltage drop of BJTs, and features high input impedance and low switching losses. Currently, IGBT has become one of the leading devices in modern power electronics technology.

[0003] The equivalent circuit of an IGBT is a cascaded nMOS transistor and a PNP transistor. Current amplification is achieved through the PNP transistor, and the on-state voltage drop (Von) is reduced by conductivity modulation after minority carrier injection. However, these numerous minority carriers also affect the device's turn-off capability. Ultimately, a trade-off relationship is formed between Von and turn-off loss (Eoff). The trench bipolar transistor (CSTBT) structure with a carrier storage layer greatly optimizes this trade-off relationship, becoming a major breakthrough in the history of IGBT device development. An N-type carrier storage layer (N-CS region) is introduced below the P-type base region. The hole barrier formed by the N-CS region and the N-drift region blocks holes in the N-drift region, thereby increasing the non-equilibrium carrier concentration and conductivity modulation in the entire N-drift region, reducing the on-state voltage drop of the device, and the on-state voltage drop of the CSTBT decreases with increasing CS layer doping concentration. Traditional CSTBT structures are limited by the high concentration of N-CS layers, which significantly reduces the breakdown voltage, resulting in a substantial decrease in CSTBT performance such as turn-on and turn-off losses and safe operating area. Summary of the Invention

[0004] This invention proposes a carrier storage trench bipolar transistor structure and its manufacturing method. By introducing a deep trench emitter and a P-type layer, it solves the problems of low breakdown voltage, high conduction power consumption, and high turn-off loss of traditional CSTBTs.

[0005] The method for manufacturing the carrier storage trench bipolar transistor structure of the present invention includes the following steps: in N - A P-well region is formed on the upper part of the doped silicon substrate; an N-type doped carrier storage layer is formed below the P-well region.

[0006] The silicon substrate is etched to form two spaced-apart first trenches that penetrate the P-well region and the N-type doped carrier storage layer. A first P-type layer is formed in the peripheral region at the bottom of the first trenches. A first gate oxide layer is formed to cover the bottom and sidewalls of the first trenches and the upper surface of the P-well region. A first polysilicon layer is deposited on the first gate oxide layer to completely fill the first trenches as a gate electrode. Chemical mechanical polishing is then performed, with the silicon substrate as a stop layer.

[0007] A second trench is etched between the two first trenches, penetrating the P-well region and the N-type doped carrier storage layer; a second P-type layer is formed in the peripheral region at the bottom of the second trench; a second gate oxide layer is formed to cover the bottom and sidewalls of the second trench and the upper surface of the device; a second polysilicon layer is deposited on the second gate oxide layer and completely fills the second trench to form a deep trench emitter, followed by chemical mechanical polishing with the silicon substrate as the cut-off layer;

[0008] An N-type well is formed on the upper part of the portion of the P-well region adjacent to the first trench and located between the second trench and the first trench. + Launch area; except N + P-shaped structures are formed on the upper part of other regions of the P-well outside the launch area. + Launch area; a third oxide layer is formed above the first and second trenches;

[0009] Subsequently, a third polysilicon layer is deposited to cover the upper surface of the device as the emitter; a fourth oxide layer is then deposited to cover the third polysilicon layer; a P-type collector region is formed on the back of the silicon substrate; an N-type field blocking layer is formed above the P-type collector region, wherein the first P-type layer and the second P-type layer are both located below the N-type carrier storage layer and are spaced apart from each other and not connected; the deep trench emitter, the second P-type layer, the N-type doped carrier storage layer and the P-well region constitute a self-biased pMOS.

[0010] In the carrier storage trench bipolar transistor structure manufacturing method of the present invention, preferably, the depth of the second trench is greater than the depth of the first trench.

[0011] In the method for manufacturing the carrier storage trench bipolar transistor structure of the present invention, it is preferable to form N + Launch area, P + The steps for the emitter region and the third oxide layer specifically include: depositing silicon oxide and etching to expose the surface of a portion of the P-well region adjacent to the first trench and located between the second trench and the first trench; and forming an N-type emitter region on top of the P-well region by ion implantation. + Emitter region; silicon oxide is deposited again and etched to separate the first trench and the second trench, as well as the N... + The surface of the P-well region outside the emission region is exposed; a P-well is formed on the upper part of the aforementioned P-well region by ion implantation. +Emitter region; deposit silicon oxide and etch it, leaving only the silicon oxide above the first trench and the second trench as the third oxide layer, so that the substrate surface other than the first trench and the second trench is exposed.

[0012] In the method for manufacturing the carrier storage trench bipolar transistor structure of the present invention, it is preferable to form an N-type doped carrier storage layer by ion implantation of N-type impurities, wherein the ion implantation dose is 1e13 to 1e14 / cm². 2 The injection energy is 4–6 MeV, the angle is 0°, the annealing temperature is 1000–1200℃, and the annealing time is 20–40 min.

[0013] In the method for manufacturing the carrier storage trench bipolar transistor structure of the present invention, it is preferable to form the first P-type layer by ion implantation of P-type impurities, wherein the ion implantation dose is 1e13 to 1e15 / cm. 2 The injected energy is 20–60 keV, and the angle is 0°.

[0014] In the method for manufacturing the carrier storage trench bipolar transistor structure of the present invention, it is preferable to form the second P-type layer by ion implantation of P-type impurities, wherein the ion implantation dose is 1e13 to 1e15 / cm. 2 The injection energy is 20–60 keV, the angle is 0°, the annealing temperature is 1000–1100℃, and the annealing time is 10–30 min.

[0015] The carrier storage trench bipolar transistor structure of the present invention includes: N - A doped silicon substrate has a P-well region formed on its upper part and an N-type doped carrier storage layer formed below the P-well region; two first trenches spaced apart from each other penetrate the P-well region and the N-type doped carrier storage layer; a first gate oxide layer covers the bottom and sidewalls of the first trenches; a first polysilicon layer is formed on the first gate oxide layer and completely fills the first trenches; and a first P-type layer is formed in the peripheral region of the bottom of the first trenches.

[0016] The second trench is located between the two first trenches and extends through the P-well region and the N-type doped carrier storage layer; the second gate oxide layer covers the bottom and sidewalls of the second trench; the second polysilicon layer is formed on the second gate oxide layer and completely fills the second trench to form a deep trench emitter; the second P-type layer is formed in the peripheral region of the bottom of the second trench.

[0017] N + The launch region is formed in the upper part of the P-well region adjacent to the first trench and located between the second trench and the first trench; P + The emission region is formed in the area excluding N. +Above other regions of the P-well region outside the emitter region; a third oxide layer formed above the first trench and the second trench; a third polysilicon layer covering the upper surface of the device; a fourth oxide layer covering the third polysilicon layer;

[0018] A P-type collector region is formed on the back side of the silicon substrate; an N-type field blocking layer is formed above the P-type collector region, wherein the first P-type layer and the second P-type layer are both located below the N-type carrier storage layer and are spaced apart from each other and not connected; the deep trench emitter, the second P-type layer, the N-type doped carrier storage layer and the P-well region constitute a self-biased pMOS.

[0019] In the carrier storage trench bipolar transistor structure of the present invention, preferably, the depth of the second trench is greater than the depth of the first trench.

[0020] In the carrier storage trench bipolar transistor structure of the present invention, preferably, the doping concentration of the N-type doped carrier storage layer is 1e16 to 1e18 / cm³. 2 .

[0021] In the carrier storage trench bipolar transistor structure of the present invention, preferably, the doping concentration of the first P-type layer / second P-type layer is 1e17 to 1e19 / cm³. 2 . Attached Figure Description

[0022] Figure 1 This is a flowchart of a method for manufacturing a carrier storage trench bipolar transistor structure.

[0023] Figures 2-22 This is a schematic diagram of the various stages of the manufacturing process of a carrier storage trench bipolar transistor structure. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining this invention and are not intended to limit this invention. The described embodiments are merely some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0025] In the description of this invention, it should be noted that the terms "upper," "lower," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0026] Furthermore, many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details. Unless specifically indicated below, various parts of the device may be made of materials known to those skilled in the art, or may employ materials with similar functionality developed in the future.

[0027] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

[0028] Figure 1 This is a flowchart of a method for manufacturing a carrier storage trench bipolar transistor structure. (Example:) Figure 1 As shown, the method for manufacturing a carrier storage trench bipolar transistor structure includes the following steps:

[0029] Step S1: In N - P-type impurities are implanted into a doped silicon substrate 100 to form a P-well region 101 on the upper part of the silicon substrate 100, resulting in the structure shown below. Figure 2 As shown, the ion implantation dose is 1e13~1e14 / cm². 2 The implantation energy was 200–400 keV, the angle was 0°, the annealing temperature was 950–1100℃, and the annealing time was 300–600 min. Afterwards, N-type impurities were implanted to form an N-type doped carrier storage layer (N-CS) 102 below the P-well region 101, resulting in the structure shown below. Figure 3 As shown, the injection dose is 1e13~1e14 / cm. 2 The injection energy is 4–6 MeV, the angle is 0°, the annealing temperature is 1000–1200℃, and the annealing time is 20–40 min.

[0030] Step S2: Using photoresist 103 as a masking layer, etch the silicon substrate 100 to create two spaced-apart first trenches 104 and 105 that penetrate the P-well region 101 and the N-type doped carrier storage layer 102, resulting in the structure shown below. Figure 4 As shown. The first trench has a width of 0.6 μm, a depth of 4 μm, and a spacing of 2.4 μm. Then, P-type impurities are implanted, located in the N... - The outer periphery of the bottom of the first trenches 104 and 105 in the drift region 100 forms the first P-type layers 106 and 107, resulting in the structure shown below. Figure 5 As shown, the first P-type layers 106 and 107 are formed below the N-type doped carrier storage layer 102, and are concave in shape, surrounding the bottom of the first trenches 104 and 105. The ion implantation dose is 1e14 to 1e15 / cm². 2 The injection energy is 20–60 keV, and the angle is 0°. Then, the photoresist 103 is removed, and an oxide layer, such as a 120 nm thick SiO2 layer, is grown to form the first gate oxide layer 108, covering the bottom and sidewalls of the first trenches 104 and 105, as well as the upper surface of the P-well region 101. The resulting structure is as follows: Figure 6 As shown.

[0031] Step S3: Deposit a first polysilicon layer 109 on the first gate oxide layer 108 and completely fill the first trenches 104 and 105, resulting in the structure shown below. Figure 7 As shown. Subsequent chemical mechanical polishing was performed, using a silicon substrate as a stop layer, resulting in the structure shown below. Figure 8 As shown.

[0032] Step S4: Using photoresist 103 as a masking layer, a second trench 110 is etched between the two first trenches 104 and 105, penetrating the P-well region 101 and the N-type doped carrier storage layer 102. The second trench 110 has a greater depth than the first trenches 104 and 105, meaning the bottom of the second trench 110 is located below the bottom of the first trenches 104 and 105. The resulting structure is as follows: Figure 9 As shown. Then, P-type impurities are injected, located at N... - The outer region at the bottom of the second trench 110 in the drift region 100 forms a second P-type layer 111, resulting in a structure as shown below. Figure 10 As shown, the second P-type layer 111 is formed below the N-type doped carrier storage layer 102, and is concave in shape, surrounding the bottom of the second trench 110. The ion implantation dose is 1e14–1e15 / cm². 2 The implantation energy is 20–60 keV, the angle is 0°, the annealing temperature is 1000–1100℃, and the annealing time is 10–30 min. Each P-type layer is discontinuous along the transverse direction of the device, and there is an N-type layer between adjacent P-type layers. -Drift region. Then, the photoresist 103 is removed, and a second gate oxide layer 112, such as SiO2 with a thickness of 25 nm, is grown to cover the bottom and sidewalls of the second trench 110 and the upper surface of the device, resulting in the structure shown below. Figure 11 As shown.

[0033] Step S5: A second polysilicon layer 113 is deposited on the second gate oxide layer 112 and completely fills the second trench 110, resulting in the structure shown below. Figure 12 As shown. Subsequent chemical mechanical polishing was performed, using a silicon substrate as a stop layer, resulting in the structure shown below. Figure 13 As shown.

[0034] Step S6: Deposit silicon oxide 114, and etch silicon oxide 114 using photoresist 103 as a masking layer, exposing the surface of a portion of the P-well region 101 adjacent to the first trenches 104, 105 and located between the second trench 110 and the first trenches 104, 105, resulting in the structure shown below. Figure 14 As shown. An N-type impurity is implanted into the upper part of the P-well region 101 to form an N-type impurity. + Launch zone 116, the resulting structure is as follows Figure 15 As shown. The ion implantation dose is 1e15–1e16 / cm². 2 The injection energy is 30–60 keV, the angle is 0°, the annealing temperature is 900–1100℃, and the annealing time is 15–40 min. Silicon oxide 114 is deposited again, and photoresist 103 is used as a masking layer to etch the silicon oxide 114, so that, except for the first trench 104, 105, the second trench 110, and N... + The substrate surface outside the emitter region 116 is exposed, that is, the surface of the P-well region 101 is exposed, and the resulting structure is as follows. Figure 16 As shown.

[0035] Step S7: Using photoresist 103 as a stop layer, P-type impurities are implanted to form a P-type impurity on the upper part of the P-well region. + Launch zone 118, the resulting structure is as follows Figure 17 As shown. The ion implantation dose is 1e15–1e16 / cm². 2 The injection energy is 30–80 keV, the angle is 0°, the annealing temperature is 900–1100℃, and the annealing time is 20–40 min. Then, the photoresist 103 is removed and silicon oxide 114 is deposited. Next, the silicon oxide 114 is etched using the photoresist 103 as a masking layer, leaving only the silicon oxide above the first trenches 104, 105 and the second trench 110 as the third oxide layer, exposing the substrate surface except for the first trenches 104, 105 and the second trench 110. The resulting structure is as follows. Figure 18 As shown.

[0036] Step S8: Remove photoresist 103, deposit third polysilicon layer 121, and remove excess third polysilicon layer 121 using CMP to obtain emitter polysilicon. The resulting structure is as follows. Figure 19 As shown. Subsequently, silicon oxide is deposited to form the fourth oxide layer 122, and the resulting structure is as follows. Figure 20 As shown.

[0037] Step S9: A P-type collector region 123 is formed on the back side by implanting P-type impurities, resulting in the structure shown below. Figure 21 As shown. The ion implantation dose is 1e12–1e13 / cm². 2 The injection energy is 40–100 keV, and the angle is 0°. An N-type field blocking layer 124 is formed above the P-type collector region 123 by injecting N-type impurities, resulting in the structure shown below. Figure 22 As shown. The ion implantation dose is 1e12–1e13 / cm². 2 The injection energy is 400–1000 keV, the angle is 0°, the annealing temperature is 1200–1250℃, and the annealing time is 10–30 min.

[0038] like Figure 22 As shown, the carrier storage trench bipolar transistor structure of this application includes: N - A doped silicon substrate 100 has a P-well region 101 formed on its upper part, and an N-type doped carrier storage layer 102 is formed below the P-well region 101; wherein the doping concentration of the N-type doped carrier storage layer is 1e16~1e18 / cm. 2 .

[0039] Two spaced-apart first trenches 104 and 105 penetrate the P-well region 101 and the N-type doped carrier storage layer 102; a first gate oxide layer 108 covers the bottom and sidewalls of the first trenches 104 and 105; a first polysilicon layer 109 is formed on the first gate oxide layer 108 and completely fills the first trenches 104 and 105, serving as a gate electrode; first P-type layers 106 and 107 are formed in the peripheral region of the bottom of the first trenches 104 and 105 and are located below the N-type doped carrier storage layer 102, wherein the doping concentration of the first P-type layer is 1e17 to 1e19 / cm³. 2 .

[0040] A second trench 110 is located between two first trenches 104 and 105, penetrating the P-well region 101 and the N-type doped carrier storage layer 102; a second gate oxide layer 112 covers the bottom and sidewalls of the second trench 110; a second polysilicon layer 113 is formed on the second gate oxide layer 112 and completely fills the second trench 110, serving as a deep trench emitter; a second P-type layer 111 is formed in the peripheral region of the bottom of the second trench 110 and is located below the N-type doped carrier storage layer 102, wherein the doping concentration of the first P-type layer is 1e17 to 1e19 / cm³. 2 The second P-type layer 111 is spaced apart from the first P-type layers 106 and 107 and is not connected to them.

[0041] N + The launch region 116 is formed on the upper part of the portion of the P-well region 101 adjacent to the first trenches 104, 105 and located between the second trench 110 and the first trenches 104, 105; P + Launch zone 118, formed in addition to N + Above other regions of the P-well region 101 outside the emission region 116; a third oxide layer 114 is formed above the first trench 104, 105 and the second trench 110.

[0042] The third polysilicon layer 121 covers the third oxide layer 114 and extends to cover the upper surface of the silicon substrate 100, serving as an emitter; the fourth oxide layer 122 covers the third polysilicon layer 121.

[0043] A P-type collector region 123 is formed on the back side of the silicon substrate 100; an N-type field blocking layer 124 is formed above the P-type collector region 123.

[0044] The introduction of deep trench emitter and P-type layer can shield the influence of N-type doped carrier storage layer on device breakdown characteristics, and can increase the doping concentration of N-type doped carrier storage layer to reduce device on-state voltage drop, thereby further improving the trade-off relationship between device on-state voltage drop Vceon and turn-off loss Eoff.

[0045] Simultaneously, the deep trench emitter, the second P-type layer 111 located at the bottom periphery of the deep trench emitter, the N-type doped carrier storage layer 102, and the P-well region 101 constitute a self-biased pMOS. In the on-state, the potential of the N-type doped carrier storage layer 102 increases with the increase of the collector voltage, increasing to the absolute value of the pMOS threshold voltage (|V). thPWhen the pMOS transistor is activated, a hole channel is formed, the pMOS transistor turns on, and the second P-type layer is connected to the emitter. As a result, the potentials of the second P-type layer 111 and the N-type doped carrier storage layer 102 are clamped to a low potential, allowing the nMOS channel to saturate earlier, thereby reducing the saturation current density and improving the device's short-circuit safety capability. Furthermore, the P-type layer can shield the gate electrode and the N-type doped carrier storage layer. - The coupling effect of the drift region can effectively reduce the gate-collector capacitance (Miller capacitance), thereby improving the switching speed of the device and reducing switching losses. During device turn-off, excess holes in the drift region can be quickly removed through the pMOS structure, thereby improving the switching speed of the device and further reducing the switching losses.

Claims

1. A method for manufacturing a carrier storage trench type bipolar transistor structure, characterized in that, Includes the following steps: In N - A P-well region is formed on the upper part of the doped silicon substrate; an N-type doped carrier storage layer is formed below the P-well region. The silicon substrate is etched to form two spaced-apart first trenches that penetrate the P-well region and the N-type doped carrier storage layer. A first P-type layer is formed in the peripheral region at the bottom of the first trenches. A first gate oxide layer is formed to cover the bottom and sidewalls of the first trenches and the upper surface of the P-well region. A first polysilicon layer is deposited on the first gate oxide layer and completely fills the first trenches to form a gate electrode. Subsequently, chemical mechanical polishing is performed, with the P-well region as the cutoff layer. A second trench is etched between the two first trenches, penetrating the P-well region and the N-type doped carrier storage layer; a second P-type layer is formed in the peripheral region at the bottom of the second trench; a second gate oxide layer is formed, covering the bottom and sidewalls of the second trench and the upper surface of the device; a second polysilicon layer is deposited on the second gate oxide layer and completely fills the second trench to form a deep trench emitter, followed by chemical mechanical polishing, with the P-well region as the cutoff layer; An N-type well is formed on the upper part of the portion of the P-well region adjacent to the first trench and located between the second trench and the first trench. + Launch area; except N + P-shaped structures are formed on the upper part of other regions of the P-well outside the launch area. + Launch area; a third oxide layer is formed above the first and second trenches; Subsequently, a third polysilicon layer is deposited to cover the upper surface of the device, serving as the emitter; then a fourth oxide layer is deposited to cover the third polysilicon layer. A P-type collector region is formed on the back side of the silicon substrate; an N-type field blocking layer is formed above the P-type collector region. The first P-type layer and the second P-type layer are both located below the N-type carrier storage layer and are spaced apart from each other and not connected; the deep trench emitter, the second P-type layer, the N-type doped carrier storage layer and the P-well region constitute a self-biased pMOS.

2. The method for manufacturing a carrier storage trench bipolar transistor structure according to claim 1, characterized in that, The second trench is deeper than the first trench.

3. The method for manufacturing a carrier storage trench bipolar transistor structure according to claim 1, characterized in that, Forming N + Launch area, P + The specific steps for the emission region and the third oxide layer include: Silicon oxide is deposited and etched to expose the surface of a portion of the P-well region adjacent to the first trench and located between the second trench and the first trench. An N-type nanotube is then formed on the upper part of the P-well region via ion implantation. + Launch area; Silicon oxide was deposited again and etched, so that except for the first trench and the second trench, as well as N... + The surface of the P-well region outside the emitter region is exposed, and P-wells are formed on the upper part of the P-well region by ion implantation. + Launch area; Silicon oxide is deposited and etched, leaving only the silicon oxide above the first and second trenches as the third oxide layer, thus exposing the substrate surface other than the first and second trenches.

4. The method for manufacturing a carrier storage trench bipolar transistor structure according to claim 1, characterized in that, The N-type doped carrier storage layer is formed by ion implantation of N-type impurities, wherein the ion implantation dose is 1e13~1e14 / cm. 2 The injection energy is 4~6MeV, the angle is 0°, the annealing temperature is 1000~1200℃, and the annealing time is 20~40min.

5. The method for manufacturing a carrier storage trench bipolar transistor structure according to claim 1, characterized in that, The first P-type layer is formed by ion implantation of P-type impurities, wherein the ion implantation dose is 1e13~1e15 / cm. 2 The injected energy is 20~60keV, and the angle is 0°.

6. The method for manufacturing a carrier storage trench bipolar transistor structure according to claim 1, characterized in that, The second P-type layer is formed by ion implantation of P-type impurities, wherein the ion implantation dose is 1e13~1e15 / cm. 2 The injection energy is 20~60keV, the angle is 0°, the annealing temperature is 1000~1100℃, and the annealing time is 10~30min.

7. A carrier storage trench type bipolar transistor structure, characterized in that, include: N - A doped silicon substrate has a P-well region formed on its upper part and an N-type doped carrier storage layer formed below the P-well region. Two first trenches spaced apart from each other, penetrating the P-well region and the N-type doped carrier storage layer; a first gate oxide layer covering the bottom and sidewalls of the first trenches; a first polysilicon layer formed on the first gate oxide layer and completely filling the first trenches to form a gate electrode; and a first P-type layer formed in the peripheral region at the bottom of the first trenches. The second trench is located between the two first trenches and extends through the P-well region and the N-type doped carrier storage layer; the second gate oxide layer covers the bottom and sidewalls of the second trench; the second polysilicon layer is formed on the second gate oxide layer and completely fills the second trench to form a deep trench emitter; the second P-type layer is formed in the peripheral region at the bottom of the second trench. N + The launch region is formed in the upper part of the P-well region adjacent to the first trench and located between the second trench and the first trench; P + The emission region is formed in the area excluding N. + Above other areas of the P-well region outside the launch area; a third oxide layer, formed above the first and second trenches; A third polysilicon layer covers the upper surface of the device and serves as the emitter; a fourth oxide layer covers the third polysilicon layer. A P-type collector region is formed on the back side of the silicon substrate; an N-type field blocking layer is formed above the P-type collector region. The first P-type layer and the second P-type layer are both located below the N-type carrier storage layer and are spaced apart from each other and not connected. The deep trench emitter, the second P-type layer, the N-type doped carrier storage layer, and the P-well region constitute a self-biased pMOS.

8. The carrier storage trench bipolar transistor structure according to claim 7, characterized in that, The second trench is deeper than the first trench.

9. The carrier storage trench bipolar transistor structure according to claim 7, characterized in that, The doping concentration of the N-type doped carrier storage layer is 1e16~1e18 / cm³. 3 .

10. The carrier storage trench bipolar transistor structure according to claim 7, characterized in that, The doping concentration of the first P-type layer / second P-type layer is 1e17~1e19 / cm. 3 .

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