Self-aligned process suitable for SiC power devices

Abstract

The present application relates to a self-alignment process suitable for SiC power device, which comprises: providing a device substrate; preparing a side wall window layer above the device substrate, wherein the side wall window layer is supported on an etching stop layer on the device substrate; patterning the side wall window layer to form a plurality of side wall windows penetrating the side wall window layer, wherein the side wall of the side wall window is inclined to the surface of the etching stop layer; depositing a side wall material to obtain a side wall base at least filling the side wall window; removing the side wall window layer to form a plurality of side wall base isolation windows isolating the side wall base; preparing an implantation blocking layer, wherein the implantation blocking layer at least covers the side wall of the side wall base to block ion implantation when the implantation blocking layer covers the side wall of the side wall base. The side wall prepared by the present application can accurately control ion implantation and improve the control accuracy of the channel length of the SiC power device, and is compatible with the existing process.

Description

Technical Field

[0001] This invention relates to a self-alignment process, and more particularly to a self-alignment process suitable for SiC power devices. Background Technology

[0002] SiC power devices, such as SiC MOSFETs, utilize self-alignment processes derived from Si MOSFETs. Common self-alignment processes typically involve oxidation and etching. There is no inherent advantage or disadvantage between oxidation- or etching-based self-alignment processes; the choice primarily depends on the fabrication capabilities of the fab.

[0003] Figure 1 The image shows an embodiment of a self-alignment process employing a Spacer (sidewall) structure. Figure 1 In the process, a sidewall support layer 102 is formed on the process substrate 101, and a rounded shoulder sidewall 103 is formed on the sidewall support layer 102 by etching. During self-alignment, the rounded shoulder sidewall 103 has serious hidden dangers. In particular, when there are fluctuations in the process, the online monitoring CD cannot ensure that the position of the edge of the rounded shoulder sidewall 103 blocks high-energy ions. Once ions are implanted in the area of ​​the rounded shoulder sidewall 103, leakage will occur in the channel of the MOSFET device, which will lead to damage to the MOSFET device during operation and seriously affect the reliability of the MOSFET device during operation. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a self-aligned process suitable for SiC power devices. The sidewalls prepared by this process can precisely control ion implantation, improve the control accuracy of the channel length of SiC power devices, and are compatible with existing processes, making it safe and reliable.

[0005] According to the technical solution provided by the present invention, a self-alignment process suitable for SiC power devices is provided, the self-alignment process comprising:

[0006] Provide device substrates;

[0007] A sidewall window layer is prepared above the device substrate, wherein the sidewall window layer is supported on an etch stop layer on the device substrate;

[0008] The aforementioned sidewall window layer is patterned to form a plurality of sidewall windows that penetrate the sidewall window layer, wherein the sidewalls of the sidewall windows are inclined relative to the surface of the etching termination layer.

[0009] Sidewall material deposition is performed to obtain a sidewall matrix that at least fills the sidewall window;

[0010] Remove the aforementioned sidewall window layer to form several sidewall substrate isolation windows that isolate the sidewall substrate;

[0011] An implantation barrier layer is prepared, wherein the implantation barrier layer at least covers the sidewall of the sidewall substrate to block ion implantation.

[0012] The angle between the sidewall of the sidewall substrate and the surface of the etching termination layer is 80° to 87°, and the width of the sidewall substrate gradually increases along the direction from the bottom of the sidewall substrate to the top of the sidewall substrate.

[0013] The material of the etching stop layer includes polycrystalline silicon or silicon nitride, and the thickness of the etching stop layer is 10 nm to 100 nm.

[0014] The material of the sidewall window layer includes silicon dioxide.

[0015] When preparing the sidewall matrix by depositing sidewall material, the process includes:

[0016] Sidewall material deposition is performed to obtain a sidewall deposition layer, wherein the sidewall deposition layer fills the sidewall window and covers the sidewall window layer;

[0017] The sidewall deposit layer covering the sidewall window layer is removed to obtain the sidewall matrix filling the sidewall window, wherein,

[0018] When removing the sidewall deposit layer on the cover sidewall window layer, if the cell pitch is large, the removal method includes CMP or mask removal; if the cell pitch is small, the removal method includes reverse etching.

[0019] The implantation barrier layer is made of silicon dioxide, and its thickness is consistent with the channel width of the power device.

[0020] The deposited sidewall material includes polycrystalline silicon.

[0021] A self-alignment process suitable for SiC power devices, the self-alignment process comprising:

[0022] Provide device substrates;

[0023] A sidewall material layer is prepared above the device substrate, wherein the sidewall material layer is supported on the etching stop layer of the device substrate;

[0024] The aforementioned sidewall material layer is graphically represented to obtain several sidewall layer windows that penetrate the sidewall material layer, and several mutually isolated sidewall unit bodies are formed through the sidewall layer windows.

[0025] Prepare a barrier oxide layer, wherein the barrier oxide layer covers the sidewall unit, the bottom of the sidewall layer window, and the sidewalls of the sidewall unit and the sidewall layer window respectively;

[0026] Along the direction from the bottom of the sidewall unit to the top of the sidewall unit, the thickness of the barrier oxide layer covering the sidewall of the sidewall unit gradually increases.

[0027] In preparing the barrier oxide layer, the preparation process includes several sequential preparation steps, wherein,

[0028] Each preparation step includes sequential deposition of oxidized material, high-temperature oxidation, and post-oxidation cleaning.

[0029] The barrier oxide layer is a silicon dioxide layer.

[0030] Advantages of the present invention: The angle between the sidewall of the sidewall substrate and the surface of the etching termination layer is 80° to 87°, and the width of the sidewall substrate gradually increases along the direction from the bottom of the sidewall substrate to the top of the sidewall substrate, which means that the round shoulder sidewall of the prior art will not be formed, thereby avoiding the leakage phenomenon of the existing round shoulder sidewall during ion implantation. In other words, the sidewall can accurately control ion implantation, improve the control accuracy of the channel length of SiC power devices, and is compatible with existing processes, safe and reliable. Attached Figure Description

[0031] Figure 1 This is an embodiment of an existing rounded shoulder sidewall.

[0032] Figures 2-9 This is a cross-sectional view showing the specific process steps of a self-alignment process according to the present invention, wherein,

[0033] Figure 2 This is a cross-sectional view of an embodiment of the substrate of the device of the present invention.

[0034] Figure 3 This is a cross-sectional view of one embodiment of the sidewall window layer prepared according to the present invention.

[0035] Figure 4 This is a cross-sectional view of one embodiment of the present invention after graphical representation of the side wall window layer.

[0036] Figure 5 This is a cross-sectional view of one embodiment of the present invention after the deposition of the sidewall material.

[0037] Figure 6 This is a cross-sectional view of one embodiment of the present invention after the removal of the sidewall deposit layer on the covered sidewall window layer.

[0038] Figure 7 This is a cross-sectional view of one embodiment of the present invention after removing the side wall window layer.

[0039] Figure 8 This is a cross-sectional view of one embodiment of the invention after the injection barrier layer has been prepared.

[0040] Figure 9This is a cross-sectional view of one embodiment of the invention after retaining the injection barrier layer covering the sidewall of the substrate.

[0041] Figures 10-11 This is a cross-sectional view showing the specific process steps of another self-alignment process according to the present invention, wherein,

[0042] Figure 10 This is a cross-sectional view of one embodiment of the present invention, showing the graphical representation of the sidewall material layer.

[0043] Figure 11 This is a cross-sectional view of one embodiment of the present invention after obtaining the barrier oxide layer.

[0044] Figure reference numerals: 10-Device substrate, 11-Etching stop layer, 12-Sidewall window layer, 13-Sidewall window, 14-Sidewall deposition layer, 15-Sidewall substrate, 16-Sidewall substrate isolation window, 17-Impplant barrier layer, 18-Sidewall cell, 19-Sidewall layer window, 20-Barrier oxide layer. Detailed Implementation

[0045] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0046] To enable precise control of ion implantation in the fabricated sidewalls and improve the control accuracy of the channel length in SiC power devices, in one embodiment of the present invention, the self-alignment process suitable for SiC power devices includes:

[0047] Provide device substrate 10;

[0048] A sidewall window layer 12 is formed above the device substrate 10, wherein the sidewall window layer 12 is supported on the etching stop layer 11 on the device substrate 10;

[0049] The sidewall window layer 12 described above is patterned to form a plurality of sidewall windows 13 that penetrate the sidewall window layer 12, wherein the sidewalls of the sidewall windows 13 are inclined relative to the surface of the etching termination layer 11.

[0050] Sidewall material deposition is performed to obtain a sidewall substrate 15 that at least fills the sidewall window 13;

[0051] Remove the aforementioned sidewall window layer 12 to form a plurality of sidewall substrate isolation windows 16 that isolate the sidewall substrate 15;

[0052] An implantation barrier layer 17 is prepared, wherein the implantation barrier layer 17 at least covers the sidewall of the sidewall substrate 15 to block ion implantation.

[0053] Figures 2-9The following is a process step diagram of the self-alignment process in this embodiment. The process in this embodiment will be described in detail below with reference to the process step diagram.

[0054] Figure 2 The image shows one embodiment of the device substrate 10, which can be a SiC material substrate. In this case, the power device fabricated is a SiC power device.

[0055] To fabricate the sidewall window layer 12, an etch stop layer 11 is typically fabricated on the device substrate 10. Specifically, the material of the etch stop layer 11 includes polysilicon or silicon nitride, and the thickness of the etch stop layer 11 is 10 nm to 100 nm. The material type and thickness of the etch stop layer 11 can be selected according to actual needs to meet the requirements of etch termination. The etch stop layer 11 can generally be fabricated on the device substrate 10 using deposition or growth processes.

[0056] After obtaining the etch stop layer 11, a sidewall window layer 12 is prepared on the etch stop layer 11 using a deposition / growth process. The sidewall window layer 12 covers the etch stop layer, such as... Figure 3 As shown. In specific implementation, the material of the sidewall window layer 12 includes silicon dioxide, and the thickness of the sidewall window layer 12 is related to the dose and energy of ion implantation; for example, if the implantation dose is 1*10... 13 cm -2 ~1*10 15 cm -2 At that time, the thickness of the sidewall window layer 12 was 800nm ​​to 1500nm.

[0057] After the sidewall window layer 12 is prepared, it is patterned to prepare a plurality of sidewall windows 13, which penetrate the sidewall window layer 12, such as... Figure 4 As shown. The sidewall window 13 allows the etching termination layer 11 corresponding to the sidewall window 13 to be exposed, and the distribution of the sidewall window 13 can be selected according to actual needs.

[0058] After forming the sidewall window 13, a sidewall corresponding to the sidewall window 13 is obtained. In specific implementation, the sidewall of the sidewall window is inclined relative to the surface of the etching termination layer 11. The inclination angle of the sidewall window sidewall determines the angle at which the final sidewall substrate 15 is formed. The inclination angle can be adjusted to 80° to 87° according to the process. The size of the inclination angle is consistent with the inclination angle of the final sidewall substrate 15 corresponding to the etching termination layer 11. The specific process and the size of the inclination angle are selected according to the actual application requirements. The inclination angle of the sidewall window sidewall and the inclination angle of the sidewall substrate 15 prepared based on the inclination angle of the sidewall window can be achieved by adjusting the process of the etching machine pressure, gas, gas flow rate, etc. The specific process conditions and procedures can be selected as needed to prepare the required sidewall substrate 15.

[0059] After patterning the sidewall window layer 12, sidewall material is deposited, including polysilicon. The sidewall material is deposited to obtain a sidewall substrate 15 filling the sidewall window, which can be obtained through the following process steps, specifically including:

[0060] Sidewall material deposition is performed to obtain sidewall deposition layer 14, wherein sidewall deposition layer 14 fills the sidewall window and covers the sidewall window layer 12;

[0061] The sidewall deposit layer 14 covering the sidewall window layer 12 is removed to obtain the sidewall substrate 15 filling the sidewall window 13, wherein,

[0062] When removing the sidewall deposit layer 14 on the cover sidewall window layer 12, if the cell pitch is large, the removal method includes CMP or mask removal; if the cell pitch is small, the removal method includes reverse etching.

[0063] Specifically, polycrystalline silicon deposition can be performed using deposition processes commonly used in this technical field. The resulting sidewall deposition layer 14 generally covers the sidewall window layer 12, and of course, it will also fill the sidewall window 13, such as... Figure 5 As shown.

[0064] To form the sidewall substrate 15, the sidewall deposition layer 14 needs to be partially removed. The specific removal process is related to the cell pitch. In one embodiment of the present invention, a cell pitch within 1 μm is considered small, while a cell pitch greater than 1 μm is considered large. Specifically, the cell pitch is the length of the cell, also known as the cell pitch.

[0065] The specific process conditions and procedures for CMP, mask removal, or reverse etching can be selected according to actual needs. After removal, the sidewall window layer 12 covered by the sidewall deposition layer 14 is exposed, such as... Figure 6As shown. Specifically, mask removal is used, that is, a mask layer is prepared on the sidewall deposition layer 14, and by patterning the mask layer, the sidewall deposition layer 14 covering the sidewall window layer 12 is etched and removed by utilizing the blocking effect of the mask.

[0066] The reverse etching process, also known as etch back, specifically refers to indiscriminate etching without any mask. By utilizing the loading effect, different parts are etched at different rates, thereby removing the sidewall deposit layer 14 covering the sidewall window layer 12.

[0067] Remove the aforementioned sidewall window layer 12. If, as mentioned above, the sidewall window layer 12 is a silicon dioxide layer, hydrofluoric acid solution can be used to remove it. The concentration of the hydrofluoric acid solution can be selected as needed to ensure the removal of the sidewall window layer 12. Figure 7 As shown. Figure 7 In the process, after removing the sidewall window layer 12, several independent sidewall substrates 15 are formed on the etching termination layer 11. The original sidewall window layer 12 is used to form a sidewall substrate isolation window 16, and adjacent sidewall substrates 15 are isolated by the sidewall substrate isolation window 16.

[0068] As can be seen from the above process, the angle between the sidewall of the sidewall substrate 15 and the surface of the etching termination layer 11 is 80° to 87°, and the width of the sidewall substrate 15 gradually increases along the direction from the bottom of the sidewall substrate 15 to the top of the sidewall substrate 15. The bottom of the sidewall substrate 15 specifically refers to the end that contacts the etching termination layer 11.

[0069] After obtaining the sidewall substrate 15, the implantation barrier layer 17 is prepared. Generally, the material of the implantation barrier layer 17 includes a silicon dioxide layer, and the thickness of the implantation barrier layer 17 is consistent with the channel width of the power device. In specific implementation, when preparing the implantation barrier layer 17, the implantation barrier layer 17 covers the etching stop layer 11 and covers the top surface and corresponding sidewalls of the sidewall substrate 15, such as... Figure 8 As shown.

[0070] To meet the ion implantation conditions, the implantation barrier layer 17 needs to be patterned using a technique commonly used in this field. This involves retaining only the implantation barrier layer 17 on the sidewall of the substrate 15 covering the sidewall, while removing all other implantation barrier layers 17. Figure 9 As shown.

[0071] In specific implementation, the aforementioned power device can be an IGBT type device or a MOSFET type device. For the power device, during the fabrication process... Figure 7 After the sidewall substrate 15 and the sidewall substrate isolation window 16 are installed, impurity ion implantation is required to form a base region within the device substrate 10. The implantation dose can be selected as 1*10.12 ~1*10 15 cm -2 .

[0072] In order to fabricate the source or emitter region of power devices, in the formation of Figure 9 After the implantation barrier layer 17 is applied, impurity ions are implanted to form the source region, thereby forming the source region after implantation. The ion implantation dose for forming the source region can be 1*102. 13 ~1*10 15 cm -2 During ion implantation to form the source region, the blocking effect of the implantation barrier layer 17 can prevent leakage current in the conductive channel of the power device.

[0073] After the source or emitter region of the power device is formed, the etch stop layer 11 and the like on the device substrate 10 are removed so that the front side of the device substrate 10 can be processed with the required front cell process to prepare the required front cell structure. The process conditions and methods for preparing the front cell structure can be selected according to actual needs, so as to form the required front cell.

[0074] Furthermore, the self-alignment process can also be implemented in other embodiments. In another embodiment, the self-alignment process includes:

[0075] Provide device substrate 10;

[0076] A sidewall material layer is prepared on the device substrate 10, wherein the sidewall material layer is supported on the etch stop layer 11 of the device substrate 10;

[0077] The aforementioned sidewall material layer is graphically represented to obtain several sidewall layer windows 19 that penetrate the sidewall material layer, and several mutually isolated sidewall unit bodies 18 are formed through the sidewall layer windows 19.

[0078] A barrier oxide layer 20 is prepared, wherein the barrier oxide layer 20 covers the sidewall unit 18, the bottom of the sidewall layer window 19, and the sidewalls of the sidewall unit 18 and the sidewall layer window 19 respectively.

[0079] Along the direction from the bottom of the sidewall unit 18 to the top of the sidewall unit 18, the thickness of the barrier oxide layer 20 covering the sidewall of the sidewall unit 18 gradually increases.

[0080] Specifically, the device substrate 10 and the etching stop layer 11 can be referred to the above. Figures 2-9 The corresponding explanations will not be repeated here. The sidewall material layer is generally a polycrystalline silicon layer, and the fabrication process conditions and thickness of the polycrystalline silicon layer can be selected according to actual needs.

[0081] After graphically representing the sidewall material layer, sidewall layer window 19 is obtained. Sidewall layer window 19 extends through the sidewall material layer, as shown below. Figure 10 As shown. The sidewall of the sidewall layer window 19 should be as straight as possible. The angle between the sidewall of the sidewall layer window 19 and the etching termination layer 11 is usually selected to be 87° to 90°.

[0082] In practice, after obtaining the sidewall window 19, impurity ion implantation is performed on the device substrate 10 to form the source or emitter region of the power device after implantation.

[0083] After patterning the sidewall material layer, a barrier oxide layer 20 needs to be prepared, which is a silicon dioxide layer. Specifically, the preparation process for the barrier oxide layer 20 includes several sequential preparation steps, wherein...

[0084] Each preparation step includes sequential deposition of oxidized material, high-temperature oxidation, and post-oxidation cleaning.

[0085] In this embodiment, after the barrier oxide layer 20 is prepared through multiple preparation processes, the thickness of the barrier oxide layer 20 covering the sidewall of the sidewall unit 18 gradually increases, thus forming the above-mentioned sidewall substrate 15 structure.

[0086] Specifically, when depositing oxide materials, SACVD or CVD can be used, but equipment with poor conformality is required. The thickness of the deposited silica film can be 50 nm. For high-temperature oxidation, the oxidation temperature can be 900°C, and the oxidation time can be 1 hour. During oxidation cleaning, HF (hydrofluoric acid) or BOE (a buffer solution of hydrofluoric acid) can be used to remove the silica (deposited and oxidized silica). This process can be repeated multiple times as needed. For example, if it is necessary to prevent the oxide layer 20 from forming an 84° angle on the sidewall of the sidewall window 19, approximately two such processes are required.

[0087] After forming the aforementioned barrier oxide layer 20, a similar structure can be formed. Figure 7 The structure allows for subsequent ion implantation to form a base region within the device substrate 10.

[0088] As can be seen from the above description, after the base region is formed in the device substrate 10, the etching stop layer 11 on the device substrate 10 needs to be removed so that the required front cell process can be performed on the front side of the device substrate 10 to prepare the required front cell structure.

Claims

1. A self-aligned process suitable for SiC power devices, characterized in that, The self-alignment process includes: Provide device substrates; A sidewall window layer is prepared above the device substrate, wherein the sidewall window layer is supported on an etch stop layer on the device substrate; The aforementioned sidewall window layer is patterned to form a plurality of sidewall windows that penetrate the sidewall window layer, wherein the sidewalls of the sidewall windows are inclined relative to the surface of the etching termination layer. Sidewall material deposition is performed to obtain a sidewall matrix that at least fills the sidewall window; Remove the aforementioned sidewall window layer to form several sidewall substrate isolation windows that isolate the sidewall substrate; An implantation barrier layer is prepared, wherein the implantation barrier layer at least covers the sidewall of the sidewall substrate to block ion implantation by means of the implantation barrier layer covering the sidewall of the sidewall substrate; The angle between the sidewall of the sidewall substrate and the surface of the etching termination layer is 80°~87°, and the width of the sidewall substrate gradually increases along the direction from the bottom of the sidewall substrate to the top of the sidewall substrate.

2. The self-aligned process suitable for SiC power devices according to claim 1, characterized in that: The etching stop layer is made of polycrystalline silicon or silicon nitride, and the thickness of the etching stop layer is 10 nm to 100 nm.

3. The self-aligned process suitable for SiC power devices according to claim 1, characterized in that: The material of the sidewall window layer includes silicon dioxide.

4. The self-aligned process suitable for SiC power devices according to any one of claims 1 to 3, characterized in that, When preparing the sidewall matrix by depositing sidewall material, the process includes: Sidewall material deposition is performed to obtain a sidewall deposition layer, wherein the sidewall deposition layer fills the sidewall window and covers the sidewall window layer; The sidewall deposit layer covering the sidewall window layer is removed to obtain the sidewall matrix filling the sidewall window, wherein, When removing the sidewall deposit layer on the cover sidewall window layer, if the cell pitch is large, the removal method includes CMP or mask removal; if the cell pitch is small, the removal method includes reverse etching.

5. The self-aligned process suitable for SiC power devices according to any one of claims 1 to 3, characterized in that: The implantation barrier layer is made of silicon dioxide, and its thickness is consistent with the channel width of the power device.

6. The self-aligned process suitable for SiC power devices according to any one of claims 1 to 3, characterized in that: The deposited sidewall material includes polycrystalline silicon.

7. A self-aligned process suitable for SiC power devices, characterized in that, The self-alignment process includes: Provide device substrates; A sidewall material layer is prepared above the device substrate, wherein the sidewall material layer is supported on the etching stop layer of the device substrate; The aforementioned sidewall material layer is graphically represented to obtain several sidewall layer windows that penetrate the sidewall material layer, and several mutually isolated sidewall unit bodies are formed through the sidewall layer windows. Prepare a barrier oxide layer, wherein the barrier oxide layer covers the sidewall unit, the bottom of the sidewall layer window, and the sidewall of the sidewall unit and the sidewall layer window respectively; Along the direction from the bottom of the sidewall unit to the top of the sidewall unit, the thickness of the barrier oxide layer covering the sidewall of the sidewall unit gradually increases.

8. The self-aligned process suitable for SiC power devices according to claim 7, characterized in that, in The preparation process for the barrier oxide layer includes several sequential preparation steps, among which, Each preparation step includes sequential deposition of oxidized material, high-temperature oxidation, and post-oxidation cleaning.

9. The self-aligned process suitable for SiC power devices according to claim 7 or 8, characterized in that, The barrier oxide layer is a silicon dioxide layer.

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