P-type back contact battery structure, manufacturing method, and solar cell

Abstract

This invention relates to the field of solar cell technology, specifically providing a P-type back-contact cell structure, fabrication method, and solar cell. The structure includes a P-type monocrystalline silicon substrate, with a locally doped region on the front side and a first doped region and a second doped region on the back side; a first tunneling oxide layer disposed on the locally doped region; a second tunneling oxide layer and a first intrinsic amorphous silicon layer sequentially disposed on the first doped region; a second intrinsic amorphous silicon layer disposed on the second doped region; a first electrode passing through the first intrinsic amorphous silicon layer and making electrical contact with the second tunneling oxide layer; and a second electrode passing through the second intrinsic amorphous silicon layer and making electrical contact with the back side of the P-type monocrystalline silicon substrate. This invention enhances front-side passivation by providing a first tunneling oxide layer on the front side of the P-type monocrystalline silicon substrate, and further improves back-side passivation by providing an intrinsic amorphous silicon layer, thereby effectively improving the conversion efficiency of the P-type back-contact cell.

Description

Technical Field

[0001] This invention belongs to the field of solar cell technology, and particularly relates to a P-type back contact cell structure, manufacturing method and solar cell. Background Technology

[0002] The structure of a P-type back contact battery is as follows: Figure 1 As shown, this is a novel battery structure that uses a P-type silicon wafer as a substrate, with no electrodes obstructing the front side, and designs both the emitter and base electrodes (positive and negative electrodes) on the back of the battery. The electrodes of the P-type back contact battery can be Al positive electrodes and Ag negative electrodes. The presence of the Al positive electrode greatly reduces the use of precious metals. In addition, Al also has a self-doping function, so no doping is required under the Al electrode, simplifying the process and not significantly affecting the conversion efficiency.

[0003] However, in P-type back-contact solar cells, the front side has no electrode shielding, and charge carriers need to cross the silicon substrate to reach the back side of the silicon wafer for separation. Recombination is significant during this crossing process. Typically, a front passivation film is used to reduce recombination between the front side and the silicon substrate, and a rear passivation film is used to passivate the Al electrode. However, the insufficient passivation performance of the front surface and the Al positive electrode area on the back side limits the conversion efficiency of P-type back-contact solar cells. Summary of the Invention

[0004] This invention provides a P-type back contact battery structure, which solves the problem of low conversion efficiency in existing P-type back contact batteries.

[0005] This invention is implemented as follows: a P-type back contact battery structure, comprising:

[0006] The P-type single crystal silicon substrate has a localized doped region on the front side and a first doped region and a second doped region on the back side.

[0007] A first tunneling oxide layer is disposed on the locally doped region;

[0008] A second tunneling oxide layer and a first intrinsic amorphous silicon layer are sequentially disposed on the first doped region;

[0009] A second intrinsic amorphous silicon layer disposed on the second doped region;

[0010] The first electrode passes through the first intrinsic amorphous silicon layer and makes electrical contact with the second tunneling oxide layer; and

[0011] The second electrode passes through the second intrinsic amorphous silicon layer and makes electrical contact with the back side of the P-type single-crystal silicon substrate.

[0012] Optionally, the first tunneling oxide layer includes a first tunneling layer and a first doped layer sequentially disposed on the locally doped region.

[0013] Optionally, the first doped layer is an N+ polycrystalline silicon layer.

[0014] Optionally, the second tunneling oxide layer includes a second tunneling layer and a second doped layer sequentially disposed on the first doped region.

[0015] Optionally, the second doped layer is an N+ polysilicon layer.

[0016] Optionally, a front passivation film and a back passivation film are respectively provided on the front and back sides of the P-type single crystal silicon substrate.

[0017] Optionally, the front passivation film and the back passivation film are made of at least one of aluminum oxide, silicon oxide and silicon nitride.

[0018] Secondly, this application also provides a method for manufacturing a P-type back contact battery structure, characterized in that it includes:

[0019] Fabrication of P-type single-crystal silicon substrates;

[0020] A first tunneling oxide layer and a second tunneling oxide layer are deposited on the local doped region on the front side and the first doped region on the back side of the P-type single crystal silicon substrate, respectively.

[0021] An intrinsic amorphous silicon layer is deposited on the back side of the P-type single-crystal silicon substrate, wherein the intrinsic amorphous silicon layer includes a first intrinsic amorphous silicon layer deposited on the second tunneling oxide layer and a second intrinsic amorphous silicon layer deposited on the second doped region.

[0022] A first electrode is disposed on the first intrinsic amorphous silicon layer, which is in electrical contact with the second tunneling oxide layer;

[0023] A second electrode is disposed on the second intrinsic amorphous silicon layer, which makes electrical contact with the back side of the P-type monocrystalline silicon substrate.

[0024] Optionally, after the step of depositing an intrinsic amorphous silicon layer on the back side of the P-type single-crystal silicon substrate, the method further includes:

[0025] A passivation film is deposited on the front side and a passivation film on the back side of the P-type single crystal silicon substrate, respectively.

[0026] Thirdly, this application also provides a solar cell, including the P-type back contact cell structure as described above.

[0027] The beneficial effects of this invention are as follows: By forming a first tunneling oxide layer on the front side of the P-type monocrystalline silicon substrate, and the first tunneling oxide layer being a local POLY structure to enhance front-side passivation and reduce parasitic absorption of light by POLY, and by forming an intrinsic amorphous silicon layer on the back side of the P-type monocrystalline silicon substrate, the passivation effect on the back side can be improved. By improving the front-side passivation effect in combination with improving the back-side passivation effect, the conversion efficiency of the P-type back contact cell can be effectively improved. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of a P-type back contact battery in the prior art;

[0029] Figure 2 This is a schematic diagram of one embodiment of the P-type back contact battery structure of this application;

[0030] Figure 3 This is a schematic flowchart of a method for manufacturing a P-type back contact battery structure according to an embodiment of this application;

[0031] Figure 4 This is a schematic flowchart of another embodiment of the method for manufacturing the P-type back contact battery structure of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0033] This invention, through the provision of a first tunneling oxide layer on the front side of a P-type monocrystalline silicon substrate, enhances front-side passivation by forming a localized polyline structure, thereby reducing parasitic light absorption by the polyline. Additionally, an intrinsic amorphous silicon layer is deposited on the back side of the P-type monocrystalline silicon substrate to further improve back-side passivation. By combining enhanced front-side and back-side passivation, the conversion efficiency of the P-type back-contact solar cell can be effectively improved.

[0034] Example 1

[0035] like Figure 2 As shown, this embodiment provides a P-type back contact battery structure, including:

[0036] P-type single crystal silicon substrate 100, the front side of P-type single crystal silicon substrate 100 has a local doped region, and the back side of P-type single crystal silicon substrate 100 has a first doped region and a second doped region.

[0037] A first tunneling oxide layer 200 is disposed on the locally doped region;

[0038] A second tunneling oxide layer 300 and a first intrinsic amorphous silicon layer 400 are sequentially disposed on the first doped region;

[0039] The second intrinsic amorphous silicon layer 500 is disposed on the second doped region;

[0040] The first electrode 600 passes through the first intrinsic amorphous silicon layer 400 and makes electrical contact with the second tunneling oxide layer 300; and

[0041] The second electrode 700 passes through the second intrinsic amorphous silicon layer 500 and makes electrical contact with the back side of the P-type single crystal silicon substrate 100.

[0042] In some embodiments, the P-type monocrystalline silicon substrate 100 of this application is used in a solar cell, which is a device that absorbs sunlight and directly or indirectly converts solar radiation energy into electrical energy through the photoelectric effect or photochemical effect. In implementation, the P-type monocrystalline silicon substrate 100 includes a front side and a back side, wherein the front side is the light-facing surface and the back side is the light-repelling surface.

[0043] Optionally, the P-type single crystal silicon substrate 100 is a P-type single crystal silicon wafer with a resistivity of 0.8 Ω·cm-3.0 Ω·cm, a thickness of 140 μm-180 μm, a minority carrier lifetime of 800 μs-3000 μs, an oxygen content of <12 ppm, and Ga doping.

[0044] Optionally, the front side of the P-type single-crystal silicon substrate 100 has a locally doped region, and the back side of the P-type single-crystal silicon substrate 100 has a first doped region and a second doped region. A first tunneling oxide layer 200 is disposed on the locally doped region. This first tunneling oxide layer 200 is a locally POLY structure on the front side of the P-type single-crystal silicon substrate 100, which can enhance the passivation effect on the front side of the P-type single-crystal silicon substrate 100. The first doped region corresponds to the negative electrode region, and the second doped region corresponds to the positive electrode region.

[0045] Optionally, a second tunneling oxide layer 300 and a first intrinsic amorphous silicon layer 400 are disposed on the first doped region. In practice, the first doped region corresponds to the negative electrode region, and the second tunneling oxide layer 300 and the first intrinsic amorphous silicon layer 400 are sequentially disposed on the first doped region.

[0046] Optionally, a first electrode 600 is further disposed on the first doped region, specifically, the first electrode 600 is in electrical contact with the second tunneling oxide layer 300. Optionally, a first intrinsic amorphous silicon layer 400 covers the second tunneling oxide layer 300, and a through-hole can be formed in the first intrinsic amorphous silicon layer 400 so that the first electrode 600 can pass through the through-hole and make electrical contact with the second tunneling oxide layer 300.

[0047] Optionally, a second intrinsic amorphous silicon layer 500 is disposed on the second doped region. In practice, the second doped region corresponds to the positive electrode region. Optionally, a second electrode 700 is also disposed on the second doped region, specifically, the second electrode 700 is in electrical contact with the back side of the P-type single-crystal silicon substrate 100.

[0048] Optionally, the second intrinsic amorphous silicon layer 500 covers the second doped region on the back side of the P-type single crystal silicon substrate 100. Through holes can be provided in the second intrinsic amorphous silicon layer 500 so that the second electrode 700 can pass through the through holes and make electrical contact with the back side of the P-type single crystal silicon substrate 100.

[0049] In some embodiments, the first intrinsic amorphous silicon layer 400 and the second intrinsic amorphous silicon layer 500 are both intrinsic amorphous silicon layers. By depositing an intrinsic amorphous silicon layer on the back side, the passivation effect of the positive electrode region can be greatly improved.

[0050] In this embodiment, a first tunneling oxide layer 200 is formed on the front side of the P-type monocrystalline silicon substrate 100. The first tunneling oxide layer 200 is a local POLY structure to enhance front-side passivation and reduce parasitic light absorption by POLY. In addition, an intrinsic amorphous silicon layer is formed on the back side of the P-type monocrystalline silicon substrate 100 to improve the passivation effect on the back side. By improving the passivation effect on the front side and combining it with the improvement of the passivation effect on the back side, the conversion efficiency of the P-type back contact cell can be effectively improved.

[0051] Example 2

[0052] In some alternative embodiments, the first tunneling oxide layer 200 includes a first tunneling layer 210 and a first doped layer 220 sequentially disposed on a local doped region.

[0053] In practice, a first tunneling layer 210 and a first doped layer 220 are sequentially disposed on the local doped region.

[0054] Optionally, the first tunneling layer 210 is silicon oxide with a thickness of 1nm-2nm.

[0055] Optionally, the first doped layer 220 is an N+ polycrystalline silicon layer with a thickness of 20nm-80nm and a surface P concentration of 2-10*E+20 atoms / cm3.

[0056] In practice, the first doped layer 220 and the first tunneling layer 210 are locally deposited in the local doped region. The local doped region accounts for 5-20% of the front area of ​​the P-type single crystal silicon substrate 100. In some possible embodiments, the local doped region is uniformly distributed in a rectangular or circular shape on the front side of the P-type single crystal silicon substrate 100.

[0057] In some alternative embodiments, the second tunneling oxide layer 300 includes a second tunneling layer 310 and a second doped layer 320 sequentially disposed on the first doped region.

[0058] Optionally, the second tunneling layer 310 has the same thickness and type as the first tunneling layer 210, which will not be described in detail here.

[0059] Optionally, the second doped layer 320 is an N+ polycrystalline silicon layer with a thickness of 80nm-300nm and a P concentration of 2-10*E+20 atoms / cm3.

[0060] In practice, both the first intrinsic amorphous silicon layer 400 and the second intrinsic amorphous silicon layer 500 are intrinsic amorphous silicon layers with a thickness of 5nm-50nm.

[0061] In some embodiments, a front passivation film 800 and a back passivation film 900 are respectively provided on the front and back sides of the P-type single crystal silicon substrate 100.

[0062] Optionally, the front passivation film and the back passivation film are made of at least one of aluminum oxide, silicon oxide, and silicon nitride. For example, the front passivation film may be aluminum oxide / silicon nitride, with the aluminum oxide having a thickness of 5 nm-10 nm and the silicon nitride having a thickness of 70 nm-80 nm. In other embodiments, the back passivation film may be aluminum oxide / silicon nitride, or silicon oxide / silicon nitride, with the aluminum oxide having a thickness of 5 nm-10 nm, the silicon nitride having a thickness of 80 nm-150 nm, and the silicon oxide having a thickness of 10 nm-30 nm.

[0063] Optionally, the first electrode 600 and the second electrode 700 may be made of metal. For example, the first electrode 600 may be made of Ag (silver) and the second electrode 700 may be made of Al (aluminum). The Ag electrode is in electrical contact with the N+ polycrystalline silicon layer on the back side, and the Al electrode is in electrical contact with the back side of the P-type single-crystal silicon substrate 100.

[0064] In practice, the fabrication process of the P-type back contact battery structure provided in this embodiment is as follows:

[0065] Step 1: Polish the P-type single-crystal silicon substrate with 100% double-sided alkaline solution, controlling the reflectivity to 38%-50%, with the quadrilateral side length of the pyramid base being 5-15 micrometers. The raw silicon wafer is first pre-cleaned in a mixed solution of H2O2 / KOH (hydrogen peroxide / potassium hydroxide) to remove surface contaminants for 100-300 seconds at 60-65°C. Then, it is rinsed in a water bath for 60-120 seconds, followed by alkaline polishing in a KOH solution for 250-400 seconds at 60-70°C with a KOH concentration of 1%-2%. This is followed by another 60-120 seconds of rinsing in a water bath, then further immersion in HF / HCl (hydrogen fluoride / hydrogen chloride) to remove surface impurities and metal ions. Finally, it is rinsed with water and dried.

[0066] Step 2: Deposition of the second tunneling layer 310 and P-doped amorphous silicon (second doped layer 320). The deposition of the second tunneling layer 310 and P-doped amorphous silicon is completed in one device using LPCVD (Low Pressure Chemical Vapor Deposition). The second tunneling layer 310 is silicon oxide, and the P-doped amorphous silicon is 80nm-300nm.

[0067] Step 3: POCl3 (phosphorus oxychloride) diffusion, which can be carried out using a double-sided diffusion mode; diffusion temperature 830℃-860℃. After diffusion, amorphous silicon is crystallized into N+ polycrystalline silicon, and a 30nm-50nm phosphosilicate glass layer PSG (boron phosphosilicate glass) is formed on the surface of the polycrystalline silicon. The P atom content on the polycrystalline silicon surface is 2-10*1020 atoms / cm3; PSG is present on both the front and back sides;

[0068] Step 4: Laser ablation. Using a nanosecond or picosecond laser device, patterned laser etching is performed on the back side to remove the PSG and N+ polysilicon in the region designed as P (corresponding to the positive electrode region), exposing the P-type single crystal silicon substrate 100.

[0069] Step 5: PSG removal on both sides / texturing on the front and removal of laser damage layer on the back; using a combined chain and trough wet process equipment, the silicon wafer is first placed in the chain HF trough, floating on water with the front side down and the back side up, and sprayed with a water film to remove PSG from the front side of the wafer; water washing removes acid residue; then a transmission device places the silicon wafer from the chain trough into a transfer basket; the basket is transferred into the trough wet process equipment for texturing, using 0.5%-1% KOH (potassium hydroxide), at a temperature of 70℃-75℃, for 350s-500s, forming a textured surface on the front side of the silicon wafer with a reflectivity of 8%-11% and a pyramid base side length of 2-3 micrometers; the same textured surface is formed on the laser ablation trough on the back side of the silicon wafer, removing the laser damage layer, with a depth of 4-8 micrometers; then it enters a water tank for rinsing; then it enters an HF / HCl trough to remove PSG from the back side; after water washing, it is dried;

[0070] Step 6: Locally deposit a tunneling layer (first tunneling layer 210) and a pre-P-doped amorphous silicon layer (first doped layer 220) on the front side using plate-type PVD (Physical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition). During deposition, a patterned mask is placed on the front side of the silicon wafer. This mask allows only the tunneling layer and the pre-P-doped amorphous silicon layer to be patterned and deposited on the front side. The thicknesses of the pre-P-doped amorphous silicon layer and the tunneling layer are 20nm-80nm and 1nm-2nm, respectively, and the tunneling layer is made of silicon oxide. Plate-type PVD or PECVD deposition methods do not have the problem of plating around the substrate.

[0071] Step 7: Annealing is performed in a high-temperature annealing furnace at a temperature of 700℃-850℃ in a nitrogen or argon atmosphere for 40-80 minutes. After annealing, the P-doped amorphous silicon is transformed into an N+ polycrystalline silicon layer with a surface P concentration of 2-10*E+20 atoms / cm3. The N+ polycrystalline silicon layer occupies 5%-20% of the front area of ​​the silicon wafer and is uniformly distributed in a rectangular or circular pattern.

[0072] Step 8: Deposit an intrinsic amorphous silicon layer on the back side; use plate-type PVD or PECVD, without the problem of wrap-around plating; the thickness of the intrinsic amorphous silicon layer is 5nm-50nm;

[0073] Step 9: Simultaneously deposit aluminum oxide layers on both sides of the silicon wafer using ALD (Atomic Layer Deposition); the aluminum oxide layer thickness is 5nm-10nm.

[0074] Step 10: Deposit silicon nitride layers on the front and back sides; the thickness of silicon nitride on the front side is 70nm-80nm, and the thickness of silicon nitride on the back side is 80nm-150nm; a silicon oxide / silicon nitride stack can also be deposited on the back side, with silicon nitride thickness of 80nm-150nm and silicon oxide thickness of 10nm-30nm.

[0075] Step 11: Laser grooving of the P-region on the back side; use a nanosecond or picosecond laser to perform local grooving in the P-region to remove the local post-passivation film / intrinsic amorphous silicon and expose the P-type silicon (P-type single crystal silicon substrate 100); the laser spot width for grooving is 25 micrometers-35 micrometers.

[0076] Step 12: Screen printing metal paste on the back side; Al paste is used for the P area and Ag paste is used for the N (corresponding to the negative electrode area) area for screen printing, and then high-temperature sintering is performed; Ag paste has strong corrosiveness, which allows the metal Ag electrode and the back N+ polycrystalline silicon layer (second doped layer 320) to be in direct contact; the metal Al electrode is in direct contact with the P-type silicon substrate through laser-grooved holes.

[0077] The front surface employs a POLY structure formed by a localized tunneling layer / N+ polycrystalline silicon layer to enhance passivation, utilizing the excellent passivation performance of the POLY structure. The localized POLY layer minimizes parasitic absorption of light by the front POLY layer, achieving a better balance between passivation and parasitic absorption, which is beneficial for improving conversion efficiency. On the back surface, an intrinsic amorphous silicon layer containing hydrogen (H) is deposited on top of the POLY layer. During high-temperature sintering, H is injected into the back of the silicon wafer, improving its passivation performance. Since there is POLY in the N-region, this passivation effect is mainly for the P-region. The combination of these two methods can significantly improve the passivation effect of the front and back surfaces of the P-type back contact solar cell, thereby improving the cell's conversion efficiency.

[0078] Example 3

[0079] In some alternative embodiments, such as Figure 3 As shown, this application also provides a method for manufacturing a P-type back contact battery structure, used to manufacture the P-type back contact battery structure as described above, the method comprising:

[0080] S1100, fabrication of P-type single-crystal silicon substrates;

[0081] In implementation, this application selects a P-type single crystal silicon wafer as the P-type single crystal silicon substrate. The silicon wafer has a resistivity of 0.8Ω·cm-3.0Ω·cm, a thickness of 140μm-180μm, a minority carrier lifetime of 800µs-3000µs, an oxygen content of <12ppm, and is Ga-doped.

[0082] Optionally, to fabricate a P-type monocrystalline silicon substrate, the substrate should first undergo double-sided alkaline polishing to control the reflectivity to 38%-50%, with the quadrilateral side length of the pyramid base being 5-15 micrometers. The raw silicon wafer is then pre-cleaned in a mixed solution of H₂O₂ / KOH (hydrogen peroxide / potassium hydroxide) for 100-300 seconds at 60-65°C to remove surface contaminants. Next, the wafer is placed in a water bath for 60-120 seconds, followed by alkaline polishing in a KOH solution for 250-400 seconds at 60-70°C and a KOH concentration of 1%-2%. This is followed by another 60-120 seconds of water cleaning, then immersion in HF / HCl (hydrogen fluoride / hydrogen chloride) to remove surface impurities and metal ions. Finally, the wafer is washed and dried.

[0083] S1200, deposit a first tunneling oxide layer and a second tunneling oxide layer on the local doped region on the front side and the first doped region on the back side of the P-type single crystal silicon substrate, respectively.

[0084] Optionally, the front side of the P-type single-crystal silicon substrate has a locally doped region, and the back side of the P-type single-crystal silicon substrate has a first doped region and a second doped region. A first tunneling oxide layer and a second tunneling oxide layer are deposited on the locally doped region and the first doped region, respectively.

[0085] In some embodiments, the second tunneling oxide layer includes a second tunneling layer disposed on the first doped region and a second doped layer disposed on the second tunneling layer.

[0086] Optionally, a second tunneling layer and P-doped amorphous silicon (second doped layer) are deposited on the first doped region, wherein the deposition of the second tunneling layer and P-doped amorphous silicon is completed in one device using LPCVD.

[0087] In some embodiments, the second tunneling layer 310 is silicon oxide, and the P-doped amorphous silicon is 80nm-300nm.

[0088] Then, diffusion is performed using POCl3 (phosphorus oxychloride). During implementation, a double-sided diffusion mode can be used. The diffusion temperature is 830℃-860℃. After diffusion, the amorphous silicon (second doped layer) is crystallized into N+ polycrystalline silicon. A 30nm-50nm phosphorus-silicone glass layer (PSG) is formed on the polycrystalline silicon surface. The P atom content on the polycrystalline silicon surface is 2-10*1020 atoms / cm3; PSG is present on both the front and back sides.

[0089] In some embodiments, since the second tunneling layer and P-doped amorphous silicon deposition cover the back side of the P-type monocrystalline silicon substrate, it is also necessary to remove the second tunneling layer and P-doped amorphous silicon deposition on the second doped region accordingly. In practice, the second tunneling layer and P-doped amorphous silicon deposition on the second doped region can be removed by laser ablation. For example, a nanosecond or picosecond laser device can be used to perform patterned laser etching on the back side, removing the PSG and N+ polycrystalline silicon in the region designed as P (corresponding to the second doped region), exposing the P-type monocrystalline silicon substrate.

[0090] In some possible embodiments, PSG removal / texturing of the front and back sides and removal of the laser damage layer on the back side can also be performed. A combined chain-type and trough-type wet processing device is used. The silicon wafer is first placed in a chain-type HF trough, floating on water with the front side facing down and the back side facing up, and a water film is sprayed to remove the PSG from the front side. Water washing removes acid residue. Then, a transmission device places the silicon wafer from the chain trough into a transfer basket. The basket is then transferred into the trough-type wet processing device for texturing. Texturing uses 0.5%-1% KOH (potassium hydroxide), at a temperature of 70℃-75℃, for 350s-500s, forming a textured surface on the front side of the silicon wafer with a reflectivity of 8%-11% and a pyramid base side length of 2-3 micrometers. The same textured surface is formed on the laser ablation trough on the back side of the silicon wafer, removing the laser damage layer. The depth of the laser ablation trough is 4-8 micrometers. Then, the wafer is rinsed in a water tank. Next, it enters an HF / HCl trough to remove the PSG on the back side. After water washing, it is dried.

[0091] Optionally, after depositing the second tunneling oxide layer in the first doped region on the back side of the P-type single-crystal silicon substrate, it is also necessary to deposit the first tunneling oxide layer in the local doped region on the front side of the second tunneling oxide layer.

[0092] In some embodiments, the first tunneling oxide layer is a local POLY structure on the front side of a P-type single-crystal silicon substrate, which can enhance the passivation effect on the front side of the P-type single-crystal silicon substrate.

[0093] Optionally, the first tunneling oxide layer includes a first tunneling layer disposed on a locally doped region and a first doped layer disposed on the first tunneling layer.

[0094] In practice, a first tunneling layer and a pre-P-doped amorphous silicon layer (corresponding to the first doped layer) can be deposited in the local doped region, for example, by using plate PVD or PECVD. Plate PVD or PECVD deposition does not have the problem of plating around the surface.

[0095] Optionally, during deposition, a patterned mask is placed on the front side of the silicon wafer, which allows only the tunneling layer and the pre-P-doped amorphous silicon layer to be patterned and deposited on the front side, that is, the first tunneling layer and the first doped layer are deposited only in a local area on the front side.

[0096] Optionally, the thickness of the pre-P-doped amorphous silicon layer and the tunneling layer can be 20nm-80nm and 1nm-2nm respectively, and the tunneling layer is silicon oxide.

[0097] After depositing the P-doped amorphous silicon layer, a high-temperature annealing furnace is used for annealing at a temperature of 700℃-850℃ in a nitrogen or argon atmosphere for 40-80 minutes. After annealing, the P-doped amorphous silicon becomes a post-N+ polycrystalline silicon layer with a surface P concentration of 2-10*E+20 particles / cm3, thus obtaining the first doped layer.

[0098] Optionally, the first doped layer accounts for 5%-20% of the front area of ​​the P-type single crystal silicon substrate, and its distribution is uniformly rectangular or circular, which is not limited here.

[0099] S1300, An intrinsic amorphous silicon layer is deposited on the back side of a P-type single-crystal silicon substrate, wherein the intrinsic amorphous silicon layer includes a first intrinsic amorphous silicon layer deposited on a second tunneling oxide layer and a second intrinsic amorphous silicon layer deposited on a second doped region.

[0100] In practice, both the first and second intrinsic amorphous silicon layers are intrinsic amorphous silicon layers. The intrinsic amorphous silicon layer can be deposited on the back side of the P-type single crystal silicon substrate using plate PVD or PECVD methods, without any issues related to plating around the substrate.

[0101] Optionally, in some embodiments, the thickness of the intrinsic amorphous silicon layer is 5nm-50nm.

[0102] S1400, A first electrode that is electrically in contact with the second tunneling oxide layer is disposed on the first intrinsic amorphous silicon layer;

[0103] S1500, a second electrode is provided on the second intrinsic amorphous silicon layer to make back electrical contact with the P-type monocrystalline silicon substrate.

[0104] After depositing the intrinsic amorphous silicon layer, laser grooving is performed on the intrinsic amorphous silicon layer in the second doped region on the back side of the P-type single-crystal silicon substrate. For example, nanosecond or picosecond lasers are used to perform local grooving in the second doped region to remove the local second intrinsic amorphous silicon layer and expose the P-type single-crystal silicon substrate.

[0105] Optionally, the width of the laser spot for the slot is 25 micrometers to 35 micrometers, and is not limited here.

[0106] Metal pastes are screen-printed on the back side of a P-type single-crystal silicon substrate. For example, Al paste is used in the second doped region, and Ag paste is used in the corresponding first doped region, followed by high-temperature sintering. Ag paste has strong corrosiveness, allowing the metal Ag electrode to directly contact the subsequent N+ polycrystalline silicon layer (second doped layer); the metal Al electrode directly contacts the P-type single-crystal silicon substrate through laser-drilled holes.

[0107] This application embodiment enhances front-side passivation by forming a first tunneling oxide layer on the front side of a P-type monocrystalline silicon substrate. This first tunneling oxide layer, consisting of a localized polyline structure, reduces parasitic light absorption by the polyline. Additionally, an intrinsic amorphous silicon layer is formed on the back side of the P-type monocrystalline silicon substrate to improve back-side passivation. By combining improved front-side and back-side passivation, the conversion efficiency of the P-type back-contact solar cell can be effectively improved.

[0108] In some embodiments, such as Figure 4 As shown, after step S1300, the manufacturing method provided in this application further includes:

[0109] S1310, deposit a front passivation film and a back passivation film on the front and back sides of a P-type single crystal silicon substrate, respectively.

[0110] Optionally, the passivation film on the front side can be made of aluminum oxide / silicon nitride, wherein the thickness of aluminum oxide is 5nm-10nm and the thickness of silicon nitride is 70nm-80nm, which is not limited here.

[0111] Optionally, the back passivation film can be aluminum oxide / silicon nitride or silicon oxide / silicon nitride, wherein the thickness of aluminum oxide is 5nm-10nm, the thickness of silicon nitride is 80nm-150nm, and the thickness of silicon oxide is 10nm-30nm, without limitation.

[0112] In some embodiments, aluminum oxide layers can be deposited simultaneously on the front and back sides of the silicon wafer using the ALD method, followed by silicon nitride layers, which is not limited here.

[0113] Example 4

[0114] This application also provides a solar cell, which includes the P-type back contact cell structure as described above.

[0115] Those skilled in the art will clearly understand that, for the sake of convenience and indirectness, the structure and implementation principle of the solar cell described above can be referred to the corresponding structure and implementation principle in the foregoing embodiments one and two, and will not be repeated here.

[0116] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A P-type back contact battery structure, characterized in that, include: The P-type single crystal silicon substrate has a locally doped region on the front side and a first doped region and a second doped region on the back side. A first tunneling oxide layer is disposed on the local doped region; A second tunneling oxide layer and a first intrinsic amorphous silicon layer are sequentially disposed on the first doped region; A second intrinsic amorphous silicon layer disposed on the second doped region; The first electrode passes through the first intrinsic amorphous silicon layer and makes electrical contact with the second tunneling oxide layer; and The second electrode passes through the second intrinsic amorphous silicon layer and makes electrical contact with the back side of the P-type single-crystal silicon substrate; The first tunneling oxide layer includes a first tunneling layer and a first doped layer sequentially disposed on the local doped region; the first doped layer is an N+ polysilicon layer; The second tunneling oxide layer includes a second tunneling layer and a second doped layer sequentially disposed on the first doped region; The second doped layer is an N+ polycrystalline silicon layer.

2. The P-type back contact battery structure as described in claim 1, characterized in that, The P-type single-crystal silicon substrate has a front passivation film and a back passivation film respectively on its front and back sides.

3. The P-type back contact battery structure as described in claim 2, characterized in that, The front passivation film and the back passivation film are made of at least one of aluminum oxide, silicon oxide and silicon nitride.

4. A method for manufacturing a P-type back contact battery structure as described in any one of claims 1 to 3, characterized in that, include: Fabrication of P-type single-crystal silicon substrates; A first tunneling oxide layer and a second tunneling oxide layer are deposited on the local doped region on the front side and the first doped region on the back side of the P-type single crystal silicon substrate, respectively. An intrinsic amorphous silicon layer is deposited on the back side of the P-type single-crystal silicon substrate, wherein the intrinsic amorphous silicon layer includes a first intrinsic amorphous silicon layer deposited on the second tunneling oxide layer and a second intrinsic amorphous silicon layer deposited on the second doped region. A first electrode is disposed on the first intrinsic amorphous silicon layer, which is in electrical contact with the second tunneling oxide layer; A second electrode is disposed on the second intrinsic amorphous silicon layer, which makes electrical contact with the back side of the P-type monocrystalline silicon substrate.

5. A manufacturing method as described in claim 4, characterized in that, After the step of depositing an intrinsic amorphous silicon layer on the back side of the P-type single-crystal silicon substrate, the method further includes: A passivation film is deposited on the front side and a passivation film on the back side of the P-type single crystal silicon substrate, respectively.

6. A solar cell, characterized in that, Includes the P-type back contact battery structure as described in any one of claims 1 to 3.

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