A low power reference circuit for wide range buck converter
By employing a low-power reference circuit design that superimposes PTAT and CTAT voltages in the Buck converter, the pre-buck circuit is eliminated, achieving a low quiescent current and low power consumption reference circuit. This solves the problem of high power consumption in traditional reference circuits and improves the efficiency and durability of the converter.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2023-04-14
- Publication Date
- 2026-07-31
AI Technical Summary
Traditional wide-range Buck converters have high reference circuit power consumption, making it difficult to achieve low-power designs with low quiescent current. Furthermore, the lack of a pre-buck circuit leads to device aging and low efficiency.
By directly superimposing the PTAT and CTAT voltages, a low-power reference circuit is designed, eliminating the need for a pre-step-down circuit. This circuit includes a high-voltage depletion-mode N-type power transistor, a low-voltage depletion-mode NMOS transistor, a resistor adjustment network, and a transistor, achieving a single-branch output reference voltage suitable for a wide input range.
It achieves quiescent current as low as nA, has good linear regulation and power supply rejection performance, is suitable for environments with a wide range of power supply fluctuations, and improves the efficiency and durability of the converter.
Smart Images
Figure CN116388521B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the fields of integrated circuit technology and power electronics, and specifically relates to a low-power reference circuit for a wide-range Buck converter. Background Technology
[0002] Wide-range DC-DC Buck converter chips are widely used in industrial power systems, telecommunications systems, military avionics, and medical systems. Low-power design in wide-range Buck converters not only saves energy but also reduces chip temperature, slows down the aging of internal components, and improves chip durability. Low-power design, as one of the development trends of Buck converters, is a key challenge in the power supply industry today. In traditional wide-range Buck converters, a pre-buck circuit powers the reference circuit, generating a reference voltage as the LDO's reference voltage. To reduce the chip's quiescent current, the LDO-reference nested power rail was later invented, eliminating the need for the pre-buck circuit. However, the reference core often uses a bandgap structure, resulting in still relatively high power consumption. Therefore, for wide-range DC-DC Buck converters with low quiescent current, designing a low-power reference circuit without a pre-buck circuit is of practical significance. Summary of the Invention
[0003] The purpose of this invention is to propose a low-power reference circuit suitable for Buck converters with low quiescent current and a wide input range. Compared to traditional reference circuits in Buck converters, this invention eliminates the pre-stepping circuit and can support a wide input range on its own. It uses a direct superposition of PTAT and CTAT voltages to output a single-branch reference voltage with a quiescent current in the nA range.
[0004] To achieve the above objectives, the technical solution of the present invention is as follows: a low-power reference circuit for a wide-range Buck converter, comprising a high-voltage depletion-type N-type power transistor NDA, a low-voltage depletion-type NMOS transistor NDE, a first resistor adjustment network R1, a second resistor adjustment network R2, and a transistor Q1; the drain of the high-voltage depletion-type N-type power transistor NDA in the low-power reference circuit is connected to the power supply VDD, the source of the high-voltage depletion-type N-type power transistor NDA is connected to the drain of the low-voltage depletion-type NMOS transistor NDE, and the high-voltage depletion-type N-type power transistor NDA is connected to the drain of the low-voltage depletion-type NMOS transistor NDE. The gate of the high-voltage depletion-type N-type power transistor NDA is connected to the base of transistor Q1; the source of the low-voltage depletion-type NMOS transistor NDE is connected to the upper end of the first resistor adjustment network R1, and the gate of the low-voltage depletion-type NMOS transistor NDE is connected to the lower end of the first resistor adjustment network R1 and the upper end of the second resistor adjustment network R2; the lower end of the second resistor adjustment network R2 is connected to the collector of transistor Q1; the collector and base of transistor Q1 are shorted, connected to the lower end of the second resistor adjustment network R2 and the gate of the high-voltage depletion-type N-type power transistor NDA, and the emitter of transistor Q1 is grounded.
[0005] The resistor adjustment networks R1 and R2 are arbitrary resistor adjustment structures commonly used by those skilled in the art.
[0006] The beneficial effects of this invention are as follows: It provides a low-power reference circuit for wide-range Buck converters with low quiescent current. Compared to traditional reference circuits in Buck converters, this invention eliminates the pre-buck circuit and can support a wide input range on its own. It uses a direct superposition of PTAT and CTAT voltages to output a single-branch reference voltage. This invention exhibits excellent line regulation and power supply rejection performance, and also enables self-starting. This invention can also be used as a bias circuit for an LDO, replicating the current by providing a bias voltage through transistor Q1. This invention has a quiescent current as low as nA, making it possible to reduce the quiescent current of wide-range Buck converters in non-switching states to the nA level, further improving converter efficiency. Attached Figure Description
[0007] Figure 1 This is a schematic diagram of a low-power reference circuit for a wide-range Buck converter proposed in this invention;
[0008] Figure 2 This is a simulation diagram of the output voltage-temperature of a low-power reference circuit for a wide-range Buck converter proposed in this invention.
[0009] Figure 3 This is a static current-supply voltage simulation diagram of a low-power reference circuit for a wide-range Buck converter proposed in this invention.
[0010] Figure 4 This is a simulation diagram of the output voltage versus supply voltage of a low-power reference circuit for a wide-range Buck converter proposed in this invention.
[0011] Figure 5 This is a PSR-frequency simulation diagram of a low-power reference circuit for a wide-range Buck converter proposed in this invention. Detailed Implementation
[0012] The embodiments of the present invention will be described in detail with reference to the accompanying drawings. A schematic diagram of a low-power reference circuit for a low quiescent current, wide-range Buck converter proposed in this invention is shown below. Figure 1 As shown.
[0013] Figure 1 In the low-power reference circuit schematic, the circuit is powered by a supply voltage of several to tens of volts. A high-voltage depletion-type N-type power transistor, NDA, pre-manages the supply voltage, lowering it to a low voltage range, allowing low-voltage devices NDE, R1, R2, and Q1 to operate normally. The reference voltage V... ref The following expression exists:
[0014]
[0015] V can be calculated using the NDE saturation current formula. SG,NDE :
[0016]
[0017] Substitute V ref The expression:
[0018]
[0019] V ref In the expression, the first and third terms have negative temperature coefficients, while the second term has a positive temperature coefficient. Therefore, by appropriately setting the aspect ratio of the NDE and the resistance values of R1 and R2, a voltage with zero temperature coefficient can be obtained. Process deviations are corrected by changing the resistance values of the resistor adjustment network R1 and R2.
[0020] Since this invention uses only N-type transistors, the impedance to ground of the reference output is much smaller than the impedance to ground of the power supply, thus this design has good power supply rejection performance.
[0021] This invention uses only transistors with their power dissipation and base shorted, thus enabling self-starting.
[0022] by Figure 1 Taking the low-power reference circuit shown as an example, applying a power supply voltage of 3-65V, and combining specific case simulation results, the technical effect of the voltage reference circuit proposed in this invention is illustrated. The results obtained through Spectre simulation are as follows: Figure 2 , Figure 3 , Figure 4 and Figure 5 The simulation diagram shown demonstrates that under a power supply voltage of 65V, a temperature range of -40℃ to 125℃, and a standard process angle, the reference voltage V... ref The temperature coefficient is 20.71 ppm / ℃. Under standard process angles and with a power supply voltage of 3V–65V and a temperature of 25℃, the quiescent current remains stable at 168 nA. The linear regulation is 1.98 μV / V under standard process angles and with a power supply voltage of 3V–65V and a temperature of 25℃. At a power supply voltage of 65V and a temperature of 25℃, the low-frequency PSR reaches -107 dB. It is evident that this invention exhibits a low temperature coefficient, low quiescent current, excellent linear regulation, and power supply rejection performance under normal operating conditions, making it particularly suitable for applications with a wide power supply range and large fluctuations.
[0023] Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the essence of this invention, and these modifications and combinations are still within the protection scope of this invention.
Claims
1. A low power reference circuit for a wide range Buck converter, characterized by, The circuit includes a high-voltage depletion-type N-type power transistor NDA, a low-voltage depletion-type NMOS transistor NDE, a first resistor adjustment network R1, a second resistor adjustment network R2, and a transistor Q1. The drain of the high-voltage depletion-type N-type power transistor NDA is connected to the power supply VDD, the source of NDA is connected to the drain of the low-voltage depletion-type NMOS transistor NDE, and the gate of NDA is connected to the base of transistor Q1. The source of the low-voltage depletion-type NMOS transistor NDE is connected to the upper end of the first resistor adjustment network R1, and the gate of NDE is connected to the lower end of the first resistor adjustment network R1 and the upper end of the second resistor adjustment network R2. The lower end of the second resistor adjustment network R2 is connected to the collector of transistor Q1. The collector and base of transistor Q1 are shorted, connected to the lower end of the second resistor adjustment network R2 and the gate of the high-voltage depletion-type N-type power transistor NDA, and the emitter of transistor Q1 is grounded.