A fixed conduction time based constant frequency PWM controller and control method

Abstract

The application relates to a fixed conduction time-based fixed-frequency PWM controller and a control method, and belongs to the field of analog integrated circuit design. The fixed-frequency PWM controller comprises a filtering and feedback circuit, a PFM comparator circuit, an error amplification and compensation circuit, a clock generator, a slope compensation circuit, a PFM fixed conduction time generation circuit, a fixed-frequency PWM conduction time generation circuit, a zero-crossing detection circuit, an OR gate logic circuit, a PWM logic and driving circuit and a switching power stage. The application takes the OR gate logic and the PFM comparator circuit as cores, realizes the entry and exit of a DC / DC controller between a fixed-frequency PWM mode and a light-load variable-frequency mode, the circuit structure and the control logic are simple, the realization is convenient, and the application has the characteristics of light-load high efficiency.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design technology, and in particular to a fixed-frequency PWM controller and control method based on a fixed on-time. Background Technology

[0002] DC / DC converters, as important power management circuits, are widely used in various portable products such as mobile phones, tablets, and digital cameras. In portable applications, the efficiency of the DC / DC converter under light loads largely determines the standby time of the portable product system. Therefore, in recent years, the design of low-power, high-efficiency DC / DC light-load control circuits has become one of the research hotspots for many portable applications.

[0003] In existing fixed-frequency DC / DC light-load control circuits that use clocks, the control logic required for light-load frequency conversion control is relatively complex. It requires a lot of logic circuits and clock synchronization, and additional control circuits are needed to extend the turn-off time or extend the clock cycle to reduce the switching frequency under light load. Therefore, they generally have the technical defects of complex circuit structure and control logic. Summary of the Invention

[0004] The purpose of this invention is to provide a fixed-frequency PWM controller and control method based on a fixed conduction time, so as to achieve high-efficiency DC / DC conversion under light load using a relatively simple circuit structure and control logic.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] A fixed-frequency PWM controller based on fixed on-time includes: a filtering and feedback circuit, a PFM comparator circuit, an error amplification and compensation circuit, a clock generator, a ramp compensation circuit, a PFM fixed on-time generation circuit, a fixed-frequency PWM on-time generation circuit, a zero-crossing detection circuit, an OR gate logic circuit, a PWM logic and drive circuit, and a switching power stage.

[0007] The output pin SW of the switching power stage is connected to the input pin SW of the filtering and feedback circuit and the input pin SW of the zero-crossing detection circuit, respectively; the output pin VOUT of the filtering and feedback circuit is connected to the input pin VOUT of the PFM fixed on-time generation circuit; the output pin VOUT of the filtering and feedback circuit generates an output voltage VOUT to power the external load.

[0008] The output pin FB of the filtering and feedback circuit is connected to the non-inverting input pin of the PFM comparator circuit and the input pin FB of the error amplification and compensation circuit, respectively; the inverting input pin of the PFM comparator circuit is connected to the PFM mode reference voltage VREF2; the output pin VCOMP of the error amplification and compensation circuit is connected to the non-inverting input pin of the ramp compensation circuit; the input pin PFM of the clock generator is connected to the output pin of the PFM comparator circuit; the output pin CLK of the clock generator is connected to the input pin CLK of the PFM fixed on-time generation circuit and the input pin CLK of the fixed-frequency PWM on-time generation circuit, respectively; the output pin VSP of the clock generator is connected to the inverting input pin of the ramp compensation circuit; the input pin VIN of the PFM fixed on-time generation circuit is connected to the input voltage VIN; the input pin VSET of the fixed-frequency PWM on-time generation circuit is connected to the output pin of the ramp compensation circuit; the input pin IHS of the fixed-frequency PWM on-time generation circuit is connected to the output pin IHS of the switching power stage.

[0009] The output pin TON_PFM of the PFM fixed on-time generator circuit is connected to the first input pin of the OR gate logic circuit; the output pin TON_PWM of the fixed-frequency PWM on-time generator circuit is connected to the second input pin of the OR gate logic circuit; the output pin of the OR gate logic circuit is connected to the input pin TON of the PWM logic and drive circuit; the input pin ZCD of the PWM logic and drive circuit is connected to the output pin ZCD of the zero-crossing detection circuit; the output pin HS of the PWM logic and drive circuit is connected to the input pin HS of the switching power stage; the output pin LS of the PWM logic and drive circuit is connected to the input pin LS of the switching power stage; and the input pin VIN of the switching power stage is connected to the input voltage VIN.

[0010] Optionally, the filtering and feedback circuit includes: an inductor L, an output capacitor C, an upper voltage divider resistor R1, and a lower voltage divider resistor R2; one end of the inductor L is the input terminal SW pin of the filtering and feedback circuit, connected to the switching voltage SW generated by the output terminal SW pin of the switching power stage; the other end of the inductor L is connected to one end of the output capacitor C and one end of the upper voltage divider resistor R1; the other end of the upper voltage divider resistor R1 is connected to one end of the lower voltage divider resistor R2; the other end of the lower voltage divider resistor R2 and the other end of the output capacitor C are both grounded; the other end of the inductor L is the output terminal VOUT pin of the filtering and feedback circuit, generating the output voltage VOUT; the other end of the upper voltage divider resistor R1 is the output terminal FB pin of the filtering and feedback circuit, generating the sampling feedback voltage FB.

[0011] Optionally, the PFM comparator circuit includes: a comparator U1; the non-inverting input terminal of the comparator U1 is the non-inverting input pin of the PFM comparator circuit and is connected to the sampling feedback voltage FB; the inverting input terminal of the comparator U1 is the inverting input pin of the PFM comparator circuit and is connected to the PFM mode reference voltage VREF2; the output terminal of the comparator U1 is the output pin of the PFM comparator circuit, generating a light-load high-efficiency mode indication signal PFM.

[0012] Optionally, the error amplification and compensation circuit includes: an error operational amplifier U2; the non-inverting input terminal of the error operational amplifier U2 is connected to the PWM mode reference voltage VREF; the inverting input terminal of the error operational amplifier U2 is the input terminal FB pin of the error amplification and compensation circuit, connected to the sampling feedback voltage FB; the output terminal of the error operational amplifier U2 is the output terminal VCOMP pin of the error amplification and compensation circuit, generating the control voltage VCOMP.

[0013] Optionally, the clock generator includes: an OR gate U14, a switch S3, a capacitor C_CLK, a switching frequency current source I_CLK, and a comparator U3; the first input terminal of the OR gate U14 is the PFM pin of the clock generator, connected to the light-load high-efficiency mode indication signal PFM; the second input terminal of the OR gate U14 is connected to the output terminal of the comparator U3; the output terminal of the OR gate U14 is connected to the control terminal of the switch S3; one end of the switch S3 is connected to one end of the capacitor C_CLK and the non-inverting input terminal of the comparator U3; the other end of the switch S3... The other end of the capacitor C_CLK is connected to the reference voltage VREF3; the inverting input of the comparator U3 is connected to the reference voltage VREF3; the output of the comparator U3 is the output CLK pin of the clock generator, generating the clock signal CLK; the input of the switching frequency current source I_CLK is connected to the power supply voltage VCC, and the output of the switching frequency current source I_CLK is connected to the non-inverting input of the comparator U3; the non-inverting input of the comparator U3 is the output VSP pin of the clock generator, generating the ramp voltage compensation signal VSP.

[0014] Optionally, the slope compensation circuit includes: a voltage follower U4 and a voltage follower U5; the non-inverting input terminal of the voltage follower U5 is the non-inverting input pin of the slope compensation circuit and is connected to the control voltage VCOMP; the non-inverting input terminal of the voltage follower U4 is the inverting input pin of the slope compensation circuit and is connected to the slope voltage compensation signal VSP; the inverting input terminal of the voltage follower U4 is grounded; the output terminal of the voltage follower U4 is connected to the inverting input terminal of the voltage follower U5; the output terminal of the voltage follower U5 is the output pin of the slope compensation circuit, generating a control signal VSET.

[0015] Optionally, the PFM fixed on-time generation circuit includes: a switch S4, a resistor R_ON, a capacitor C_ON, a diode D1, a voltage follower U6, a comparator U7, and an RS latch U8; the control terminal of the switch S4 is the input terminal CLK pin of the PFM fixed on-time generation circuit, connected to the clock signal CLK; one end of the resistor R_ON is the input terminal VIN pin of the PFM fixed on-time generation circuit, connected to the input voltage VIN; the other end of the resistor R_ON is connected to one end of the switch S4, one end of the capacitor C_ON, the positive terminal of the diode D1, and the non-inverting input terminal of the comparator U7; the negative terminal of the diode D1 is connected to the power supply voltage. VCC; the other end of switch S4, the other end of capacitor C_ON, and the inverting input of voltage follower U6 are grounded; the non-inverting input of voltage follower U6 is the input VOUT pin of the PFM fixed on-time generation circuit, connected to the output voltage VOUT; the output of voltage follower U6 is connected to the inverting input of comparator U7; the output of comparator U7 is connected to the R input of RS latch U8; the S input of RS latch U8 is connected to the clock signal CLK; the non-inverting output of RS latch U8 is the output TON_PFM pin of the PFM fixed on-time generation circuit, generating the PFM control signal TON_PFM.

[0016] Optionally, the fixed-frequency PWM on-time generation circuit includes: a comparator U9 and an RS latch U10; the non-inverting input of the comparator U9 is the IHS pin of the fixed-frequency PWM on-time generation circuit, connected to the upper transistor sampling current IHS; the inverting input of the comparator U9 is the VSET pin of the fixed-frequency PWM on-time generation circuit, connected to the control signal VSET; the output of the comparator U9 is connected to the R input of the RS latch U10; the S input of the RS latch U10 is the CLK pin of the fixed-frequency PWM on-time generation circuit, connected to the clock signal CLK; the non-inverting output of the RS latch U10 is the TON_PWM pin of the fixed-frequency PWM on-time generation circuit, generating the PWM control signal TON_PWM.

[0017] Optionally, the OR gate logic circuit includes: an OR gate U12; the first input terminal of the OR gate U12 is the first input terminal pin of the OR gate logic circuit, connected to the PFM control signal TON_PFM; the second input terminal of the OR gate U12 is the second input terminal pin of the OR gate logic circuit, connected to the PWM control signal TON_PWM; the output terminal of the OR gate U12 is the output terminal pin of the OR gate logic circuit, generating the control signal TON.

[0018] The zero-crossing detection circuit includes: a comparator U11; the non-inverting input terminal of the comparator U11 is the input terminal SW pin of the zero-crossing detection circuit, connected to the switching voltage SW; the inverting input terminal of the comparator U11 is connected to the zero-current detection reference voltage VZCD; the output terminal of the comparator U11 is the output terminal ZCD pin of the zero-crossing detection circuit, generating a control signal ZCD.

[0019] Optionally, the switching power stage includes: an upper power transistor S1 and a lower power transistor S2; the gate of the upper power transistor S1 is the input terminal HS pin of the switching power stage, connected to the upper transistor drive signal HS; the drain of the upper power transistor S1 is the input terminal VIN pin of the switching power stage, connected to the input voltage VIN; the input voltage VIN is sampled to obtain the upper transistor sampling current HIS, which is led out as the output terminal IHS pin of the switching power stage; the source of the upper power transistor S1 is the output terminal SW pin of the switching power stage, generating a switching voltage SW; the gate of the lower power transistor S2 is the input terminal LS pin of the switching power stage, connected to the lower transistor drive signal LS; the drain of the lower power transistor S2 is connected to the source of the upper power transistor S1; the source of the lower power transistor S2 is grounded.

[0020] A fixed-frequency PWM control method based on a fixed on-time, comprising the aforementioned fixed-frequency PWM controller; the fixed-frequency PWM control method includes:

[0021] The filtering and feedback circuit filters the switching voltage SW through an LC filter to obtain an output voltage VOUT, which is then used to power the external load. The output voltage VOUT is fed back by the voltage sampling of the filtering and feedback circuit to obtain a sampling feedback voltage FB.

[0022] The PFM comparator circuit compares the sampled feedback voltage FB with the PFM mode reference voltage VREF2 to obtain the light-load high-efficiency mode indication signal PFM.

[0023] The error amplification and compensation circuit sends the sampled feedback voltage FB into the internal circuit for amplification and compensation processing, and then generates the control voltage VCOMP.

[0024] The clock generator works in conjunction with the light-load high-efficiency mode indication signal PFM to generate the clock signal CLK and the ramp voltage compensation signal VSP.

[0025] The ramp compensation circuit generates a control signal VSET based on the control voltage VCOMP and the ramp voltage compensation signal VSP.

[0026] The PFM fixed on-time generation circuit is triggered by the clock signal CLK at the beginning of each cycle to perform fixed on-time timing, generating a PFM control signal TON_PFM that is phase and frequency matched with the clock signal CLK, determined by the input voltage VIN and the output voltage VOUT, and has a fixed duty cycle.

[0027] The fixed-frequency PWM conduction time generation circuit is triggered by the clock signal CLK at the beginning of each cycle, generating a PWM control signal TON_PWM with a non-fixed duty cycle that is phase and frequency matched with the clock signal CLK and determined by the control signal VSET and the sampling current IHS of the upper tube.

[0028] The zero-crossing detection circuit compares the switching voltage SW with a preset negative current threshold to generate the control signal ZCD.

[0029] The OR gate logic circuit generates a control signal TON based on the PFM control signal TON_PFM and the PWM control signal TON_PWM, with the minimum time to clamp the upper power transistor S1 to be turned on being TON_PFM.

[0030] The PWM logic and driving circuit generate the upper transistor driving signal HS and the lower transistor driving signal LS, which are inversely phase with the upper transistor driving signal HS and have a certain dead time, according to the control signal ZCD and the control signal TON.

[0031] The switching power stage controls the conduction of the upper power transistor S1 and the lower power transistor S2 according to the upper transistor drive signal HS and the lower transistor drive signal LS; the input voltage VIN is processed by the upper and lower power transistors of the switching power stage to obtain the switching voltage SW, and when the upper power transistor S1 is turned on, the current of the upper power transistor S1 is sampled to obtain the upper transistor sampling current IHS.

[0032] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0033] This invention provides a fixed-frequency PWM controller and control method based on a fixed on-time. The fixed-frequency PWM controller includes: a filtering and feedback circuit, a PFM comparator circuit, an error amplification and compensation circuit, a clock generator, a ramp compensation circuit, a PFM fixed on-time generation circuit, a fixed-frequency PWM on-time generation circuit, a zero-crossing detection circuit, an OR gate logic circuit, a PWM logic and drive circuit, and a switching power stage. This invention, with OR gate logic and a PFM comparator circuit as its core, realizes the entry and exit of the DC / DC controller between fixed-frequency PWM mode and light-load frequency conversion mode. Its circuit structure and control logic are simple, easy to implement, and feature high efficiency under light loads. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A schematic diagram of the overall structure of a fixed-frequency PWM controller based on a fixed on-time provided in an embodiment of the present invention;

[0036] Figure 2 A schematic diagram of the specific circuit connection of a fixed-frequency PWM controller based on a fixed conduction time provided in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of the simulation results of the fixed-frequency PWM control method based on fixed conduction time provided in an embodiment of the present invention. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] The purpose of this invention is to provide a fixed-frequency PWM controller and control method based on a fixed conduction time, so as to achieve high-efficiency DC / DC conversion under light load using a relatively simple circuit structure and control logic.

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Figure 1 This is a schematic diagram of the overall structure of a fixed-frequency PWM controller based on a fixed on-time, as provided in an embodiment of the present invention. See also... Figure 1 The fixed-frequency PWM controller based on fixed on-time includes: a filtering and feedback circuit 1, a PFM comparator circuit 2, an error amplification and compensation circuit 3, a clock generator 4, a ramp compensation circuit 5, a PFM fixed on-time generation circuit 6, a fixed-frequency PWM on-time generation circuit 7, a zero-crossing detection circuit 8, an OR gate logic circuit 9, a PWM logic and drive circuit 10, and a switching power stage 11.

[0042] See Figure 1The output pin SW of the switching power stage is connected to the input pin SW of the filtering and feedback circuit and the input pin SW of the zero-crossing detection circuit, respectively. The output pin VOUT of the filtering and feedback circuit is connected to the input pin VOUT of the PFM fixed on-time generation circuit. The output pin VOUT of the filtering and feedback circuit generates an output voltage VOUT to power an external load. The output pin FB of the filtering and feedback circuit is connected to the non-inverting input pin of the PFM comparator circuit and the input pin FB of the error amplification and compensation circuit, respectively. The inverting input pin of the PFM comparator circuit is connected to the PFM mode reference voltage VREF2. The output pin VCOMP of the error amplification and compensation circuit is connected to the non-inverting input pin of the ramp compensation circuit. The input pin PFM of the clock generator is connected to the output pin of the PFM comparator circuit. The output pin CLK of the clock generator is connected to the input pin CLK of the PFM fixed on-time generation circuit and the input pin CLK of the fixed-frequency PWM on-time generation circuit, respectively. The output pin VSP of the clock generator is connected to the ramp compensation circuit. The inverting input pin of the ramp compensation circuit; the input VIN pin of the PFM fixed on-time generation circuit is connected to the input voltage VIN; the input VSET pin of the fixed-frequency PWM on-time generation circuit is connected to the output pin of the ramp compensation circuit; the input IHS pin of the fixed-frequency PWM on-time generation circuit is connected to the output IHS pin of the switching power stage; the output TON_PFM pin of the PFM fixed on-time generation circuit is connected to the first input pin of the OR gate logic circuit; the output TON_PWM pin of the fixed-frequency PWM on-time generation circuit is connected to the second input pin of the OR gate logic circuit; the output pin of the OR gate logic circuit is connected to the input TON pin of the PWM logic and drive circuit; the input ZCD pin of the PWM logic and drive circuit is connected to the output ZCD pin of the zero-crossing detection circuit; the output HS pin of the PWM logic and drive circuit is connected to the input HS pin of the switching power stage; the output LS pin of the PWM logic and drive circuit is connected to the input LS pin of the switching power stage; the input VIN pin of the switching power stage is connected to the input voltage VIN.

[0043] The filtering and feedback circuit 1 has one input pin (SW) and two output pins (FB and VOUT). The switching voltage SW connected to the input pin (SW) is one of the outputs of the switching power stage 11. After filtering, the switching voltage SW yields the output voltage VOUT, which supplies power to the external load. The output voltage VOUT is then fed back to the sampling feedback voltage FB via voltage sampling feedback and connected to the input of the error amplification and compensation circuit 3.

[0044] For example, the PFM comparator circuit 2 can be composed of comparator U1, whose non-inverting input is the sampling feedback voltage FB and the inverting input is the PFM mode reference voltage VREF2. When the FB voltage is greater than VREF2, the light load high efficiency mode indication signal PFM is 1 and is transmitted to the clock generator 4.

[0045] The error amplification and compensation circuit 3 has an input pin FB and an output pin VCOMP. After the FB signal is amplified and compensated internally, it generates a control voltage signal VCOMP, which is then sent to the ramp compensation circuit 5.

[0046] Clock generator 4 and light-load high-efficiency mode indicator signal PFM work together to generate CLK clock and ramp voltage compensation signal VSP, which are respectively sent to PFM fixed conduction time generation circuit 6 and fixed frequency PWM conduction time generation circuit 7.

[0047] The ramp compensation circuit 5 takes VCOMP as positive and VSP as negative to perform ramp compensation, and generates a control signal VSET which is transmitted to the fixed frequency PWM conduction time generation circuit 7 for control.

[0048] The PFM fixed on-time generation circuit 6 has three inputs: input voltage VIN, output voltage VOUT, and clock signal CLK. At the beginning of each cycle, the clock signal CLK triggers the circuit to perform a fixed on-time timing. Before the timing ends, the TON_PFM signal is 1; after the timing ends, the TON_PFM signal is 0. It can be seen that the TON_PFM signal and the clock signal CLK are phase and frequency matched, and a PFM control signal TON_PFM with a fixed duty cycle determined by VIN and VOUT is generated.

[0049] The fixed-frequency PWM conduction time generation circuit 7 has three inputs: a clock signal CLK, a control signal VSET, and the upper transistor sampling current IHS. Its output is the PWM control signal TON_PWM. At the beginning of each cycle, the clock signal CLK triggers TON_PWM to be 1. When the upper transistor sampling current IHS rises to VSET, TON_PWM is pulled low to 0. It can be seen that the output TON_PWM signal generated by the fixed-frequency PWM conduction time generation circuit 7 is also phase- and frequency-matched with CLK, and generates a control signal TON_PWM with a non-fixed duty cycle determined by the control signal VSET and the upper transistor current peak value IHS.

[0050] The zero-crossing detection circuit 8 compares the switching voltage SW with the preset negative current threshold. When the voltage of SW is higher than the reference value when the lower power transistor S2 is turned on, that is, when the negative current of the lower power transistor S2 is higher than the preset value, the ZCD signal is 1 and is sent to the PWM logic and drive circuit for control.

[0051] The inputs of OR gate logic circuit 9 are control signals TON_PFM and TON_PWM. This OR gate logic will clamp the power transistor S1 to conduct for a minimum time of TON_PFM. If the TON_PWM signal is low and the TON_PFM signal is high, the output of the OR gate logic is high, i.e., 1.

[0052] The PWM trigger and driver 10 have two inputs: TON and ZCD signals. The on-time of the upper transistor is controlled by TON, generating the upper transistor drive signal HS and the lower transistor drive signal LS, which is inversely phase to HS and has a certain dead time. If the ZCD signal is 1 when the lower power transistor S2 is on, then LS is pulled low to 0, and the lower power transistor S2 is turned off.

[0053] The input to the switching power stage 11 consists of the upper transistor drive signal HS, the lower transistor drive signal LS, and the input voltage VIN. When HS is high, the upper power transistor S1 in the Buck circuit is turned on; when LS is high, the lower power transistor S2 in the Buck circuit is turned on. VIN is processed by the upper and lower power transistors to obtain the SW voltage, which is then fed into the filter and feedback circuit 1 for filtering. When the upper power transistor S1 is turned on, the upper transistor current IHS is sampled.

[0054] When the load decreases, the error amplification and compensation circuit 3 controls the reduction of VSET, the peak current of the upper transistor IHS decreases, and the average inductor current decreases. If the load continues to decrease to a light load, causing the minimum inductor current to cross zero, the zero-crossing detection circuit 8 starts working, forcing the lower power transistor S2 to turn off when the inductor current crosses zero to a preset value. Afterward, the error amplification and compensation circuit 3 continues to reduce VSET, and the duty cycle of the control signal TON_PWM generated by the fixed-frequency PWM conduction time generation circuit 7 decreases. When the duty cycle decreases to less than the duty cycle of the control signal TON_PFM, the OR gate logic circuit 9 clamps the duty cycle of TON to TON_PFM. Since the duty cycle remains unchanged, the decrease in load causes the power output of the switching power stage 11 to exceed the actual power required by the load, and the output voltage begins to rise. When the sampling voltage FB rises above VREF2, the PFM signal is high, the clamping clock generator 4 is 0, the clock CLK is 0, and the upper power transistor S1 is no longer turned on. Afterward, the controller enters the IDLE state, waiting for FB to fall back to VREF2. When it falls back to VREF2, the clock CLK is high, and the upper power transistor S1 is turned on for a fixed conduction time TON_PFM before being turned off. The FB voltage rises above VREF2, and the controller enters the IDLE state again. If the load continues to decrease to a very light load, the fallback of FB to VREF2 will be slower, and the controller will remain in the IDLE state for a longer period. Subsequently, the switching frequency is affected by the load; the lighter the load, the lower the switching frequency. This achieves the control effect of fixed frequency under heavy load and reduced frequency under light load.

[0055] Figure 2This is a schematic diagram of the specific circuit connection of a fixed-frequency PWM controller based on a fixed on-time, provided in an embodiment of the present invention. See also... Figure 2 The filtering and feedback circuit 1 includes: an inductor L, an output capacitor C, an upper voltage divider resistor R1, and a lower voltage divider resistor R2; one end of the inductor L is the input terminal SW pin of the filtering and feedback circuit, connected to the switching voltage SW generated by the output terminal SW pin of the switching power stage; the other end of the inductor L is connected to one end of the output capacitor C and one end of the upper voltage divider resistor R1; the other end of the upper voltage divider resistor R1 is connected to one end of the lower voltage divider resistor R2; the other end of the lower voltage divider resistor R2 and the other end of the output capacitor C are both grounded; the other end of the inductor L is the output terminal VOUT pin of the filtering and feedback circuit, generating the output voltage VOUT; the other end of the upper voltage divider resistor R1 is the output terminal FB pin of the filtering and feedback circuit, generating the sampling feedback voltage FB.

[0056] As can be seen, the filter and feedback circuit 1 consists of an inductor L, an output capacitor C, an upper voltage divider resistor R1, and a lower voltage divider resistor R2. The switching voltage SW is filtered by an LC filter to obtain the output voltage VOUT. R1 and R2 sample VOUT to obtain the voltage divider FB, which represents the voltage information of VOUT.

[0057] See Figure 2 The PFM comparator circuit 2 includes: a comparator U1; the non-inverting input terminal of the comparator U1 is the non-inverting input pin of the PFM comparator circuit and is connected to the sampling feedback voltage FB; the inverting input terminal of the comparator U1 is the inverting input pin of the PFM comparator circuit and is connected to the PFM mode reference voltage VREF2; the output terminal of the comparator U1 is the output pin of the PFM comparator circuit, generating a light-load high-efficiency mode indication signal PFM.

[0058] As can be seen, the PFM comparator circuit 2 consists of a PFM mode reference VREF2 and a comparator U1. When the FB voltage is greater than VREF2, PFM is 1. The voltage of VREF2 is greater than the PWM mode reference VREF.

[0059] See Figure 2 The error amplification and compensation circuit 3 includes: an error operational amplifier U2; the non-inverting input terminal of the error operational amplifier U2 is connected to the PWM mode reference voltage VREF; the inverting input terminal of the error operational amplifier U2 is the input terminal FB pin of the error amplification and compensation circuit, which is connected to the sampling feedback voltage FB; the output terminal of the error operational amplifier U2 is the output terminal VCOMP pin of the error amplification and compensation circuit, which generates the control voltage VCOMP.

[0060] As can be seen, the error amplification and compensation circuit 3 consists of a PWM mode reference base VREF and an error operational amplifier U2. The FB voltage is compared with VREF and then amplified to obtain the VCOMP control voltage, which is then supplied to the slope compensation circuit 5.

[0061] See Figure 2 The clock generator 4 includes: an OR gate U14, a switch S3, a capacitor C_CLK, a switching frequency current source I_CLK, and a comparator U3; the first input terminal of the OR gate U14 is the PFM pin of the clock generator, connected to the light-load high-efficiency mode indication signal PFM; the second input terminal of the OR gate U14 is connected to the output terminal of the comparator U3; the output terminal of the OR gate U14 is connected to the control terminal of the switch S3; one end of the switch S3 is connected to one end of the capacitor C_CLK and the non-inverting input terminal of the comparator U3; the other end of the switch S3... The other end of the capacitor C_CLK is connected to the reference voltage VREF3; the inverting input of the comparator U3 is connected to the reference voltage VREF3; the output of the comparator U3 is the output CLK pin of the clock generator, generating the clock signal CLK; the input of the switching frequency current source I_CLK is connected to the power supply voltage VCC, and the output of the switching frequency current source I_CLK is connected to the non-inverting input of the comparator U3; the non-inverting input of the comparator U3 is the output VSP pin of the clock generator, generating the ramp voltage compensation signal VSP.

[0062] As can be seen, the clock generator 4 consists of switch S3, capacitor C_CLK, switching frequency current source I_CLK, reference VREF3, and comparator U3. At the beginning of each cycle, CLK is high, switch S3 resets the voltage across C_CLK, the non-inverting input of U3 is 0, and the output of U3 is low. If PFM is low, S3 does not reset C_CLK, I_CLK charges C_CLK, and when the non-inverting input of U3 is higher than VREF, CLK is high, and S3 resets C_CLK. From the working principle of the clock generator, it can be seen that the output clock frequency is determined by C_CLK and I_CLK, and the duration of CLK being high each time is determined by the conduction delay of comparator U3. Changing C_CLK or I_CLK changes the switching frequency. When PFM is 1, the clamped clock output CLK is low and no longer participates in external control. When capacitor C_CLK charges and discharges with CLK as the cycle, a ramp voltage VSP with the same frequency as the CLK clock is generated across its terminals.

[0063] See Figure 2The slope compensation circuit 5 includes a voltage follower U4 and a voltage follower U5. The non-inverting input of the voltage follower U5 is the non-inverting input pin of the slope compensation circuit and is connected to the control voltage VCOMP. The non-inverting input of the voltage follower U4 is the inverting input pin of the slope compensation circuit and is connected to the slope voltage compensation signal VSP. The inverting input of the voltage follower U4 is grounded. The output of the voltage follower U4 is connected to the inverting input of the voltage follower U5. The output of the voltage follower U5 is the output pin of the slope compensation circuit, generating a control signal VSET.

[0064] Voltage followers U4 and U5 are both 1:1 voltage followers. The ramp compensation circuit 5 takes the ramp signal VSP generated by the clock generator, passes it through U4 in a 1:1 ratio, and sends it to U5. After comparing it with the VCOMP control voltage, the resulting VSET signal is sent to the fixed-frequency PWM on-time generator 7.

[0065] See Figure 2 The PFM fixed on-time generation circuit 6 includes: a switch S4, a resistor R_ON, a capacitor C_ON, a diode D1, a voltage follower U6, a comparator U7, and an RS latch U8. The control terminal of the switch S4 is the input terminal CLK pin of the PFM fixed on-time generation circuit, connected to the clock signal CLK. One end of the resistor R_ON is the input terminal VIN pin of the PFM fixed on-time generation circuit, connected to the input voltage VIN. The other end of the resistor R_ON is connected to one end of the switch S4, one end of the capacitor C_ON, the positive terminal of the diode D1, and the non-inverting input terminal of the comparator U7. The negative terminal of the diode D1 is connected to the power supply voltage V. CC; the other end of the switch S4, the other end of the capacitor C_ON, and the inverting input of the voltage follower U6 are grounded; the non-inverting input of the voltage follower U6 is the input VOUT pin of the PFM fixed on-time generation circuit, connected to the output voltage VOUT; the output of the voltage follower U6 is connected to the inverting input of the comparator U7; the output of the comparator U7 is connected to the R input of the RS latch U8; the S input of the RS latch U8 is connected to the clock signal CLK; the non-inverting output of the RS latch U8 is the output TON_PFM pin of the PFM fixed on-time generation circuit, generating the PFM control signal TON_PFM.

[0066] Among them, voltage follower U6 is a 1:0.8 voltage follower. The input of PFM fixed conduction time generation circuit 6 is VIN, VOUT and CLK, and the output is a TON_PFM signal with a fixed duty cycle and frequency and phase consistent with CLK. Its working principle is as follows: at the beginning of each cycle, CLK is high, S4 resets capacitor C_ON, U7 outputs low, U8 outputs TON_PFM high, after CLK is low, S4 no longer resets C_ON, and then VIN charges C_ON through R_ON. When the voltage across C_ON is charged to 0.8 times VOUT, U7 outputs high, resets U8, and TON_PFM is pulled low. From the working principle, it can be seen that the frequency and phase of the TON_PFM signal and the CLK clock signal are matched, and its high level time depends on the product of VIN, VOUT and R_ON and C_ON. Formula (1) gives the conduction time of the upper power transistor S1 in each cycle when the Buck circuit efficiency is 100% in PWM mode. Among them, T ON For the conduction time, F SW V is the switching frequency. OUT V is the output voltage value. IN The output voltage value. Formula (2) is the time TON_PFM is high for each cycle of the PFM fixed on-time generator 6. ON By setting RC, i.e., the product of the resistance R of R_ON and the capacitance C of C_ON, to be consistent with the switching cycle, we can obtain the PWM mode on-time T, where the high-time of each TON_PFM cycle is 0.8 times. ON_PFM .

[0067]

[0068]

[0069] See Figure 2 The fixed-frequency PWM on-time generation circuit 7 includes: a comparator U9 and an RS latch U10; the non-inverting input of the comparator U9 is the IHS pin of the fixed-frequency PWM on-time generation circuit, connected to the upper transistor sampling current IHS; the inverting input of the comparator U9 is the VSET pin of the fixed-frequency PWM on-time generation circuit, connected to the control signal VSET; the output of the comparator U9 is connected to the R input of the RS latch U10; the S input of the RS latch U10 is the CLK pin of the fixed-frequency PWM on-time generation circuit, connected to the clock signal CLK; the non-inverting output of the RS latch U10 is the TON_PWM pin of the fixed-frequency PWM on-time generation circuit, generating the PWM control signal TON_PWM.

[0070] As can be seen, the fixed-frequency PWM conduction time generation circuit 7 consists of comparator U9 and RS latch U10. At the beginning of each cycle, CLK is pulled high to set the SET input of U10 to high, and the output TON_PWM of U10 is high. After the upper power transistor S1 is turned on, the IHS current increases. When it increases to VSET, the output of U9 flips to high, resetting the output of U10 to low, and TON_PWM is pulled low.

[0071] See Figure 2 The zero-crossing detection circuit 8 includes: a comparator U11; the non-inverting input terminal of the comparator U11 is the input terminal SW pin of the zero-crossing detection circuit, connected to the switching voltage SW; the inverting input terminal of the comparator U11 is connected to the zero-current detection reference voltage VZCD; the output terminal of the comparator U11 is the output terminal ZCD pin of the zero-crossing detection circuit, generating a control signal ZCD.

[0072] The zero-crossing detection circuit 8 is essential for implementing the control method of this invention. It allows the controller to enter an intermittent operating state under light load, thereby reducing the conduction time in conjunction with the fixed-frequency PWM conduction time generator 7. The zero-crossing detection circuit 8 consists of a zero-current detection reference VZCD and a comparator U11. When the lower power transistor S2 is turned on, the voltage SW is sampled. If SW is greater than VZCD, it indicates that the current of the lower power transistor S2 has crossed zero. Afterward, ZCD is 1, which is then fed to the PWM logic and drive circuit 10.

[0073] See Figure 2 The OR gate logic circuit 9 includes: an OR gate U12; the first input terminal of the OR gate U12 is the first input terminal pin of the OR gate logic circuit, connected to the PFM control signal TON_PFM; the second input terminal of the OR gate U12 is the second input terminal pin of the OR gate logic circuit, connected to the PWM control signal TON_PWM; the output terminal of the OR gate U12 is the output terminal pin of the OR gate logic circuit, generating the control signal TON.

[0074] OR gate logic circuit 9 is the key circuit for implementing the control logic of this invention. Its logic limits the on-time of output TON to a minimum of TON_PFM. If the high time of each cycle of TON_PWM is greater than TON_PFM, then the output of U12 is TON_PWM.

[0075] See Figure 2 The PWM trigger and drive circuit 10 is typically implemented using a control chip U13. The PWM trigger and drive circuit 10 processes TON into a PWM signal, which is then fed to the switching power stage to control the on and off states of the upper power transistor S1 and the lower power transistor S2. When the load is lightly loaded, and the lower power transistor S2 is on, if ZCD is 1, then the lower power transistor S2 is turned off.

[0076] See Figure 2 The switching power stage 11 includes an upper power transistor S1 and a lower power transistor S2; both upper power transistor S1 and lower power transistor S2 are NMOS transistors. The gate of the upper power transistor S1 is the input terminal HS pin of the switching power stage, connected to the upper transistor drive signal HS; the drain of the upper power transistor S1 is the input terminal VIN pin of the switching power stage, connected to the input voltage VIN; the input voltage VIN is sampled to obtain the upper transistor sampling current HIS, which is led out as the output terminal IHS pin of the switching power stage; the source of the upper power transistor S1 is the output terminal SW pin of the switching power stage, generating the switching voltage SW; the gate of the lower power transistor S2 is the input terminal LS pin of the switching power stage, connected to the lower transistor drive signal LS; the drain of the lower power transistor S2 is connected to the source of the upper power transistor S1; the source of the lower power transistor S2 is grounded.

[0077] This invention utilizes a fixed-frequency PWM controller with a fixed on-time. When the load is heavy, the on-time of the fixed-frequency PWM on-time generation circuit 7 (TON_PWM) will always be greater than TON_PFM, and the output of the OR gate logic circuit 9 will be the normal on-time required for the fixed-frequency PWM mode. When the load is light, the zero-crossing detection circuit 8 will prematurely turn off the lower power transistor S2, causing the output voltage to rise during the original TON_PWM on-time. The error amplification and compensation module will control VCOMP and VSET to decrease, resulting in IHS triggering VSET earlier each cycle, and TON_PWM decreasing synchronously. When it decreases to less than the fixed on-time TON_PFM, the OR gate logic circuit 9 will operate, and thereafter the upper transistor's on-time will be clamped at the fixed TON_PFM each cycle. As the load continues to decrease, because the energy output by the controller in each cycle is greater than the energy required by the load itself, the output VOUT and FB increase. When FB is higher than VREF2, the output PFM of PFM comparator circuit 2 is high, and the output of clamp clock generator 4 is always low. After that, TON_PFM remains 0, and the controller no longer turns on the upper power transistor S1 or the lower power transistor S2, and enters the IDLE waiting state. When FB drops to VREF2, the PFM signal is pulled low, and after clock generator 4 counts a new CLK, the TON_PFM signal goes high.

[0078] As the working principle shows, transitioning from PWM to PFM mode requires TON_PFM to be higher than TON_PWM and FB to be greater than VREF2, making the PFM signal high. If the load increases, because the clock generator needs to restart the clock by one CLK after each FB encounters VREF2 before TON_PFM can go high and turn on the power transistor S1, this structure determines that the maximum duty cycle of PFM mode is less than the duty cycle required under heavy load. The energy output by the controller in each cycle will be less than the energy required by the load, the output voltage will be pulled low, and the controller will exit PFM and return to PWM mode.

[0079] The core of this invention, a fixed-frequency PWM controller based on a fixed on-time, consists of an OR gate and an FB-VREF2 comparator. This enables the DC / DC controller to enter and exit fixed-frequency PWM mode and light-load inverter mode. The structure is simple and easy to implement. When the on-time predicted by COMP is less than the preset fixed on-time, the on-time is clamped to the preset fixed on-time, after which the output begins to rise, and the controller enters COT control with VREF2 as the new reference. Whenever the voltage divider FB of VOUT touches VREF2, the controller controls the upper power transistor S1 to turn on for the preset on-time. The smaller the load, the slower the voltage divider FB of VOUT returns to VREF2, and the lower the frequency at which the upper power transistor S1 is turned on. When the load suddenly becomes heavy, the comparator no longer participates in the control, the on-time is naturally set by COMP, and the controller returns to the PWM fixed-frequency control mode.

[0080] In the embodiments and figures of this application, various pins such as SW pin, CLK pin, VIN pin, VSET pin, FB pin, VSP pin, IHS pin, LS pin, etc. are abbreviated in English for the convenience of description and reference. These abbreviations do not constitute a limitation on the pin type or function. Those skilled in the art can replace them with other expressions without creative effort. Any change in the expression of a pin is a specific implementation of the embodiments of this application.

[0081] Based on the aforementioned fixed-frequency PWM controller, the present invention also provides a fixed-frequency PWM control method based on a fixed on-time, the fixed-frequency PWM control method comprising:

[0082] The filtering and feedback circuit filters the switching voltage SW through an LC filter to obtain an output voltage VOUT, which is then used to power the external load. The output voltage VOUT is fed back by the voltage sampling of the filtering and feedback circuit to obtain a sampling feedback voltage FB.

[0083] The PFM comparator circuit compares the sampled feedback voltage FB with the PFM mode reference voltage VREF2 to obtain the light-load high-efficiency mode indication signal PFM.

[0084] The error amplification and compensation circuit sends the sampled feedback voltage FB into the internal circuit for amplification and compensation processing, and then generates the control voltage VCOMP.

[0085] The clock generator works in conjunction with the light-load high-efficiency mode indication signal PFM to generate a clock signal CLK and a ramp voltage compensation signal VSP.

[0086] The ramp compensation circuit generates a control signal VSET based on the control voltage VCOMP and the ramp voltage compensation signal VSP.

[0087] The PFM fixed on-time generation circuit is triggered by the clock signal CLK at the beginning of each cycle to perform fixed on-time timing, generating a PFM control signal TON_PFM that is phase and frequency matched with the clock signal CLK, determined by the input voltage VIN and the output voltage VOUT, and has a fixed duty cycle.

[0088] The fixed-frequency PWM conduction time generation circuit is triggered by the clock signal CLK at the beginning of each cycle, generating a PWM control signal TON_PWM with a non-fixed duty cycle that is phase and frequency matched with the clock signal CLK and determined by the control signal VSET and the upper transistor sampling current IHS.

[0089] The zero-crossing detection circuit compares the switching voltage SW with a preset negative current threshold to generate a control signal ZCD.

[0090] The OR gate logic circuit generates a control signal TON based on the PFM control signal TON_PFM and the PWM control signal TON_PWM, with the minimum time to clamp the upper transistor to conduct being TON_PFM.

[0091] The PWM logic and driving circuit generate an upper transistor driving signal HS and a lower transistor driving signal LS that is inversely related to the upper transistor driving signal HS and has a certain dead time according to the control signal ZCD and the control signal TON.

[0092] The switching power stage controls the conduction of the upper power transistor S1 and the lower power transistor S2 according to the upper transistor drive signal HS and the lower transistor drive signal LS; the input voltage VIN is processed by the upper and lower power transistors of the switching power stage to obtain the switching voltage SW, and when the upper power transistor S1 is turned on, the current of the upper power transistor S1 is sampled to obtain the upper transistor sampling current IHS.

[0093] Existing light-load frequency converter control requires complex control logic, necessitating numerous logic circuits and clock synchronization, and additional control circuitry to extend the turn-off time or clock cycle to reduce the switching frequency under light load conditions. This invention utilizes the characteristic of Constant On-Time (COT) control mode automatically entering frequency converter control under light load conditions. This allows the fixed-frequency PWM controller to automatically enter light-load frequency conversion by clamping the on-time, resulting in simple logic. Furthermore, the controller logic and control method provided by this invention can be used in various clock-based fixed-frequency DC / DC circuits, exhibiting strong portability and low implementation difficulty.

[0094] Figure 3 Simulation results of the control method of this invention are shown, with time on the horizontal axis and output voltage VOUT on the vertical axis. Figure 3 As can be seen, the initial load was 2A, and at 1ms, the load decreased to 5mA at a slope of 2A / µs; at 3ms, the load suddenly increased to 2.005A at a slope of 2A / µs. From Figure 3 It can be seen that the control method of the present invention effectively meets the requirements of light-load frequency conversion, reduces the switching frequency under light load, and improves the efficiency under light load.

[0095] The fixed-frequency PWM controller and control method based on fixed on-time provided by this invention are applied to clock-based fixed-frequency PWM DC / DC converters. By employing a fixed on-time approach, the converter automatically adjusts its frequency when entering light-load operation, reducing switching-related losses and ensuring high efficiency under light loads. Furthermore, the controller circuit and control method of this invention are highly versatile and simple in structure, applicable to various operating conditions and topologies. Moreover, the single-pulse control ensures minimal output voltage ripple, demonstrating broad application prospects.

[0096] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the control method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A fixed-frequency PWM controller based on a fixed on-time, characterized in that, include: Filtering and feedback circuits, PFM comparator circuits, error amplification and compensation circuits, clock generators, ramp compensation circuits, PFM fixed on-time generation circuits, fixed-frequency PWM on-time generation circuits, zero-crossing detection circuits, OR gate logic circuits, PWM logic and drive circuits, and switching power stages; The output pin SW of the switching power stage is connected to the input pin SW of the filtering and feedback circuit and the input pin SW of the zero-crossing detection circuit, respectively; the output pin VOUT of the filtering and feedback circuit is connected to the input pin VOUT of the PFM fixed on-time generation circuit; the output pin VOUT of the filtering and feedback circuit generates an output voltage VOUT to power the external load. The output pin FB of the filtering and feedback circuit is connected to the non-inverting input pin of the PFM comparator circuit and the input pin FB of the error amplification and compensation circuit, respectively; the inverting input pin of the PFM comparator circuit is connected to the PFM mode reference voltage VREF2; the output pin VCOMP of the error amplification and compensation circuit is connected to the non-inverting input pin of the ramp compensation circuit; the input pin PFM of the clock generator is connected to the output pin of the PFM comparator circuit; the output pin CLK of the clock generator is connected to the input pin CLK of the PFM fixed on-time generation circuit and the input pin CLK of the fixed-frequency PWM on-time generation circuit, respectively; the output pin VSP of the clock generator is connected to the inverting input pin of the ramp compensation circuit; the input pin VIN of the PFM fixed on-time generation circuit is connected to the input voltage VIN; the input pin VSET of the fixed-frequency PWM on-time generation circuit is connected to the output pin of the ramp compensation circuit; the input pin IHS of the fixed-frequency PWM on-time generation circuit is connected to the output pin IHS of the switching power stage. The output pin TON_PFM of the PFM fixed on-time generator circuit is connected to the first input pin of the OR gate logic circuit; the output pin TON_PWM of the fixed-frequency PWM on-time generator circuit is connected to the second input pin of the OR gate logic circuit; the output pin of the OR gate logic circuit is connected to the input pin TON of the PWM logic and drive circuit; the input pin ZCD of the PWM logic and drive circuit is connected to the output pin ZCD of the zero-crossing detection circuit; the output pin HS of the PWM logic and drive circuit is connected to the input pin HS of the switching power stage; the output pin LS of the PWM logic and drive circuit is connected to the input pin LS of the switching power stage; and the input pin VIN of the switching power stage is connected to the input voltage VIN.

2. The fixed-frequency PWM controller according to claim 1, characterized in that, The filtering and feedback circuit includes: an inductor L, an output capacitor C, an upper voltage divider resistor R1, and a lower voltage divider resistor R2; one end of the inductor L is the input terminal SW pin of the filtering and feedback circuit, connected to the switching voltage SW generated by the output terminal SW pin of the switching power stage; the other end of the inductor L is connected to one end of the output capacitor C and one end of the upper voltage divider resistor R1; the other end of the upper voltage divider resistor R1 is connected to one end of the lower voltage divider resistor R2; the other end of the lower voltage divider resistor R2 and the other end of the output capacitor C are both grounded; the other end of the inductor L is the output terminal VOUT pin of the filtering and feedback circuit, generating the output voltage VOUT; the other end of the upper voltage divider resistor R1 is the output terminal FB pin of the filtering and feedback circuit, generating the sampling feedback voltage FB.

3. The fixed-frequency PWM controller according to claim 2, characterized in that, The PFM comparator circuit includes: comparator U1; the non-inverting input terminal of comparator U1 is the non-inverting input pin of the PFM comparator circuit and is connected to the sampling feedback voltage FB; the inverting input terminal of comparator U1 is the inverting input pin of the PFM comparator circuit and is connected to the PFM mode reference voltage VREF2; the output terminal of comparator U1 is the output pin of the PFM comparator circuit, generating a light-load high-efficiency mode indication signal PFM; The error amplification and compensation circuit includes: an error operational amplifier U2; the non-inverting input terminal of the error operational amplifier U2 is connected to the PWM mode reference voltage VREF; the inverting input terminal of the error operational amplifier U2 is the input terminal FB pin of the error amplification and compensation circuit, which is connected to the sampling feedback voltage FB; the output terminal of the error operational amplifier U2 is the output terminal VCOMP pin of the error amplification and compensation circuit, which generates the control voltage VCOMP.

4. The fixed-frequency PWM controller according to claim 3, characterized in that, The clock generator includes: an OR gate U14, a switch S3, a capacitor C_CLK, a switching frequency current source I_CLK, and a comparator U3; the first input terminal of the OR gate U14 is the PFM pin of the clock generator, connected to the light-load high-efficiency mode indication signal PFM; the second input terminal of the OR gate U14 is connected to the output terminal of the comparator U3; the output terminal of the OR gate U14 is connected to the control terminal of the switch S3; one end of the switch S3 is connected to one end of the capacitor C_CLK and the non-inverting input terminal of the comparator U3; the other end of the switch S3 is connected to... Connect the other end of the capacitor C_CLK to the reference voltage VREF3; connect the inverting input of the comparator U3 to the reference voltage VREF3; connect the output of the comparator U3 to the CLK pin of the clock generator to generate the clock signal CLK; connect the input of the switching frequency current source I_CLK to the power supply voltage VCC, and connect the output of the switching frequency current source I_CLK to the non-inverting input of the comparator U3; connect the non-inverting input of the comparator U3 to the VSP pin of the clock generator to generate the ramp voltage compensation signal VSP. The slope compensation circuit includes a voltage follower U4 and a voltage follower U5. The non-inverting input of the voltage follower U5 is the non-inverting input pin of the slope compensation circuit and is connected to the control voltage VCOMP. The non-inverting input of the voltage follower U4 is the inverting input pin of the slope compensation circuit and is connected to the slope voltage compensation signal VSP. The inverting input of the voltage follower U4 is grounded. The output of the voltage follower U4 is connected to the inverting input of the voltage follower U5. The output of the voltage follower U5 is the output pin of the slope compensation circuit, generating the control signal VSET.

5. The fixed-frequency PWM controller according to claim 4, characterized in that, The PFM fixed on-time generation circuit includes: switch S4, resistor R_ON, capacitor C_ON, diode D1, voltage follower U6, comparator U7, and RS latch U8. The control terminal of switch S4 is the input terminal CLK pin of the PFM fixed on-time generation circuit, connected to the clock signal CLK. One end of resistor R_ON is the input terminal VIN pin of the PFM fixed on-time generation circuit, connected to the input voltage VIN. The other end of resistor R_ON is connected to one end of switch S4, one end of capacitor C_ON, the positive terminal of diode D1, and the non-inverting input terminal of comparator U7. The negative terminal of diode D1 is connected to the power supply voltage VC. C; The other end of switch S4, the other end of capacitor C_ON, and the inverting input of voltage follower U6 are grounded; the non-inverting input of voltage follower U6 is the input VOUT pin of the PFM fixed on-time generation circuit, connected to the output voltage VOUT; the output of voltage follower U6 is connected to the inverting input of comparator U7; the output of comparator U7 is connected to the R input of RS latch U8; the S input of RS latch U8 is connected to the clock signal CLK; the non-inverting output of RS latch U8 is the output TON_PFM pin of the PFM fixed on-time generation circuit, generating the PFM control signal TON_PFM; The fixed-frequency PWM on-time generation circuit includes: a comparator U9 and an RS latch U10; the non-inverting input of the comparator U9 is the IHS pin of the fixed-frequency PWM on-time generation circuit, connected to the upper transistor sampling current IHS; the inverting input of the comparator U9 is the VSET pin of the fixed-frequency PWM on-time generation circuit, connected to the control signal VSET; the output of the comparator U9 is connected to the R input of the RS latch U10; the S input of the RS latch U10 is the CLK pin of the fixed-frequency PWM on-time generation circuit, connected to the clock signal CLK; the non-inverting output of the RS latch U10 is the TON_PWM pin of the fixed-frequency PWM on-time generation circuit, generating the PWM control signal TON_PWM.

6. The fixed-frequency PWM controller according to claim 5, characterized in that, The OR gate logic circuit includes: OR gate U12; the first input terminal of OR gate U12 is the first input terminal pin of the OR gate logic circuit, connected to the PFM control signal TON_PFM; the second input terminal of OR gate U12 is the second input terminal pin of the OR gate logic circuit, connected to the PWM control signal TON_PWM; the output terminal of OR gate U12 is the output terminal pin of the OR gate logic circuit, generating the control signal TON; The zero-crossing detection circuit includes: a comparator U11; the non-inverting input terminal of the comparator U11 is the input terminal SW pin of the zero-crossing detection circuit, connected to the switching voltage SW; the inverting input terminal of the comparator U11 is connected to the zero-current detection reference voltage VZCD; the output terminal of the comparator U11 is the output terminal ZCD pin of the zero-crossing detection circuit, generating a control signal ZCD.

7. The fixed-frequency PWM controller according to claim 6, characterized in that, The switching power stage includes an upper power transistor S1 and a lower power transistor S2. The gate of the upper power transistor S1 is the input terminal HS pin of the switching power stage, connected to the upper transistor drive signal HS. The drain of the upper power transistor S1 is the input terminal VIN pin of the switching power stage, connected to the input voltage VIN. The input voltage VIN is sampled to obtain the upper transistor sampling current ISH, which is led out as the output terminal IHS pin of the switching power stage. The source of the upper power transistor S1 is the output terminal SW pin of the switching power stage, generating the switching voltage SW. The gate of the lower power transistor S2 is the input terminal LS pin of the switching power stage, connected to the lower transistor drive signal LS. The drain of the lower power transistor S2 is connected to the source of the upper power transistor S1. The source of the lower power transistor S2 is grounded.

8. A fixed-frequency PWM control method based on fixed on-time, characterized in that, Based on the fixed-frequency PWM controller according to claim 7; the fixed-frequency PWM control method includes: The filtering and feedback circuit filters the switching voltage SW through an LC filter to obtain an output voltage VOUT, which is then used to power the external load. The output voltage VOUT is fed back by the voltage sampling of the filtering and feedback circuit to obtain a sampling feedback voltage FB. The PFM comparator circuit compares the sampled feedback voltage FB with the PFM mode reference voltage VREF2 to obtain the light-load high-efficiency mode indication signal PFM. The error amplification and compensation circuit sends the sampled feedback voltage FB into the internal circuit for amplification and compensation processing, and then generates the control voltage VCOMP. The clock generator works in conjunction with the light-load high-efficiency mode indication signal PFM to generate the clock signal CLK and the ramp voltage compensation signal VSP. The ramp compensation circuit generates a control signal VSET based on the control voltage VCOMP and the ramp voltage compensation signal VSP. The PFM fixed on-time generation circuit is triggered by the clock signal CLK at the beginning of each cycle to perform fixed on-time timing, generating a PFM control signal TON_PFM that is phase and frequency matched with the clock signal CLK, determined by the input voltage VIN and the output voltage VOUT, and has a fixed duty cycle. The fixed-frequency PWM conduction time generation circuit is triggered by the clock signal CLK at the beginning of each cycle, generating a PWM control signal TON_PWM with a non-fixed duty cycle that is phase and frequency matched with the clock signal CLK and determined by the control signal VSET and the sampling current IHS of the upper tube. The zero-crossing detection circuit compares the switching voltage SW with a preset negative current threshold to generate the control signal ZCD. The OR gate logic circuit generates a control signal TON based on the PFM control signal TON_PFM and the PWM control signal TON_PWM, with the minimum time to clamp the upper power transistor S1 to be turned on being TON_PFM. The PWM logic and driving circuit generate the upper transistor driving signal HS and the lower transistor driving signal LS, which are inversely phase with the upper transistor driving signal HS and have a certain dead time, according to the control signal ZCD and the control signal TON. The switching power stage controls the conduction of the upper power transistor S1 and the lower power transistor S2 according to the upper transistor drive signal HS and the lower transistor drive signal LS; the input voltage VIN is processed by the upper and lower power transistors of the switching power stage to obtain the switching voltage SW, and when the upper power transistor S1 is turned on, the current of the upper power transistor S1 is sampled to obtain the upper transistor sampling current IHS.

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