A multi-mode power amplifier circuit for improving efficiency and power of a communications band

Abstract

This invention belongs to the field of microwave integrated circuit technology, specifically relating to a multimode power amplifier circuit for improving the efficiency and power of communication frequency bands. It includes a pre-amplifier circuit, a post-amplifier circuit, and a DC blocking capacitor C for connecting the pre-amplifier circuit and the post-amplifier circuit. B2 The subsequent amplifier circuit includes a performance enhancement circuit. The switching transistor Q in the performance enhancement circuit is adjusted accordingly. s7 The control voltage for mode switching enables the switching of operating modes from ultra-wideband to communication bands, and improves efficiency and power after the switching. This is achieved through the series inductor L in the performance enhancement circuit. ee and capacitor C ee To suppress harmonics in the communication frequency band and improve the efficiency and power of the power amplifier, the adjustable switching transistor Q is used. s7 The control voltage for mode switching enables the switching of operating modes from ultra-wideband to communication bands, and improves efficiency and power after switching. This method can be extended to microwave multimode amplifiers in other frequency bands.

Description

Technical Field

[0001] This invention belongs to the field of microwave integrated circuit technology, specifically relating to a multimode power amplifier circuit that improves the efficiency and power of communication frequency bands. Background Technology

[0002] With the development of integrated electronic technology, power amplifiers must not only meet the requirements of electronic warfare systems but also the performance requirements of communication bands. Low power consumption is beneficial for the continuous operation of communication systems, while higher power can cover a wider range. As a core component of the radio frequency transmission front-end, the power consumption of the power amplifier (PA) directly determines the power consumption of the entire system. In systems with high requirements for heat dissipation and battery life, improving the efficiency of the power amplifier becomes a primary goal. This necessitates that power amplifiers with ultra-wideband and communication band operating modes, used in integrated electronics, further improve their efficiency and power after switching communication bands. Current multimode power amplifier designs only switch operating modes between a few narrow frequency bands and do not involve improving the efficiency and power of the switching. Summary of the Invention

[0003] The purpose of this invention is to provide a multi-mode power amplifier circuit that improves the efficiency and power of communication frequency bands, thereby enhancing the efficiency and power of the multi-mode power amplifier after switching communication frequency bands.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A multimode power amplifier circuit for improving the efficiency and power of communication bands includes: a preamplifier circuit, a power amplifier circuit, and a DC blocking capacitor C for connecting the preamplifier circuit and the power amplifier circuit. B2 ;

[0006] The preamplifier circuit includes a DC blocking capacitor C connected in sequence. B1 , Stabilizing resistor R in The system includes an input matching inductor L0, an input matching inductor L1, a transistor Q0, and an output matching inductor L2; the DC blocking capacitor C is also present. B1 The input terminal of the preamplifier circuit is connected to an externally input RF signal, and the output matching inductor L2 is connected to the output terminal of the preamplifier circuit via a DC blocking capacitor C. B2 The input terminal;

[0007] Stabilizing resistor R in Each of the three reconfigurable stubs—between the input matching inductor L0, between the input matching inductor L0 and the input matching inductor L1, and between the input matching inductor L1 and the gate of transistor Q0—is connected to a reconfigurable stub. These three reconfigurable stubs have identical structures, each consisting of a capacitor C. pn Inductor L pnDC blocking capacitor C sn and switching transistor Q sn Composition, capacitor C pn and inductor L pn The parallel connections form a bandpass network, with one end of the bandpass network connected to a DC blocking capacitor C. sn With switching transistor Q sn The drains of the transistors are connected, and the switching transistor Q is connected. sn The source is grounded, and the switching transistor Q in the three reconfigurable stubs sn The gates are connected and all are connected to the DC control power supply V. gc The other end of the bandpass network connects to its respective access point.

[0008] The common contact between the input matching inductor L1 and the gate of transistor Q0 is further provided with a gate power supply circuit; the gate power supply circuit includes the input matching inductor L1. g Isolation resistor R G1 and the isolation resistor C c1 Input matching inductor L g One end is connected between inductor L1 and the gate of transistor Q0, and the other end is connected to the isolation resistor R. G1 One end, the isolation resistor R G1 The other end is connected to a DC power supply V. gs1 Coupling capacitor C c1 One end, coupling capacitor C c1 The other end is grounded; the gate and source of the transistor Q0 are grounded, and the drain is connected to the input terminal of the output matching inductor L2; the output matching inductor L2 and the DC blocking capacitor C B2 The common contact point between them is connected to a drain power supply circuit, which consists of two power supplies connected in parallel, one of which is an inductor L. D1，1 Parallel decoupling capacitor C c2,1 Upon arrival, C c2,1 The end is connected to a DC power supply V. ds1，1 The other path is an inductor L D1，2 Parallel decoupling capacitor C c2,2 Upon arrival, C c2,2 The end is connected to a DC power supply V. ds1，2 ;

[0009] The subsequent amplifier circuit includes gate matching microstrip lines MLIN1, MLIN2, and MLIN3, and a gate matching inductor L. g Isolation resistor R G2 Decoupling capacitor C c3 Transistors Q1, Q2, Q3; drain matching inductor L d Drain matching microstrip lines MLIN4 and MLIN5, performance provisioning circuit, power supply circuit, DC blocking capacitor C B3 ;

[0010] One end of the gate-matching microstrip line MLIN1 serves as the input to the subsequent amplifier circuit, and the other end is connected in series with inductor L. g Gate matching microstrip lines MLIN2 and MLIN3, and interlocking resistor R G2 Decoupling capacitor C c3 Decoupling capacitor C c3 The end is grounded, and the isolation resistor R G2 and decoupling capacitor C c3 Common contact connection supply voltage V gs2 ;

[0011] Gate matching microstrip line MLIN1 and inductor L g common contact, inductance L g The common junction of gate-matching microstrip line MLIN2 and the common junction of gate-matching microstrip lines MLIN2 and MLIN3 are all connected to an RC network and a reconfigurable stub. All reconfigurable stubs in the subsequent amplifier circuit have the same reconfigurable direct structure as the preceding amplifier circuit, and the gates of the switching transistors Qsn in the three reconfigurable stubs of the subsequent amplifier circuit are also connected to a DC control power supply V. gc ;

[0012] An RC network consists of parallel resistors R n and C n Composition; the gate matching microstrip line MLIN1 and inductor L are combined. g The RC network with common contact is defined as the first RC network, and the inductor L g The RC network connected to the common junction of gate matching microstrip line MLIN2 is defined as the second RC network, and the RC network connected to the common junction of gate matching microstrip lines MLIN2 and MLIN3 is defined as the third RC network. One end of each of the three RC networks is connected to its corresponding junction. The other end of the first RC network is connected to the gate of transistor Q1, the other end of the second RC network is connected to the gate of transistor Q2, and the other end of the third RC network is connected to the gate of transistor Q3. The source of transistor Q1 is grounded, and the drain is connected to L. d At one end, the source of Q2 is grounded, and the drain is connected to L. d The source of Q3 is grounded, and the drain is connected to the common junction of MLIN4 and MLIN5; the drain matching inductor L d The other end is connected sequentially to drain matching microstrip line MLIN4 and drain matching microstrip line MLIN5;

[0013] The performance enhancement circuit consists of a microstrip line MLIN6 and an inductor L. ee Capacitor C ee and the switching transistor Q s7Composition: One end of microstrip line MLIN6 is connected to the drain matching microstrip line MLIN5, and the other end is connected to the power supply circuit and the DC blocking capacitor C. B3 One end; inductor L ee One end is connected to the common junction of microstrip line MLIN6 and drain-matching microstrip line MLIN5, and the other end is connected to capacitor C. ee Connecting the switching transistor Q s7 The drain of the switching transistor Q s7 The gate is connected to a DC control power supply V. gc The source is grounded;

[0014] The power supply circuit for the rear electrode consists of a series capacitor C c4 and inductor L D2 Composition, capacitor C c4 One end is connected to the common junction of the microstrip line MLIN6, and the other end is connected via inductor L. D2 Connect DC power supply V ds2 ;

[0015] DC blocking capacitor C B3 The other end is the output terminal of the subsequent amplifier circuit, used to output the amplified radio frequency signal.

[0016] It should be noted that capacitor C pn Inductor L pn DC blocking capacitor C sn Switching transistor Q sn Resistance R n and capacitor C n The range of values ​​for n in the equation is: n = 1, 2, 3.

[0017] This invention provides a multimode power amplifier circuit for improving communication frequency band efficiency by enhancing the performance of the series inductor L in the circuit. ee and capacitor C ee To suppress harmonics in the communication frequency band and improve the efficiency and power of the power amplifier, the adjustable switching transistor Q is used. s7 The control voltage for mode switching enables the switching of operating modes from ultra-wideband to communication bands, and improves efficiency and power after switching; the switching transistor Q... s7 The parasitic capacitance is absorbed into the artificial transmission line of the drain in the subsequent amplifier circuit, allowing the power amplifier circuit to operate normally when switching to ultra-wideband mode, without being affected by the switching transistor Q. s7 The parasitic capacitance affects the high-frequency performance during ultra-wideband operation. This is addressed by suppressing the second harmonic and using an artificial transmission line absorption switching transistor Q. s7This invention utilizes parasitic capacitance to achieve dual-mode operation of a power amplifier in both ultra-wideband and communication bands. It improves efficiency and power when switching from ultra-wideband mode to communication band mode without affecting the performance of the power amplifier in ultra-wideband mode. This method can be extended to microwave multimode amplifiers in other frequency bands. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of Embodiment 1 of the present invention;

[0019] Figure 2 The figure shows the simulation results of Embodiment 1 of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in conjunction with the following specific embodiments and with reference to the accompanying drawings.

[0021] Example 1:

[0022] like Figure 1 As shown, this embodiment provides a power amplifier circuit that operates in both ultra-wideband and communication band dual-mode, including a preamplifier circuit, a power amplifier circuit, and a DC blocking capacitor C for connecting the preamplifier circuit and the power amplifier circuit. B2 The specific structures of the preamplifier and power amplifier circuits are set as described above and will not be repeated here. In the entire circuit, the transistor input terminals are matched using inductors, resistors, and microstrip lines, while the output terminals are matched using microstrip lines. After passing through a DC blocking capacitor, the transistors are connected to the multi-stage traveling-wave amplifier circuit via microstrip lines. Switching between ultra-wideband and communication bands is achieved by changing the control voltage of the switching transistors in the reconfigurable stub and the control voltage of the drain power supply circuit of the preamplifier circuit. A performance enhancement circuit is added to the power amplifier circuit to improve efficiency and power after switching from ultra-wideband to communication bands. Specifically:

[0023] When the control voltage V gc = -40V and the power supply circuit for the drain of the preceding stage is a DC source V ds1,1 When the power supply branch is in operation, the power amplifier operates in ultra-wideband mode, and the control voltage V gc =0V and the drain power supply circuit of the preceding stage is switched to DC source V ds1,2 When the power supply branch switches to the communication band operating mode, the inductor L in the performance enhancement circuit will... ee and capacitor C eeThe LC stub operation, by short-circuiting the second harmonic of the fundamental frequency, shapes the output waveform, thereby improving output power and power-added efficiency. This stub needs to be turned off in ultra-wideband operation mode. Since there is parasitic capacitance in the off state of the switching transistor, the addition of the microstrip line MLIN6 connects the microstrip line and the amplifying transistor to form an artificial transmission line that absorbs the parasitic capacitance of the switching transistor. This prevents the reduction of the LC stub resonant frequency caused by parasitic capacitance, which would otherwise lead to a decrease in ultra-wideband high-frequency performance. This achieves normal operation of ultra-wideband and improved efficiency and power when switching to the communication frequency band.

[0024] Figure 2 This is a simulation result diagram of Embodiment 1 of the present invention. Figure 2 As shown, in ultra-wideband operating mode, the power amplifier circuit operates at a frequency of 0.03–7 GHz, with an output power greater than 40.5 dBm, a power-added efficiency greater than 46%, and a gain greater than 17 dB. At 2.8 GHz, the output power is 41.5 dBm, and the power-added efficiency is 52.7%. When switching to communication band operating mode, the frequency is 2.4–3.3 GHz, with an output power greater than 42.4 dBm at 2.8 GHz and a power-added efficiency of 58.3%. Compared to ultra-wideband operation, the output power is increased by 0.9 dB, and the power-added efficiency is increased by 5.6%.

[0025] In summary, this invention proposes a novel multimode power amplifier circuit structure to improve the efficiency and power of communication bands. By short-circuiting the second harmonic of the communication band through LC stubs and by constructing an artificial transmission line to absorb the parasitic capacitance of the switching transistor, the performance of ultra-wideband and dual-communication band multimode power amplifiers switching to communication band mode is improved.

Claims

1. A multimode power amplifier circuit for improving communication frequency band efficiency and power, comprising: The preamplifier circuit, the power amplifier circuit, and the DC blocking capacitor C used to connect the preamplifier circuit and the power amplifier circuit. B2 Its features are: The preamplifier circuit includes a DC blocking capacitor C connected in sequence. B1 , Stabilizing resistor R in The system includes an input matching inductor L0, an input matching inductor L1, a transistor Q0, and an output matching inductor L2; the DC blocking capacitor C is also present. B1 The input terminal of the preamplifier circuit is connected to an externally input RF signal, and the output matching inductor L2 is connected to the output terminal of the preamplifier circuit via a DC blocking capacitor C. B2 The input terminal; Stabilizing resistor R in Each of the three reconfigurable stubs is connected between the input matching inductor L0, between the input matching inductor L0 and the input matching inductor L1, and between the input matching inductor L1 and the gate of transistor Q0; the three reconfigurable stubs have the same structure and are all connected by a capacitor C. pn Inductor L pn DC blocking capacitor C sn and switching transistor Q sn Composition, capacitor C pn and inductor L pn The parallel connections form a bandpass network, with one end of the bandpass network connected to a DC blocking capacitor C. sn With switching transistor Q sn The drains of the transistors are connected, and the switching transistor Q is connected. sn The source is grounded, and the switching transistor Q is one of the three reconfigurable stubs. sn The gates of each are independently connected to the DC control power supply V. gc The other end of the bandpass network connects to its respective access point. The common contact between the input matching inductor L1 and the gate of transistor Q0 is also connected to a gate power supply circuit; the gate power supply circuit includes the input matching inductor L1. g Bias resistor R G1 and decoupling capacitor C c1 Input matching inductor L g One end is connected between inductor L1 and the gate of transistor Q0, and the other end is connected to bias resistor R. G1 One end, bias resistor R G1 The other end is connected to a DC power supply V. gs1 and decoupling capacitor C c1 One end, decoupling capacitor C c1 The other end is grounded; the source of the transistor Q0 is grounded, and its drain is connected to the input terminal of the output matching inductor L2; the output matching inductor L2 and the DC blocking capacitor C B2 The common contact point between them is connected to a drain power supply circuit, which consists of two power supplies connected in parallel, one of which is an inductor L. D1,1 and decoupling capacitor C c2,1 Composition, inductor L D1,1 One end is connected to the output matching inductor L2 and the DC blocking capacitor C. B2 The common contact point between them, and the decoupling capacitor C connected to the other end. c2,1 One end and DC power supply V ds1,1 Decoupling capacitor C c2,1 The other end is grounded; the other route is through inductor L. D1,2 and decoupling capacitor C c2,2 Composition, inductor L D1,2 One end is connected to the output matching inductor L2 and the DC blocking capacitor C. B2 The common contact point between them is connected to a decoupling capacitor C at the other end. c2,2 One end and DC power supply V ds1,2 Decoupling capacitor C c2,2 The other end is grounded; The subsequent amplifier circuit includes gate matching microstrip lines MLIN1, MLIN2, and MLIN3, and a gate matching inductor L. g Bias resistor R G2 Decoupling capacitor C c3 Transistors Q1, Q2, Q3; drain matching inductor L d Drain matching microstrip lines MLIN4 and MLIN5, performance enhancement circuit, power supply circuit for subsequent stages, DC blocking capacitor C B3 ; One end of the gate-matching microstrip line MLIN1 serves as the input to the subsequent amplifier circuit, and the other end is connected in series with inductor L. g Gate matching microstrip lines MLIN2 and MLIN3, bias resistor R G2 Decoupling capacitor C c3 One end, decoupling capacitor C c3 The other end is grounded, and the bias resistor R G2 and decoupling capacitor C c3 Common contact connection to power supply voltage V gs2 ; Gate matching microstrip line MLIN1 and inductor L g common contact, inductance L g The common junction of gate-matching microstrip line MLIN2 and the common junction of gate-matching microstrip lines MLIN2 and MLIN3 are all connected to an RC network and a reconfigurable stub. All reconfigurable stubs in the subsequent amplifier circuit have the same reconfigurable direct structure as the preceding amplifier circuit, and the gate connection of each reconfigurable stub switching transistor Qsn in the subsequent amplifier circuit is independently connected to the DC control power supply V. gc ; An RC network consists of parallel resistors R n and C n Composition; the gate matching microstrip line MLIN1 and inductor L are combined. g The RC network with common contact is defined as the first RC network, and the inductor L g The RC network connected to the common junction of gate matching microstrip line MLIN2 is defined as the second RC network, and the RC network connected to the common junction of gate matching microstrip lines MLIN2 and MLIN3 is defined as the third RC network. One end of each of the three RC networks is connected to its corresponding junction. The other end of the first RC network is connected to the gate of transistor Q1, the other end of the second RC network is connected to the gate of transistor Q2, and the other end of the third RC network is connected to the gate of transistor Q3. The source of transistor Q1 is grounded, and the drain is connected to the drain matching inductor L. d At one end, the source of Q2 is grounded, and the drain is connected to L. d The source of Q3 is grounded, and the drain is connected to the common connection point of MLIN4 and MLIN5; the drain matching inductor L d The other end is connected sequentially to drain matching microstrip line MLIN4 and drain matching microstrip line MLIN5; The performance enhancement circuit consists of a microstrip line MLIN6 and an inductor L ee Capacitor C ee and the switching transistor Q s7 Composition: One end of microstrip line MLIN6 is connected to the drain matching microstrip line MLIN5, and the other end is connected to the subsequent power supply circuit and the DC blocking capacitor C. B3 One end; inductor L ee One end is connected to the common junction of microstrip line MLIN6 and drain-matching microstrip line MLIN5, and the other end is connected to capacitor C. ee Connecting the switching transistor Q s7 The drain of the switching transistor Q s7 The gate is connected to a DC control power supply V. gc The source is grounded; The power supply circuit for the later stage consists of capacitor C c4 and inductor L D2 Composition, capacitor C c4 One end is connected to the microstrip line MLIN6 and the DC blocking capacitor C. B3 One end is the common connection point, and the other end is grounded; inductor L D2 One end is connected to capacitor C c4 One end, the other end is connected to inductor L D2 Connect DC power supply V ds2 ; DC blocking capacitor C B3 The other end is the output terminal of the subsequent amplifier circuit, used to output the amplified radio frequency signal.

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