Filter Structure and Formulation Method

Abstract

A filter structure and a method for forming the same are disclosed. The method includes: providing a substrate, the substrate including a working region, an interconnect region surrounding the working region, and a sealing region surrounding the interconnect region, wherein a device structure is formed on the substrate of the working region; forming a buffer layer on top of the substrate of the interconnect region and the sealing region; forming a first interconnect layer on top of the buffer layer of the interconnect region, on a sidewall near the working region, and on the buffer layer of the sealing region, the first interconnect layer extending into the working region and electrically connected to the device structure, the first interconnect layer located in the sealing region serving as a sealing layer; forming an encapsulation layer on top of the first interconnect layer and above the substrate of the working region, the encapsulation layer, the sealing layer, and the substrate forming a cavity; forming an opening in the encapsulation layer in the interconnect region to expose the top of the first interconnect layer; and forming an interconnect structure in the opening. This method reduces delamination or substrate cracking problems caused by thermal stress generated by the first interconnect layer and the encapsulation layer, improving the reliability of the filter structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a filter structure and a method for forming the same. Background Technology

[0002] With the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink, and the requirements for integrated circuit packaging technology are also constantly increasing. Existing packaging technologies include ball grid array (BGA), chip scale package (CSP), wafer level package (WLP), 3D packaging, and system-in-package (SiP).

[0003] System-on-a-Chip (SoC) packaging combines multiple active and passive components, microelectromechanical systems (MEMS), optical components, and other elements with different functions into a single unit, forming a system or subsystem that provides multiple functions, allowing for the integration of heterogeneous ICs. Compared to System-on-Chip (SoC), SoC packaging offers relatively simpler integration, shorter design and time-to-market cycles, lower costs, and the ability to implement more complex systems.

[0004] To meet the goals of lower cost, higher reliability, faster speed and higher density in integrated circuit packaging, advanced packaging methods mainly adopt wafer-level package system in package (WLPSiP). Compared with traditional system packaging, wafer-level package system in package completes the packaging integration process on the device wafer, which has advantages such as significantly reducing the area of ​​the package structure, reducing manufacturing costs, optimizing electrical performance, and batch manufacturing, and can significantly reduce workload and equipment requirements. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a filter structure and its formation method, which is beneficial to improving the reliability of the filter.

[0006] To address the aforementioned problems, the present invention provides a filter structure comprising: a substrate including a working region and an interconnect region surrounding the working region, and a sealing region surrounding the interconnect region; a device structure located on the substrate in the working region; a buffer layer located on top of the substrate in the interconnect region and on top of the substrate in the sealing region; a first interconnect layer located on top of the buffer layer and on a sidewall near the working region, the first interconnect layer further extending into the working region and electrically connected to the device structure; a sealing layer located on top of the buffer layer in the sealing region; an encapsulation layer located on top of the first interconnect layer and above the top of the substrate in the working region, wherein in the working region, the encapsulation layer, the sidewall of the buffer layer, and the substrate form a cavity for accommodating the device structure; and an interconnect structure located in the encapsulation layer in the interconnect region, the bottom of the interconnect structure being electrically connected to the top of the first interconnect layer.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a filter, comprising: providing a substrate, the substrate including a working region and an interconnect region surrounding the working region, and a sealing region surrounding the interconnect region, wherein a device structure is formed on the substrate of the working region; forming a buffer layer on top of the substrate of the interconnect region and the sealing region; forming a first interconnect layer on the top of the buffer layer of the interconnect region, a sidewall near the working region, and the buffer layer of the sealing region, the first interconnect layer further extending into the working region and electrically connected to the device structure, wherein the first interconnect layer located in the sealing region serves as a sealing layer; forming an encapsulation layer on top of the first interconnect layer and above the top of the substrate of the working region, the encapsulation layer, the sealing layer, and the substrate forming a cavity, the cavity being used to accommodate the device structure; forming an opening in the encapsulation layer in the interconnect region to expose the top of the first interconnect layer; forming an interconnect structure in the opening, the bottom of the interconnect structure being electrically connected to the top of the first interconnect layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a method for forming a filter. Before forming a first interconnect layer on top of a buffer layer and on the sidewall near the working area, a buffer layer is formed on top of the substrate of the interconnect region, such that the buffer layer is located between the substrate and the first interconnect layer. After the device structure temperature changes, the buffer layer helps to offset or weaken the thermal stress generated between the first interconnect layer and the packaging layer, thereby buffering the thermal stress generated between the first interconnect layer and the packaging layer, reducing the probability of delamination problems or substrate cracking problems caused by the thermal stress generated between the first interconnect layer and the packaging layer, and thus improving the reliability of the filter structure. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a filter structure;

[0011] Figure 2 This is a schematic diagram of one embodiment of the filter structure of the present invention;

[0012] Figure 3 This is a schematic diagram of another embodiment of the filter structure of the present invention;

[0013] Figures 4 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the filter formation method of the present invention. Detailed Implementation

[0014] The reliability of current filters needs improvement. This paper analyzes the reasons for this need, using a schematic diagram of a filter structure as an example.

[0015] Figure 1 This is a schematic diagram of a filter structure.

[0016] refer to Figure 1 The filter structure includes: a substrate 10; the substrate 10 includes a working region 10A, an interconnect region 10B surrounding the working region 10A, and a sealing region 10C surrounding the interconnect region 10B; a device structure 12 located on the substrate 10 in the working region 10A; an interconnect layer 13 located on top of the substrate 10 in the interconnect region 10B; a sealing layer 16 located on the substrate 10 in the sealing region 10C; an encapsulation layer 11 located on top of the interconnect layer 13 and the sealing layer 16, above the top of the substrate 10 in the working region 10A, wherein the encapsulation layer 11, the sidewalls of the interconnect layer 13, and the substrate 10 form a cavity 19 in the working region 10A, the cavity 19 being used to accommodate the device structure 12; and a conductive pillar 17 located in the encapsulation layer 11 in the interconnect region 10B, the bottom of the conductive pillar 17 being electrically connected to the top of the interconnect layer 13.

[0017] Research has revealed that due to the significant difference between the coefficient of thermal expansion (CTE) of the encapsulation layer 11 and the substrate 10, the encapsulation layer 11 exhibits greater shrinkage during temperature variations in the filter structure, while the interconnect layer 13 demonstrates better ductility. This leads to substantial thermal stress between the interconnect layer 13, the encapsulation layer 11, and the sealing layer 16. Under such significant thermal stress, delamination between the interconnect layer 13 and the substrate 10, or even cracking of the substrate 10, can easily occur, thereby affecting the reliability of the filter structure.

[0018] To address the technical problem, embodiments of the present invention provide a method for forming a filter, comprising: providing a substrate, the substrate including a working region and an interconnect region surrounding the working region, wherein a device structure is formed on the substrate of the working region; forming a buffer layer on top of the substrate of the interconnect region; forming a first interconnect layer on top of the buffer layer and on a sidewall near the working region, the first interconnect layer further extending into the working region and electrically connected to the device structure; forming an encapsulation layer on top of the first interconnect layer and above the top of the substrate of the working region, wherein in the working region, the encapsulation layer, the sidewall of the buffer layer, and the substrate form a cavity for accommodating the device structure; forming an opening in the encapsulation layer in the interconnect region, exposing the top of the first interconnect layer; forming an interconnect structure in the opening, the bottom of the interconnect structure being electrically connected to the top of the first interconnect layer.

[0019] In this embodiment of the invention, a buffer layer is formed on top of the substrate of the interconnect region before the first interconnect layer is formed on the top of the buffer layer and the sidewall near the working area. The buffer layer is located between the substrate and the first interconnect layer. After the device structure temperature changes, the buffer layer helps to offset or weaken the thermal stress generated between the first interconnect layer and the packaging layer, thereby buffering the thermal stress generated between the first interconnect layer and the packaging layer. This reduces the probability of delamination problems or substrate cracking problems caused by the thermal stress generated between the first interconnect layer and the packaging layer, thereby improving the reliability of the filter structure.

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] Figure 2 This is a schematic diagram of one embodiment of the filter structure of the present invention.

[0022] The filter structure includes: a substrate 200, the substrate 200 including a working region 200A and an interconnect region 200B surrounding the working region 200A, and a sealing region 200C surrounding the interconnect region 200B; a device structure 202 located on the substrate 200 of the working region 200A; a buffer layer 201 located on top of the substrate 200 of the interconnect region 200B and on top of the substrate 200 of the sealing region 200C; and a first interconnect layer 203 located on top of the buffer layer 201 and on a sidewall near the working region 200A, the first interconnect layer 203 further extending into the working region 200A. It is electrically connected to the device structure 202; a sealing layer is located on top of the buffer layer 201 in the sealing region 200C; an encapsulation layer 210 is located on top of the first interconnect layer 203 and above the top of the substrate 200 in the working region 200A. In the working region 200A, the encapsulation layer 210, the sidewall of the buffer layer 201, and the substrate 200 form a cavity 209, which is used to accommodate the device structure 202; an interconnect structure 218 is located in the encapsulation layer 201 in the interconnect region 200B, and the bottom of the interconnect structure 218 is electrically connected to the top of the first interconnect layer 203.

[0023] This invention provides a filter structure in which a buffer layer 201 is located on top of the substrate 200 of the interconnect region 200B. The buffer layer 201 is located between the substrate 200 and the first interconnect layer 203. After the device structure undergoes temperature changes, the buffer layer 201 helps to offset or weaken the thermal stress generated between the first interconnect layer 203 and the encapsulation layer 210, thereby buffering the thermal stress generated between the first interconnect layer 203 and the encapsulation layer 210. This reduces the probability of delamination or substrate cracking caused by the thermal stress generated between the first interconnect layer 203 and the encapsulation layer 210, thereby improving the reliability of the filter structure.

[0024] The substrate 200 is used to provide a process platform for the filter.

[0025] In this embodiment, the substrate 200 is a wafer-level substrate 200.

[0026] By employing a wafer-level substrate 200, a wafer-level fabrication process can be realized in the filter structure formation method, which can reduce process costs and enable mass production, thereby improving the production efficiency of filter manufacturing.

[0027] In this embodiment, the filter structure is a filter. Specifically, the filter structure includes one or more of the following: surface acoustic wave filter, bulk acoustic wave filter, and thin-film cavity resonant filter.

[0028] The substrate 200 includes a working region 200A, which is the area where the device structure 202 operates. Specifically, the working region 200A is the working area of ​​the filter used to implement the filtering function, and a cavity is subsequently formed in the working region 200A.

[0029] In this embodiment, the substrate 200 is a wafer-level substrate 200. Therefore, the substrate 200 includes multiple device unit regions (not shown), and each device unit region includes a working area 200A and an interconnect area 200B.

[0030] In this embodiment, the formed filter is described as a surface acoustic wave (SAW) filter.

[0031] Accordingly, the substrate 200 is a piezoelectric substrate, enabling subsequent filters to utilize the piezoelectric effect for filtering. In this embodiment, the substrate 200 is made of one or more piezoelectric ceramic materials, such as lithium niobate (LiNbO3), lithium tantalate (LiTaO3), quartz, ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lithium barium lead niobate), and PT (lead titanate). It should be noted that rare earth elements can also be doped into the piezoelectric substrate, such as any one or a combination of scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) to improve the piezoelectric coefficient.

[0032] In this embodiment, the surface acoustic wave (SAW) filter is a combination of a PZT composite film structure and interdigital transducers (IDTs).

[0033] The device structure 202 is used to realize the mutual conversion between electrical signals and acoustic signals, so that the filter can perform filtering processing on the signals.

[0034] Specifically, the device structure 202 is an acoustic transducer with a piezoelectric structure. In this embodiment, the formed filter is a SAW filter; therefore, the device structure 202 is a metal interdigital transducer (IDT). The material of the interdigital electrode includes one or more of Mo, Al, Pt, W, Au, Al, Ni, and Ag. In this embodiment, the interdigital electrode is an interdigital aluminum electrode. Specifically, the device structure 202 is formed by depositing a metal film on the substrate 200 and patterning the metal film using photolithography and etching processes.

[0035] In this embodiment, the substrate 200 further includes an interconnect region 200B surrounding the working region 200A, and a first interconnect layer 203 is formed on the interconnect region 200B. The first interconnect layer 203 is electrically connected to the device structure 202.

[0036] Specifically, the first interconnect layer 203 is used as the input / output (I / O) terminal of the device structure 202, and the first interconnect layer 203 is used to electrically connect the input interdigital transducer and the output interdigital transducer respectively.

[0037] It should be noted that, as Figure 3 As shown, in other embodiments, the method for forming the filter structure can also be used to form bulk acoustic wave filters (BAW-SMR) and thin-film cavity resonators (FBAR). Accordingly, the device structure includes a piezoelectric stack structure.

[0038] In this embodiment, the substrate 200 further includes a sealing region 200C surrounding the interconnect region 200B.

[0039] Specifically, a sealing layer is formed on the sealing area 200C. The sealing layer is used to form the cavity 209. At the same time, the sealing layer protects and seals the first interconnect layer 203 in the interconnect area 200B, reducing the probability of the first interconnect layer 203 being corroded.

[0040] Accordingly, when the substrate 200 includes multiple device unit regions, each device unit region also includes a sealing region 200C.

[0041] The buffer layer 201 helps to offset or weaken the thermal stress generated between the subsequently formed first interconnect layer and the encapsulation layer, thereby buffering the thermal stress generated between the first interconnect layer and the encapsulation layer.

[0042] The buffer layer 201 also covers the top of the substrate 200 of the sealing area 200C.

[0043] In the process of forming the filter structure, a sealing layer is formed on top of the buffer layer 201 in the sealing region 200C. In order to reduce the probability of delamination or substrate 200 cracking caused by thermal stress generated between the sealing layer and the encapsulation layer 210, the buffer layer 201 also covers the top of the substrate 200 in the sealing region 200C.

[0044] In this embodiment, the material of the buffer layer 201 includes a polymeric organic material.

[0045] The polymeric organic material has a low Young's modulus, which is a physical quantity that measures a material's resistance to deformation. In other words, when subjected to external stress, the polymeric organic material deforms while also offsetting or weakening the external stress, thus enabling the buffer layer 201 to play a buffering role.

[0046] In other embodiments, the coefficient of thermal expansion of the material used for the buffer layer is between that of the material used for the subsequently formed encapsulation layer and the material used for the first interconnect layer.

[0047] Specifically, when the coefficient of thermal expansion of the buffer layer is between that of the encapsulation layer and the first interconnect layer, the buffer layer can offset or weaken the thermal stress generated by the encapsulation layer and the first interconnect layer, thereby enabling the buffer layer to play a buffering role.

[0048] The first interconnect layer 203 is electrically connected to the device structure 202. The first interconnect layer 203 serves as an input / output (I / O) terminal of the device structure 202. The first interconnect layer 203 is used to electrically connect the device structure 202 to an external circuit structure.

[0049] Specifically, the first interconnect layer 203 is used to electrically connect the input interdigital transducer and the output interdigital transducer, respectively.

[0050] It should be noted that the working area 200A also includes a conductive area that is electrically connected to the first interconnect layer 203. The conductive area exposed by the buffer layer 201 is covered by the first interconnect layer 203, thereby achieving an electrical connection between the first interconnect layer 203 and the device structure 202.

[0051] The material of the first interconnect layer 203 includes one or more of Ti, Cu, Al, Au, and Ni. Specifically, Ti, Cu, Al, Au, and Ni are all conductive materials, enabling the device structure in the working area 200A to be electrically connected to the external power distribution structure through the first interconnect layer 203. As an example, the material of the first interconnect layer 203 is Cu.

[0052] It should be noted that the thickness of the first interconnect layer 203 should not be too large or too small. If the thickness of the first interconnect layer 203 is too large, it increases the difficulty of removing the interconnect material layer at the junction of the interconnect region 200B and the sealing region 200C in the filter structure formation process, and also causes waste of process materials. If the thickness of the first interconnect layer 203 is too small, it is easy to cause the effective height of the cavity in the working region 200A to be too small. Correspondingly, it increases the probability of the encapsulation layer 210 contacting the device structure 202 after being deformed by external force, thereby reducing the reliability of the filter structure. Therefore, in this embodiment, the thickness of the first interconnect layer 203 is 2 micrometers to 30 micrometers.

[0053] In this embodiment, the sealing layer 206 is located on top of the buffer layer 201 of the sealing area 200C.

[0054] It should be noted that in the filter structure formation process, while forming the first interconnect layer 203, a sealing layer 206 is also formed on the buffer layer 201 of the sealing region 200C. This reduces the step of removing the first interconnect layer 203 in the sealing region 200C to form the sealing layer 206, reduces the impact of multiple etching processes on the top surface of the buffer layer 201, and reduces the process cost.

[0055] In this embodiment, the material of the sealing layer 206 is the same as that of the first interconnect layer 203. Since the first interconnect layer 203 is made of metal, the sealing layer 206 is also made of metal, as metal materials provide better sealing.

[0056] In this embodiment, the filter structure further includes an insulating layer 208 located on the top and sidewalls of the first interconnect layer 203, and the insulating layer also covers the top and sidewalls of the device structure 202 of the working area 200A.

[0057] Specifically, the insulating layer 208 located on top of the first interconnect layer 203, on the one hand, increases the adhesion strength between the encapsulation layer 210 and the first interconnect layer 203, reducing the probability of gaps forming between the encapsulation layer and the first interconnect layer 203; on the other hand, in the filter structure formation process, during the process of forming an opening in the encapsulation layer 210 that exposes the top of the first interconnect layer 203, the top of the insulating layer 208 can define the stop position of the patterning process when patterning the encapsulation layer 210, thereby protecting the first interconnect layer 203 and reducing the probability of damage to the first interconnect layer 203.

[0058] Meanwhile, the insulating layer 208 located on the top and sidewalls of the device structure 202 in the working area 200A reduces the probability of the device structure 202 in the working area 200A coming into contact with the outside air. Correspondingly, it reduces the probability of the device structure 202 in the working area 200A being oxidized and corroded, thereby improving the reliability of the filter structure.

[0059] In this embodiment, the insulating layer is also formed on the top and sidewalls of the device structure 202 in the working area 200A.

[0060] In this embodiment, the insulating layer 208 is made of one or more of SiO2, SiN, and Al2O3. The use of SiO2, SiN, and Al2O3 as dielectric materials allows for a satisfactory etching selectivity between the insulating layer 208 and the encapsulation layer 210 during the process of forming the opening that exposes the top of the first interconnect layer 203 in the encapsulation layer 210, thus reducing the difficulty of forming the opening.

[0061] It should be noted that the thickness of the insulating layer 208 should not be too large or too small. If the thickness of the insulating layer 208 is too large, the process of removing the insulating layer 208 during the formation of an opening in the encapsulation layer 210 increases the difficulty of removing the insulating layer 208. If the thickness of the insulating layer 208 is too small, the adhesion strength between the encapsulation layer 210 and the first interconnect layer 203 is reduced. At the same time, the insulating layer 208 is easily removed completely during the formation of an opening in the encapsulation layer 210. Consequently, the insulating layer 208 is less effective at stopping the etching process and can easily damage the top surface of the first interconnect layer 203, thereby affecting the reliability of the filter structure. Therefore, in this embodiment, the thickness of the insulating layer 208 is 0.01 micrometers to 3 micrometers.

[0062] The encapsulation layer 210 encapsulates the filter, providing sealing and moisture protection, thereby reducing the impact of subsequent processes on the device structure 202 and improving the reliability of the resulting filter. Furthermore, sealing the cavity 209 helps isolate it from the external environment, thus maintaining the stability of the acoustic performance of the device structure 202.

[0063] In this embodiment, the encapsulation layer 210 is located on top of the insulating layer 208.

[0064] Specifically, the insulating layer 208 improves the bonding strength between the encapsulation layer 210 and the first interconnect layer 203. For example, if the material of the first interconnect layer 203 is a metal, the adhesion between the first interconnect layer 203 and the encapsulation layer 210 will be poor if the encapsulation layer 210 is formed directly on the first interconnect layer 203.

[0065] Moreover, the adhesion strength between the encapsulation layer 210 and the insulating layer 208 is high. Under the combined action of the encapsulation layer 210 and the insulating layer 208, the sealing performance of the cavity 209 is improved, which in turn improves the reliability of the filter structure.

[0066] The encapsulation layer 210 is made of a photosensitive material or a non-photosensitive material. As an example, the encapsulation layer 210 is made of a photosensitive material. Specifically, the photosensitive material is a dry film. A dry film is a permanently bonded film with high adhesive strength, which ensures the bonding strength between the encapsulation layer 210 and the insulating layer 208, and also helps to improve the sealing of the cavity.

[0067] It should be noted that the thickness of the encapsulation layer 210 should not be too large or too small. If the thickness of the encapsulation layer 210 is too large, it increases the difficulty of patterning the encapsulation layer 210, thereby reducing production efficiency. If the thickness of the encapsulation layer 210 is too small, the size of the opening formed in the encapsulation layer 210 during the filter structure formation process will not meet the process requirements. Consequently, the size of the interconnect structure 218 formed in the opening will also not meet the process requirements, thus affecting the electrical connection between the interconnect structure 218 and the first interconnect layer 203 or the electrical connection between the interconnect structure and the external circuit. Therefore, in this embodiment, the thickness of the encapsulation layer 210 is 5 micrometers to 60 micrometers.

[0068] The interconnect structure 218 is used to realize the electrical connection between the first interconnect layer 203 and the external circuit structure.

[0069] The interconnect structure 218 extends through the encapsulation layer 210, and the interconnect structure 218 includes conductive pillars 216 and solder balls 217 located on the top surface of the conductive pillars 216.

[0070] In this embodiment, the material of the conductive pillar 216 may include an alloy composed of copper and nickel, as well as tin and silver. In other embodiments, the material of the conductive pillar may also include an alloy composed of copper and tin and silver.

[0071] The solder ball 217 can be made of tin solder, silver solder, or gold-tin alloy solder. In this embodiment, the solder ball 217 is made of tin solder.

[0072] In other embodiments, the interconnect structure extends through the encapsulation layer, and the interconnect structure is a conductive pillar.

[0073] In other embodiments, the filter structure further includes: an opening penetrating the encapsulation layer of the interconnect region and exposing the top of the first interconnect layer; the interconnect structure is a second interconnect layer located at the bottom and sidewalls of the opening and extending to cover a portion of the top of the encapsulation layer.

[0074] Figures 4 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the filter structure formation method of the present invention.

[0075] refer to Figure 4 A substrate 100 is provided, the substrate 100 including a working region 100A and an interconnect region 100B surrounding the working region 100A, and a sealing region 100C surrounding the interconnect region 100B, wherein a device structure 102 is formed on the substrate 100 of the working region 100A.

[0076] The substrate 100 is used to provide a process platform for the subsequent formation of filters.

[0077] In this embodiment, the substrate 100 is a wafer-level substrate 100.

[0078] By employing a wafer-level substrate 100, a wafer-level fabrication process can be realized in the filter structure formation method, which can reduce process costs and enable mass production, thereby improving the production efficiency of filter manufacturing.

[0079] In this embodiment, the filter structure is a filter. Specifically, the filter structure includes one or more of the following: surface acoustic wave filter, bulk acoustic wave filter, and thin-film cavity resonant filter.

[0080] The substrate 100 includes a working region 100A, which is the area where the device structure 102 operates. Specifically, the working region 100A is the working area of ​​the filter used to implement the filtering function, and a cavity is subsequently formed in the working region 100A.

[0081] In this embodiment, the substrate 100 is a wafer-level substrate 100. Therefore, the substrate 100 includes multiple device unit regions (not shown), and each device unit region includes a working area 100A and an interconnect area 100B.

[0082] In this embodiment, the formed filter is described as a surface acoustic wave (SAW) filter.

[0083] Accordingly, a piezoelectric substrate is formed on the substrate 100, enabling subsequent filters to utilize the piezoelectric effect for filtering. In this embodiment, the substrate 100 is made of one or more piezoelectric ceramic materials, such as lithium niobate (LiNbO3), lithium tantalate (LiTaO3), quartz, ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lithium barium lead niobate), and PT (lead titanate). It should be noted that rare earth elements can also be doped into the piezoelectric substrate, such as any one or a combination of scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) to improve the piezoelectric coefficient.

[0084] The device structure 102 is used to realize the mutual conversion between electrical signals and acoustic signals, thereby enabling the filter to filter the signals. Specifically, the device structure 102 is an acoustic transducer with a piezoelectric structure. In this embodiment, the formed filter is a SAW filter; therefore, the device structure 102 is a metal interdigital transducer (IDT). The material of the interdigital electrode includes one or more of Mo, Al, Pt, W, Au, Al, Ni, and Ag. In this embodiment, the interdigital electrode is an interdigital aluminum electrode. Specifically, the device structure 102 is formed by depositing a metal film on the substrate 100 and patterning the metal film through photolithography and etching processes.

[0085] In this embodiment, the substrate 100 further includes an interconnect region 100B surrounding the working region 100A, and a first interconnect layer is subsequently formed on the interconnect region 100B, the first interconnect layer being electrically connected to the device structure 102.

[0086] Specifically, the first interconnect layer is used as an input / output (I / O) terminal of the device structure 102, and the first interconnect layer is used to electrically connect the input interdigital transducer and the output interdigital transducer, respectively.

[0087] It should be noted that, in other embodiments, the method for forming the filter structure can also be used to form bulk acoustic wave filters (BAW-SMR) and thin-film cavity resonators (FBAR). Accordingly, the device structure includes a piezoelectric stack structure.

[0088] In this embodiment, the step of providing the substrate 100 further includes a sealing region 100C surrounding the interconnect region 100B.

[0089] Specifically, a sealing layer is subsequently formed on the sealing area 100C. The sealing layer protects the device structure in the working area 100A and the first interconnect layer in the interconnect area 100B, reducing the probability of contaminants and moisture entering the working area 100A. Correspondingly, it reduces the probability of corrosion of the device structure in the working area 100A and the interconnect structure in the interconnect area 100B.

[0090] Accordingly, when the substrate 100 includes multiple device unit regions, each device unit region also includes a sealing region 100C.

[0091] Continue to refer to Figure 4 The surface of the substrate 100 is then cleaned.

[0092] Specifically, cleaning the surface of the substrate 100 increases the bonding strength between the buffer layer subsequently formed on top of the substrate 100 and the substrate 100. Correspondingly, it also reduces the probability of delamination problems caused by thermal stress generated by the subsequently formed first interconnect layer and encapsulation layer.

[0093] In this embodiment, the cleaning process for the surface of the substrate 100 includes one or both of dry plasma cleaning and wet cleaning.

[0094] refer to Figure 5 A buffer layer 101 is formed on top of the substrate 100 in the interconnect region 100B and the sealing region 100C.

[0095] In this embodiment, a buffer layer 101 is formed on top of the substrate 100 in the interconnect region 100B, such that the buffer layer 101 is located between the substrate 100 and the first interconnect layer. After the device structure temperature changes, the buffer layer 101 helps to offset or weaken the thermal stress generated between the subsequently formed first interconnect layer and the encapsulation layer, thereby buffering the thermal stress generated between the first interconnect layer and the encapsulation layer, reducing the probability of delamination problems or substrate 100 cracking problems caused by the thermal stress generated between the first interconnect layer and the encapsulation layer, and thus improving the reliability of the filter structure.

[0096] In this embodiment, the step of forming the buffer layer 101 includes: forming a buffer material layer (not shown) covering the substrate 100 and the device structure 102; removing the buffer material layer in the working area 100A, and the remaining buffer material layer serving as the buffer layer 101.

[0097] Specifically, in order to reduce the difficulty of forming the buffer layer 101, the buffer material layer is selected from materials that are easy to pattern. Therefore, in this embodiment, the material of the buffer material layer is a photosensitive material, the buffer material layer is patterned by photolithography, and the buffer material layer in the working area 100A is removed.

[0098] Meanwhile, using photosensitive material as the material of the buffer material layer is beneficial to the realization of photolithography patterning, and reduces the probability of damage to the device structure 102 during the patterning process of the buffer material layer.

[0099] In this embodiment, in the step of forming a buffer layer 101 on top of the substrate 100 in the interconnect region 100B, the buffer layer 101 is also formed on top of the substrate 100 in the sealing region 100C.

[0100] Specifically, a sealing layer will be formed on top of the buffer layer 101 in the sealing region 100C. In order to reduce the probability of delamination or substrate 100 cracking due to thermal stress generated between the sealing layer and the encapsulation layer, the buffer layer 101 is also formed on top of the substrate 100 in the sealing region 100C.

[0101] In this embodiment, the material of the buffer layer 101 includes a polymeric organic material.

[0102] The polymeric organic material has a low Young's modulus. Young's modulus is a physical quantity that measures a material's resistance to deformation. When subjected to external stress, the polymeric organic material deforms while also offsetting or weakening the external stress, thus enabling the buffer layer 101 to play a buffering role.

[0103] In other embodiments, the coefficient of thermal expansion of the material used for the buffer layer is between that of the material used for the subsequently formed encapsulation layer and the material used for the first interconnect layer.

[0104] Specifically, when the coefficient of thermal expansion of the buffer layer is between that of the encapsulation layer and the first interconnect layer, the buffer layer can offset or weaken the thermal stress generated by the encapsulation layer and the first interconnect layer, thereby enabling the buffer layer to play a buffering role.

[0105] It should be noted that the process of forming the buffer layer 101 on top of the substrate 100 in the interconnect region 100B includes a spin coating process.

[0106] The spin coating process has the characteristics of high film density and fast speed. Under external thermal stress, the morphology of the buffer layer 101 formed by the spin coating process is not easily deformed, thereby improving the reliability of the filter structure.

[0107] In other embodiments, the process of forming the buffer layer may also employ a spraying process.

[0108] refer to Figure 6 A first interconnect layer 103 is formed on the top of the buffer layer 101 in the interconnect region 100B, on the sidewall near the working region 100A, and on the buffer layer 101 in the sealing region 100C. The first interconnect layer 103 also extends into the working region 100A and is electrically connected to the device structure 102. The first interconnect layer 103 located in the sealing region 100C serves as a sealing layer 106.

[0109] The first interconnect layer 103 is electrically connected to the device structure 102. The first interconnect layer 103 serves as an input / output (I / O) terminal of the device structure 102. The first interconnect layer 103 is used to electrically connect the device structure 102 to an external circuit structure.

[0110] In this embodiment, the first interconnect layer 103 is also formed on the buffer layer 101 of the sealing region 100C, serving as a sealing layer 106.

[0111] It should be noted that, while forming the first interconnect layer 103, a sealing layer 106 is also formed on the buffer layer 101 of the sealing region 100C. This reduces the step of removing the first interconnect layer 103 in the sealing region 100C to form the sealing layer 106, reduces the impact of multiple etching processes on the top surface of the buffer layer 101, and also reduces the process cost by reducing the number of process steps.

[0112] In this embodiment, the process of forming interconnect material layers on the top and sidewalls of the buffer layer 101 and on the top of the device structure 102 of the working area 100A includes physical vapor deposition, vacuum evaporation, electroless plating, or electroplating.

[0113] In this embodiment, the step of forming the first interconnect layer 103 includes: forming an interconnect material layer (not shown) on the top and sidewalls of the buffer layer 101 and on the top of the device structure 102 of the working area 100A; removing the interconnect material layer on the top of the device structure 102 and the interconnect material layer at the junction of the interconnect region 100B and the sealing region 100C, with the remaining interconnect material layer in the interconnect region 100B serving as the first interconnect layer 103, and the interconnect material layer in the sealing region 100C serving as the sealing layer 106.

[0114] It should be noted that the working area 100A also includes a conductive area that is electrically connected to the first interconnect layer 103. The conductive area exposed by the buffer layer 101 is covered by the first interconnect layer 103 during the step of forming the first interconnect layer 103, thereby achieving electrical connection between the first interconnect layer 103 and the device structure 102.

[0115] In this embodiment, the process of removing the interconnect material layer on the top of the device structure 102 and the interconnect material layer at the junction of the interconnect region 100B and the sealing region 100C includes a dry etching process.

[0116] The material of the first interconnect layer 103 includes one or more of Ti, Cu, Al, and Ni. Specifically, Ti, Cu, Al, and Ni are all conductive materials, enabling the device structure in the working area 100A to be electrically connected to the external power distribution structure through the first interconnect layer 103. As an example, the material of the first interconnect layer 103 is Al.

[0117] It should be noted that the thickness of the first interconnect layer 103 should not be too large or too small. If the thickness of the first interconnect layer 103 is too large, it increases the difficulty of removing the interconnect material layer at the junction of the interconnect region 100B and the sealing region 100C. Furthermore, increasing the thickness of the first interconnect layer 103 leads to an increase in the aspect ratio during the patterning of the interconnect material layer, which correspondingly increases the difficulty of patterning the interconnect material layer. If the thickness of the first interconnect layer 103 is too small, it can easily lead to an insufficient effective height of the cavity subsequently formed in the working region 100A. Consequently, after the encapsulation layer is deformed by external force, the probability of the encapsulation layer contacting the device structure 102 increases, thereby reducing the reliability of the filter structure. Therefore, in this embodiment, the thickness of the first interconnect layer 103 is 2 micrometers to 30 micrometers.

[0118] In other embodiments, the step of forming the first interconnect layer includes: forming a first seed layer on top of the buffer layer and its sidewalls, and on top of the device structure of the working area; forming a mask layer on top of the first seed layer in the working area, and on top of the first seed layer at the junction of the interconnect area and the sealing area; forming an interconnect material layer on top of the first seed layer exposed by the first mask layer, wherein the interconnect material layer located in the interconnect area serves as the first interconnect layer, and the interconnect material layer located in the sealing area serves as the sealing layer; and removing the mask layer, and the first seed layer exposed by the first interconnect layer and the sealing layer.

[0119] refer to Figure 7 An insulating layer 108 is formed on the top and sidewalls of the first interconnect layer 103 and on the top and sidewalls of the device structure 102 of the working area 100A.

[0120] Specifically, the insulating layer 108 located on top of the first interconnect layer 103 increases the adhesion strength between the subsequently formed encapsulation layer and the first interconnect layer 103, reducing the probability of gaps forming between the encapsulation layer and the first interconnect layer 103. On the other hand, during the subsequent process of forming an opening in the encapsulation layer that exposes the top of the first interconnect layer 103, the insulating layer 108 can define the etching stop position, reducing the probability of over-etching.

[0121] Meanwhile, an insulating layer 108 is formed on the top of the device structure 102 in the working area 100A, which reduces the probability of the device structure 102 in the working area 100A coming into contact with the outside air. Correspondingly, this reduces the probability of the device structure 102 in the working area 100A being oxidized and corroded, thereby improving the reliability of the filter structure.

[0122] It should be noted that the first interconnect layer 103 is also formed on the buffer layer 101 of the sealing region 100C, serving as a sealing layer 106, and the insulating layer 108 is correspondingly formed on the top and sidewalls of the sealing layer 106.

[0123] It should also be noted that the process for forming the insulating layer 108 includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition. As an example, the process for forming the insulating layer 108 is atomic layer deposition. Atomic layer deposition involves multiple atomic layer deposition cycles, providing good step coverage and improving the thickness uniformity of the insulating layer 108.

[0124] In this embodiment, the insulating layer 108 is made of one or more of SiO2, SiN, and Al2O3. SiO2, SiN, and Al2O3 serve as dielectric materials, which, during the subsequent formation of the opening exposing the top of the first interconnect layer 103 in the encapsulation layer, satisfies the etching selectivity ratio between the insulating layer 108 and the encapsulation layer, reducing the difficulty of forming the opening.

[0125] It should be noted that the thickness of the insulating layer 108 should not be too large or too small. If the thickness of the insulating layer 108 is too large, it increases the difficulty of removing the insulating layer 108 during the subsequent opening formation process; if the thickness of the insulating layer 108 is too small, it reduces the adhesion strength between the subsequently formed encapsulation layer and the first interconnect layer 103. Furthermore, during the subsequent opening formation process, the insulating layer 108 is easily removed completely, making it difficult for it to act as an etching stop, potentially damaging the top surface of the first interconnect layer 103 and affecting the reliability of the filter structure. Therefore, in this embodiment, the thickness of the insulating layer 108 is 0.01 micrometers to 3 micrometers.

[0126] refer to Figure 8 An encapsulation layer 110 is formed on top of the first interconnect layer 103 and on top of the substrate 100 of the working area 100A. In the working area 100A, the encapsulation layer 110, the sidewall of the buffer layer 101, and the substrate 100 form a cavity 109, which is used to accommodate the device structure.

[0127] The encapsulation layer 110 encapsulates the filter, providing sealing and moisture protection, thereby reducing the impact of subsequent processes on the device structure 102 and improving the reliability of the resulting filter. Furthermore, sealing the cavity 109 helps isolate it from the external environment, thus maintaining the stability of the acoustic performance of the device structure 102.

[0128] In this embodiment, the encapsulation layer 110 is located on top of the insulating layer 108.

[0129] As described above, the insulating layer 108 improves the bonding strength between the encapsulation layer 110 and the first interconnect layer 103. For example, if the material of the first interconnect layer 103 is a metal, and the encapsulation layer 110 is formed directly on the first interconnect layer 103, the adhesion between the first interconnect layer 103 and the encapsulation layer 110 will be poor.

[0130] Moreover, the adhesion strength between the encapsulation layer 110 and the insulating layer 108 is high. Under the combined action of the encapsulation layer 110 and the insulating layer 108, the sealing performance of the cavity 109 is improved, which in turn improves the reliability of the filter structure.

[0131] The encapsulation layer 110 is made of either a photosensitive material or a non-photosensitive material. As an example, the encapsulation layer 110 is made of a photosensitive material, which facilitates subsequent patterning of the encapsulation layer, thereby reducing the complexity and precision of the patterning process. Specifically, the photosensitive material is a dry film. Dry film is a permanently bonded film with high adhesive strength, ensuring the bonding strength between the encapsulation layer 110 and the insulating layer 108, while also improving the sealing of the cavity.

[0132] In this embodiment, the photosensitive material is a film-like dry film, which simplifies the process of forming the encapsulation layer 110. The film-like dry film is manufactured by coating a solvent-free photoresist onto a polyester substrate, then covering it with a polyethylene film; in use, the polyethylene film is removed, and the solvent-free photoresist is pressed onto the substrate. Therefore, in this embodiment, a lamination process is used to form the encapsulation layer 110. The lamination process is performed in a vacuum environment, providing excellent step coverage and significantly improving the adhesion and bonding strength between the encapsulation layer 110 and the insulating layer 108.

[0133] In other embodiments, a liquid dry film can also be used to form the encapsulation layer, wherein the liquid dry film refers to a film in which the components exist in a liquid form. Accordingly, the steps for forming the encapsulation layer include: applying the liquid dry film via spin coating; and curing the liquid dry film to form the encapsulation layer. The cured liquid dry film is also a photosensitive material. In other embodiments, the material of the encapsulation layer can also be a dielectric material or an organic material. Accordingly, the encapsulation layer can be formed using a deposition process or a coating process, respectively. The dielectric material can be silicon oxide, phosphosilicate glass (PSG), or borosilicate glass (BPSG), and the organic material can be polyimide.

[0134] It should be noted that the thickness of the encapsulation layer 110 should not be too large or too small. If the thickness of the encapsulation layer 110 is too large, it increases the difficulty of removing the encapsulation layer 110 during the subsequent formation of the opening. It also increases the size of the opening formed in the encapsulation layer 110, resulting in an increased overall area of ​​the filter structure and excessive material waste in the encapsulation layer 110, thus increasing process costs. If the thickness of the encapsulation layer 110 is too small, it reduces the external pressure resistance it can withstand, decreasing its airtightness and waterproof performance, thereby placing higher demands on the subsequent manufacturing processes and application environment of the filter structure. Therefore, in this embodiment, the thickness of the encapsulation layer 110 is 5 micrometers to 60 micrometers.

[0135] refer to Figures 9 to 10 In the interconnect region 100B, an opening 113 is formed in the encapsulation layer 110 to expose the top of the first interconnect layer 103.

[0136] The opening 113 is used to provide spatial location for the interconnect structure to be formed subsequently.

[0137] In this embodiment, the opening 113 penetrates the encapsulation layer 110 and the insulating layer 108.

[0138] The opening 113 penetrates the encapsulation layer 110 and the insulating layer 108, exposing the top surface of the first interconnect layer 103, thereby facilitating the electrical connection between the subsequently formed interconnect structure and the exposed top surface of the first interconnect layer 103.

[0139] Reference Figures 9 to 10 The process steps for forming the opening 113 are described in detail below.

[0140] refer to Figure 9 The encapsulation layer 110 is graphically represented, and a first initial opening 111 is formed in the encapsulation layer 110 in the interconnect region 100B, the first initial opening 111 exposing the top surface of the insulating layer 108.

[0141] The first initial opening 111 serves as a mask opening for the insulating layer 108 to be exposed by subsequent etching.

[0142] Furthermore, the top of the insulating layer 108 can define the stop position of the patterning process when the patterned packaging layer 110 is patterned, thereby protecting the first interconnect layer 103 and reducing the probability of damage to the top surface of the first interconnect layer 103.

[0143] As can be seen from the foregoing, the material of the encapsulation layer 110 is a dry film, which is a photosensitive material. Therefore, the encapsulation layer 110 is patterned by photolithography to form a first initial opening 111 that penetrates the encapsulation layer 110.

[0144] By using photolithography, it is beneficial to improve the morphological quality and dimensional accuracy of the first initial opening 111.

[0145] In other embodiments, the packaging layer can also be patterned using a dry etching process. Dry etching is characterized by anisotropic etching, and its use can improve the morphological quality and dimensional accuracy of the first initial opening. Accordingly, a photolithography process, including photoresist coating, exposure, and development, is used to form a photoresist mask. The packaging layer is then etched through the photoresist mask to form the first initial opening. When the packaging layer is patterned using an etching process, the top of the insulating layer can define an etching stop position.

[0146] refer to Figure 10 The insulating layer 108 exposed by the first initial opening 111 in the encapsulation layer 110 is etched, and a second initial opening 112 is formed in the insulating layer 108. The first initial opening 111 and the second initial opening 112 constitute the opening 113.

[0147] Specifically, using the encapsulation layer 110 as a mask, the exposed insulating layer 108 is removed along the first initial opening 111. Therefore, the process of removing the exposed insulating layer 108 from the first initial opening 111 is simple and has high process compatibility.

[0148] In this embodiment, the process of removing the exposed insulating layer 108 along the first initial opening 111 includes a wet etching process.

[0149] Wet etching has the characteristics of isotropic etching. By selecting wet etching, it is also beneficial to improve the morphological quality and dimensional accuracy of the second initial opening 112, while reducing the impact on the top surface of the first interconnect layer 103.

[0150] Specifically, the etching selectivity ratio of the insulating layer 108 to the encapsulation layer 110 should not be too small. If the etching selectivity ratio is too small, the top surface of the first interconnect layer 103 is easily damaged during the formation of the second initial opening 112, affecting the electrical connection between the subsequently formed interconnect structure and the first interconnect layer 103, thereby affecting the reliability of the filter structure. Therefore, in this embodiment, the etching selectivity ratio of the insulating layer 108 to the encapsulation layer 110 is 100:1.

[0151] In other embodiments, a dry etching process can also be used to remove the exposed insulating layer 108.

[0152] refer to Figure 11 An interconnect structure 118 is formed in the opening 113, and the bottom of the interconnect structure 118 is electrically connected to the top of the first interconnect layer 103.

[0153] The interconnect structure 118 is used to realize the electrical connection between the first interconnect layer 103 and the external circuit structure.

[0154] In this embodiment, a bump process is used to form the interconnect structure 118 in the opening 113. Using the bump process facilitates subsequent packaging processes.

[0155] Specifically, the bump process is a metal pillar process.

[0156] In this embodiment, a conductive post 116 is formed in the opening 113; a solder ball 117 is formed on the top surface of the conductive post 116, and the solder ball 117 and the conductive post 116 are used to form the interconnection structure 118.

[0157] Specifically, the step of forming the conductive post 116 includes: forming a second seed layer (not shown) on the top of the encapsulation layer 110 and the bottom and sidewalls of the opening 113; forming a second mask layer (not shown) on top of the second seed layer located outside the opening 113; and forming the conductive post 116 in the remaining space of the opening 113 after forming the second mask layer.

[0158] In this embodiment, the material of the conductive pillar 116 may include an alloy of copper and nickel, and tin and silver. In other embodiments, the material of the conductive pillar may also include an alloy of copper and tin and silver.

[0159] In this embodiment, the conductive pillar 116 can be formed by electroplating. In other embodiments, the conductive pillar can also be formed by any one of PVD, CVD, vacuum evaporation, or electroless plating.

[0160] It should be noted that after forming the conductive pillar 116, the process further includes: removing the second mask layer and the second seed layer exposed by the conductive pillar 116.

[0161] In this embodiment, the process of removing the second mask layer and the second seed layer exposed by the interconnect structure 118 includes a dry etching process or a wet etching process.

[0162] In this embodiment, after removing the second mask layer and the second seed layer exposed by the conductive post 116, solder balls 117 are formed on the top surface of the conductive post 116. The solder balls 117 and the conductive post 116 are used to form the interconnect structure 118.

[0163] The solder ball 117 can be made of tin solder, silver solder, or gold-tin alloy solder, and can be formed by any one of the following processes: PVD, CVD, vacuum evaporation, electroplating, or electroless plating. In this embodiment, the solder ball 117 is made of tin solder.

[0164] refer to Figure 12 In other embodiments, conductive pillars may also be formed in the openings, which serve as the interconnect structure.

[0165] Specifically, conductive pillars are formed in the opening using a chemical plating process.

[0166] It should be noted that the step of forming a conductive pillar in the opening using a chemical plating process includes: removing a small amount of organic residue from the surface of the first interconnect layer; etching the first interconnect layer to expose a new metal surface; depositing a solution containing active target ions on the surface of the first interconnect layer; initially cleaning the solution from the surface of the first interconnect layer; cleaning the surface of the first interconnect layer again to remove the target atoms from the surface of the first interconnect layer; depositing a nickel-phosphorus alloy centered on palladium atoms, and a new nickel layer will continue to be deposited on the surface of the nickel. The above reactions continue until the opening of the encapsulation layer 110 is completely filled with nickel (nickel-phosphorus alloy), that is, a conductive pillar is formed in the opening.

[0167] refer to Figure 13 In other embodiments, a second interconnect layer may also be formed at the bottom and sidewalls of the opening, the second interconnect layer extending to cover a portion of the top of the encapsulation layer, the second interconnect layer serving as the interconnect structure.

[0168] Specifically, the steps for forming the interconnect structure include: forming a third seed layer on top of the encapsulation layer 110 and on the bottom and sidewalls of the opening 113; forming a third mask layer on top of the third seed layer located outside the opening 113; and after forming the third mask layer, forming a conductive layer on top of the third seed layer by means of an electroplating process, wherein the conductive layer and the third seed layer constitute the interconnect structure.

[0169] It should be noted that after forming the interconnect structure, the process further includes: removing the third mask layer and the third seed layer exposed by the interconnect structure.

[0170] In this embodiment, after the interconnect structure 118 is formed in the opening 113, the process further includes grinding and dicing the wafer.

[0171] Specifically, since the wafer includes multiple device unit regions, each device unit region is cut to separate them, thereby forming a single packaged product.

[0172] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A filter structure, characterized in that, include: A substrate, the substrate including a working region and an interconnect region surrounding the working region, and a sealing region surrounding the interconnect region; The device structure is located on the substrate of the working area; A buffer layer is located on top of the substrate in the interconnect region and on top of the substrate in the sealing region. The material of the buffer layer includes a polymeric organic material having a low Young's modulus. A first interconnect layer is located on top of the buffer layer and on the sidewall near the working area. The first interconnect layer also extends into the working area and is electrically connected to the device structure. A sealing layer is located on top of the buffer layer in the sealing area; An insulating layer is located on top of and sidewalls of the first interconnect layer, and the insulating layer also covers the top and sidewalls of the device structure in the working area; An encapsulation layer is located on top of the insulating layer and above the top of the substrate in the working area. The encapsulation layer is made of dry film. In the working area, the encapsulation layer, the sidewall of the buffer layer, and the substrate form a cavity for accommodating the device structure. An interconnect structure is located in the encapsulation layer of the interconnect region, and the bottom of the interconnect structure is electrically connected to the top of the first interconnect layer.

2. The filter structure as described in claim 1, characterized in that, The thickness of the first interconnect layer is 2 micrometers to 30 micrometers.

3. The filter structure as described in claim 1, characterized in that, The insulating layer is made of one or more of SiO2, SiN and Al2O3.

4. The filter structure as described in claim 1, characterized in that, The interconnect structure extends through the encapsulation layer, and the interconnect structure is a conductive pillar; Alternatively, the interconnect structure extends through the encapsulation layer, and the interconnect structure includes conductive pillars and solder balls located on the top surface of the conductive pillars; Alternatively, the filter structure may further include: an opening that penetrates the encapsulation layer of the interconnect region and exposes the top of the first interconnect layer; The interconnect structure is a second interconnect layer, which is located at the bottom and sidewalls of the opening and extends to cover a portion of the top of the encapsulation layer.

5. The filter structure as described in claim 1, characterized in that, The thickness of the encapsulation layer is 5 micrometers to 60 micrometers.

6. The filter structure as described in claim 1, characterized in that, The material of the first interconnect layer includes one or more of Ti, Cu, Al and Ni.

7. The filter structure as described in claim 1, characterized in that, The sealing layer is made of the same material as the first interconnect layer.

8. The filter structure as described in claim 1, characterized in that, The filter structure includes one or more of the following: surface acoustic wave filter, bulk acoustic wave filter, and thin-film cavity resonant filter.

9. A method for forming a filter, characterized in that, include: A substrate is provided, the substrate including a working region and an interconnect region surrounding the working region, and a sealing region surrounding the interconnect region, wherein a device structure is formed on the substrate of the working region; A buffer layer is formed on top of the substrate in the interconnect region and the sealing region. The material of the buffer layer includes a polymeric organic material, which has the characteristic of low Young's modulus. A first interconnect layer is formed on the top of the buffer layer in the interconnect region, on the sidewall near the working region, and on the buffer layer in the sealing region. The first interconnect layer also extends into the working region and is electrically connected to the device structure. The first interconnect layer located in the sealing region serves as a sealing layer. An insulating layer is formed on the top and sidewalls of the first interconnect layer, and on the top and sidewalls of the device structure in the working area; An encapsulation layer is formed on top of the insulating layer and on top of the substrate of the working area. The material of the encapsulation layer is a dry film. The encapsulation layer, the sealing layer, and the substrate form a cavity for accommodating the device structure. In the interconnect region, an opening is formed in the encapsulation layer to expose the top of the first interconnect layer; An interconnect structure is formed in the opening, and the bottom of the interconnect structure is electrically connected to the top of the first interconnect layer.

10. The method for forming a filter as described in claim 9, characterized in that, In the step of forming the opening, the opening penetrates the encapsulation layer and the insulating layer.

11. The method for forming a filter as described in claim 10, characterized in that, The step of forming the opening includes: etching the encapsulation layer with the top of the insulating layer as the etching stop position; and etching the insulating layer exposed by the encapsulation layer.

12. The method for forming a filter as described in claim 9, characterized in that, In the step of providing a substrate, the substrate is a wafer-level substrate.

13. The method for forming a filter as described in claim 9, characterized in that, Before forming the buffer layer, the process further includes cleaning the surface of the substrate.

14. The method for forming a filter as described in claim 9, characterized in that, The step of forming the buffer layer includes: forming a buffer material layer covering the substrate and the device structure; removing the buffer material layer in the working area, with the remaining buffer material layer serving as the buffer layer.

15. The method for forming a filter as described in claim 14, characterized in that, The buffer material layer is made of a photosensitive material; the buffer material layer is patterned using a photolithography process, and then the buffer material layer in the working area is removed.

16. The method for forming a filter as described in claim 9, characterized in that, The process of forming a buffer layer on top of the substrate in the interconnect region includes spin coating or spray coating.

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