A linear block code encoding and decoding method, system, device and storage medium

Abstract

The present application relates to the technical field of wireless communication, in particular to a linear block code encoding and decoding method, system, device and storage medium. The method comprises: a transmitting end encodes 3-bit information symbols according to a generator matrix to obtain a 36-bit encoding output sequence; wherein the 36-bit encoding output sequence comprises the 3-bit information symbols and 33-bit check symbols; symbol padding processing is performed on the 36-bit encoding output to extend the 36-bit encoding output into a 96-bit data sequence; scrambling processing is performed on the 96-bit data sequence and data is output; a receiving end performs descrambling processing on the received data to obtain descrambled data; data merging processing is performed on the descrambled data to obtain a 36-bit data sequence; and decoding processing is performed on the 36-bit data sequence to obtain original SIG data.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a linear block code encoding and decoding method, system, device, and storage medium. Background Technology

[0002] Low-power wireless communication must utilize radio waves for channel transmission. Compared to wired channels, radio waves generally have poor propagation characteristics. Firstly, the operating environment for wireless communication is highly complex. Radio waves not only suffer from diffusion loss over propagation distance but also experience "shadowing effects" due to terrain and obstacles. Furthermore, signals undergo multiple reflections, reaching the receiving point via multiple paths. These multipath signals typically have different amplitudes, phases, and arrival times, and their superposition leads to signal fading and delay spread. Secondly, wireless communication often occurs during rapid movement, which not only causes Doppler shift and random frequency modulation but also results in rapid, random fluctuations in the propagation characteristics of radio waves, severely impacting communication quality.

[0003] Because data transmission in wireless channels is highly complex, various factors such as noise, delay, and multipath fading can cause distortion of the transmitted signal upon arrival at the receiver, making bit errors in the received sequence unavoidable. If a code element carrying crucial information is corrupted during the transmission of a single data frame, the entire frame will be erroneous. Therefore, selecting a decoding method with excellent decoding performance at the receiver, while ensuring coding performance, is crucial for data transmission in wireless communication.

[0004] Linear block codes, as an important error control channel coding technique, have been widely used in communication systems, possessing advantages such as high encoding and decoding efficiency, simple implementation, and low decoding delay. Liu Jin proposed a block code encoding and decoding method using (5,2) linear block codes as an example. This method creates a standard decoding table based on the syndrome and error pattern, and obtains the decoding result based on this table, but does not provide a specific implementation strategy for this block code encoding and decoding method. Xia Zhida et al. proposed an encoding and decoding design scheme for (7,4) Hamming codes based on CCS, providing the (7,4) Hamming code encoding and decoding circuit and programming it using C++ Builder and CCS. However, the serial processing of signals within CCS increases the decoding delay. To reduce the decoding delay, Li Shujing et al., leveraging the high signal processing speed of FPGAs (Field-Programmable Gate Arrays), designed a (25,20) linear block code encoder and decoder using parallel processing and implemented it in FPGA hardware. However, the design of the (25, 20) linear block code encoder and decoder can only correct errors in one information symbol, and the use of the supervision matrix to search for error positions and correct erroneous symbols during the decoding process implemented on the FPGA consumes a lot of hardware resources. Summary of the Invention

[0005] This invention proposes a (36,3) block code decoder design method to address the issue of bit errors in received sequences caused by various factors such as noise, delay, and multipath fading in wireless communication channels. Even when all three information bits are erroneous, this (36,3) block code decoder design method can correct the erroneous information bits using check bits, thus ensuring accurate decoding output of sequences carrying critical information. This invention leverages the high speed and parallelism of FPGAs to achieve high encoding efficiency in the (36,3) encoding circuit. Simultaneously, the rationally designed decoding module circuit structure results in a decoder design that is simple and has low decoding delay.

[0006] To address the aforementioned technical problems, the first aspect of this invention provides a linear block code encoding and decoding method, comprising the following steps: A transmitting end encodes an input 3-bit information code element according to a generator matrix to obtain a 36-bit encoded output sequence; wherein the 36-bit encoded output sequence includes the 3-bit information code element and a 33-bit check code element; the 36-bit encoded output is then filled with symbols to expand it into a 96-bit data sequence; the 96-bit data sequence is scrambled and output; a receiving end descrambles the received data to obtain descrambled data; the descrambled data is then merged to obtain a 36-bit data sequence; and the 36-bit data sequence is decoded to obtain the original SIG data.

[0007] In some exemplary embodiments, the step of scrambling the 96-bit data sequence and outputting the data includes: performing an XOR operation on the 96-bit data sequence using a repeating pseudo-random noise sequence generated by a scrambling polynomial to obtain the data and outputting it; wherein the scrambling polynomial is: S(x) = x 10 +x 3 +1.

[0008] In some exemplary embodiments, the step of encoding the input 3-bit information symbols at the transmitting end according to the generator matrix to obtain a 36-bit encoded output sequence includes: the formula for the generator matrix is ​​c = u·G; where the input information symbol sequence is u = (u0, u1, u2), the generator matrix G is a 3×36 matrix, the matrix is ​​instantiated column by column into a ROM, a counter is set to count so that every 3 bits of data is encoded once, and the result of the operation is buffered by circular shifting; after 36 encoding operations, the result of the operation is serially output to obtain the encoded output c = (c0, c1, c2, ... c 35The first 3 bits of the encoded output are information code elements, and the last 33 bits are the check code elements obtained by linear operation of the first 3 information code elements.

[0009] In some exemplary embodiments, the step of performing sign padding on the 36-bit encoded output to expand the 36-bit encoded output into a 96-bit data sequence includes: performing a copy operation on the 36-bit encoded output to expand the encoded output into a 96-bit data sequence.

[0010] In some exemplary embodiments, the step of scrambling the 96-bit data sequence and outputting the data includes: performing an XOR operation on the 96-bit data sequence using a repeating pseudo-random noise sequence generated by a scrambling polynomial to obtain the data and outputting it; wherein the scrambling polynomial is: S(x) = x 10 +x 3 +1; The step of descrambling the received data at the receiving end to obtain the descrambled data includes: performing an XOR operation on the 96-bit data sequence with a descrambling polynomial to recover the original data and output it; wherein the descrambling polynomial is consistent with the scrambling polynomial.

[0011] In some exemplary embodiments, the decoding process includes: obtaining the parity-check matrix H based on the generator matrix, and obtaining the syndrome as: S = YH T =(c+e)H T =cH T +eH T ; by cH T =0, therefore: S=YH T =eH T The transmitted codeword is c = (c0, c1, c2, ... c). 35 The received symbol sequence is Y = (y0, y1, y2, ..., y). 35 During codeword transmission, the error pattern caused by channel noise interference is e = (e0, e1, e2, ..., e 35 If ), then we get Y = c + e; when the syndrome S = YH T =0, then the error pattern e=0, indicating that there is no error in the received symbol sequence; when the syndrome S=YH T If e ≠ 0, then the incorrect pattern e ≠ 0, where e i =1 indicates that the i-th bit of the received code sequence has a decoding error, and the corrected codeword is:

[0012] In some exemplary embodiments, the decoding process further includes: obtaining the encoded output result according to c = u·G; converting the input serial data into 36-bit parallel data through a shift register and a counter; performing an XOR operation on the received 36-bit symbol sequence and the correct encoded output stored in the register to obtain multiple search values; counting the number of 1s in the output result of the XOR operation using multiple counters, storing the values ​​of each counter to obtain the number of erroneous symbols; comparing the values ​​of each counter pairwise using the parallelism of the FPGA to obtain the minimum value of the counter; obtaining the correct decoded output based on the minimum value of the counter; and serially outputting the obtained decoded result.

[0013] A second aspect of the present invention provides a linear block code encoding and decoding system, comprising a transmitting end and a receiving end. The transmitting end includes a block code encoding module, a symbol stuffing module, and a scrambling module. The block code encoding module encodes 3-bit information symbols input according to a generator matrix to obtain a 36-bit encoded output sequence. The symbol stuffing module stuffs the 36-bit encoded output with symbols to expand it into a 96-bit data sequence. The scrambling module scrambles the 96-bit data sequence and outputs the data. The receiving end includes a descrambling module, a data merging module, and a block code decoding module. The descrambling module descrambles the received data to obtain descrambled data. The data merging module merges the descrambled data to obtain a 36-bit data sequence. The block code decoding module decodes the 36-bit data sequence to obtain the original SIG data.

[0014] In some exemplary embodiments, the block code decoding module includes a data storage unit, a shift buffer unit, a search value calculation unit, a search error symbol count unit, a minimum value calculation unit, a result decision unit, and a serial output unit. The data storage unit is used to obtain the encoded output result according to c = u·G. The shift buffer unit is used to convert the input serial data into 36-bit parallel data through a shift register and a counter. The search value calculation unit is used to perform an XOR operation on the received 36-bit symbol sequence and the correctly encoded output stored in the register to obtain multiple search values. The search error symbol count unit is used to count the number of 1s in the XOR operation output results using multiple counters, and store the values ​​of each counter to obtain the number of error symbols. The minimum value calculation unit is used to compare the values ​​of each counter pairwise using the parallelism of the FPGA to obtain the minimum value of the counter. The result decision unit is used to obtain the correct decoded output based on the minimum value of the counter. The serial output unit is used to serially output the obtained decoded result.

[0015] A third aspect of the present invention provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the linear block code encoding and decoding method as described above.

[0016] A fourth aspect of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described linear block code encoding and decoding method.

[0017] The technical solution provided by this invention has at least the following advantages:

[0018] This invention provides a linear block code encoding and decoding method, system, device, and storage medium. Based on a given data frame structure, this invention proposes an improved method for SIG data, building upon existing block code encoding and decoding techniques. First, a (36,3) linear block code encoding and decoding design method is proposed, combined with symbol stuffing and scrambling techniques, to achieve good diversity gain performance, significantly reducing the impact of multipath fading. Simultaneously, the interference signal can be randomized, which helps reduce the peak-to-average power ratio, thereby improving the reliability of signal transmission. Then, in the design of the (36,3) linear block code decoder, by verifying the symbol sequence, the decoder possesses error correction capabilities capable of correcting multi-bit symbol errors, exhibiting better decoding error correction capabilities compared to existing technologies. Finally, in the hardware implementation of the (36,3) linear block code decoder, instead of using e = S(H... T ) -1 Instead of obtaining error patterns for error correction, this method uses registers to store the encoded output, compares it with the decoding input sequence, counts the number of erroneous symbols, and then corrects the error to obtain the correct decoded output. This simplifies the decoding process, reduces the workload of hardware implementation, and saves a significant amount of hardware resources. Furthermore, simulation waveforms of the (36,3) linear block code decoder show that the entire decoding process can be completed in just 7 clock cycles. Combined with the efficiency of FPGAs, this greatly reduces decoding latency. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1 This application provides an embodiment of the (36, 3) block code encoder / decoder architecture.

[0021] Figure 2This is a wireless communication system frame format provided in one embodiment of this application;

[0022] Figure 3 A scrambling flowchart provided for one embodiment of this application;

[0023] Figure 4 A hardware implementation block diagram of a (36, 3) linear block code encoder provided in an embodiment of this application;

[0024] Figure 5 Simulation waveform of a (36, 3) linear block code encoder provided in an embodiment of this application;

[0025] Figure 6 This is a hardware implementation block diagram of a (36, 3) linear block code decoder provided in an embodiment of this application;

[0026] Figure 7 Simulation waveform of a (36, 3) linear block code decoder provided in an embodiment of this application;

[0027] Figure 8 This is a schematic diagram of the structure of an electronic device provided by the present invention. Detailed Implementation

[0028] As the background technology shows, existing block code encoding and decoding methods, such as (7,4) block codes and (25,20) block codes, can only correct errors in one information symbol during the design and implementation process. However, for information symbols carrying key parameters of a complete frame of data, good decoding performance needs to be guaranteed. Therefore, in the implementation of the decoding algorithm at the receiving end, the number of erroneous symbols corrected by existing block code decoding methods is extremely limited, and it cannot guarantee that the decoded information symbols are completely correct, thus affecting the communication performance of the entire system. Furthermore, existing block code decoding methods use the parity-check matrix and the received data sequence to obtain the syndrome, and then multiply the identity matrix and the transpose of the parity-check matrix to obtain several search values, which are then compared with the syndrome to find the location of the erroneous symbol. This not only involves a huge amount of computation in hardware implementation, consuming a large amount of hardware resources, but also increases the decoding delay, impacting the performance of the entire wireless communication system.

[0029] Based on this, the linear block code encoding and decoding method proposed in this invention improves the encoding efficiency of linear block codes by combining the high-speed parallelism of FPGA. In the hardware implementation of the decoding algorithm, a clever design is made to use the encoded output result as the search value and compare it with the decoding input data to find the error position and correct it. This not only uses the check sequence to correct the errors of multi-bit information symbols, providing a good foundation for the subsequent frame structure parsing, but also saves a lot of hardware resources and reduces decoding latency. At the same time, by combining symbol stuffing, scrambling and other methods, a high-efficiency, low-latency and high-performance block code encoding and decoding architecture is realized on FPGA.

[0030] This invention provides a method for encoding and decoding linear block codes, comprising the following steps:

[0031] S1. The transmitting end encodes the input 3-bit information code element according to the generator matrix to obtain a 36-bit encoded output sequence; wherein, the 36-bit encoded output sequence includes the 3-bit information code element and a 33-bit check code element.

[0032] S2. Perform sign padding on the 36-bit encoded output to expand the 36-bit encoded output into a 96-bit data sequence;

[0033] S3. Scramble the 96-bit data sequence and output the data;

[0034] S4. The receiving end descrambles the received data to obtain the descrambled data.

[0035] S5. Perform data merging processing on the descrambled data to obtain a 36-bit data sequence;

[0036] S6. Decode the 36-bit data sequence to obtain the original SIG data.

[0037] Specifically, this invention designs a (36,3) block code encoder / decoder method for low-power wireless communication systems, with the overall architecture as follows: Figure 1 As shown, the transmitting end includes a (36,3) block code encoding module, a symbol filling module, and a scrambling module. The receiving end includes a descrambling module, a data merging module, and a (36,3) block code decoding module. It mainly performs encoding and decoding processing on the SIG data carrying key parameters of the parsed PHR and PSDU data in a frame of data. The complete frame structure of a frame of data is as follows: Figure 2As shown. At the transmitting end, the input 3-bit information code is first encoded according to the generator matrix to obtain a 36-bit encoded output sequence, including the 3-bit information code before encoding and a 33-bit check code. Then, the 36-bit encoded output is copied to expand it into a 96-bit data sequence. Symbol stuffing allows the signal to reach the receiving end via multiple paths, and these signals are then appropriately combined at the receiving end, resulting in good diversity gain performance and significantly reducing the impact of multipath fading, thus improving transmission reliability. To avoid increasing redundancy and disturbing the signal, the bits of the digital signal are randomly processed to reduce the occurrence of consecutive 0s and 1s, thereby reducing inter-symbol interference and jitter, facilitating clock extraction at the receiving end, and expanding the spectrum of the baseband signal, achieving an encryption effect. Finally, the symbol-stuffed data is XORed with a repeating pseudo-random noise sequence generated by a scrambling polynomial, defined as follows:

[0038] S(x)=x 10 +x 3 +1

[0039] When starting data processing, the initial values ​​of the scrambling polynomial are all set to 1. For each input data point, the scrambling polynomial is shifted left by one bit, and its 3rd and 10th bits are XORed. The output result is then XORed with the input data to obtain the output data. The scrambling implementation flowchart is shown below. Figure 3 As shown. At the receiving end, the received data is first descrambled. Descrambling is the inverse process of scrambling, and the implementation processes are basically similar. Then, the descrambled data is merged to obtain a 36-bit data sequence, which serves as the data input to the block code decoding module. Finally, the original SIG data is decoded using the designed (36,3) block code decoding algorithm. This invention mainly provides specific descriptions of the FPGA implementation methods for the (36,3) linear block code encoding and decoding algorithms.

[0040] (1)(36,3) Design of Linear Block Code Encoder

[0041] (36, 3) The input code group of the linear block code encoder consists of 3 information symbols. Assuming the input information symbol sequence is u = (u0, u1, u2), the encoded output is c = (c0, c1, c2, ... c2). 35 The first 3 bits are information code elements, and the last 33 bits are check code elements obtained by linear operation on the first 3 information code elements. The encoded output can be obtained by matrix operation on c = u·G, and the generated matrix G is a 3×36 matrix, as shown in the following formula:

[0042]

[0043] The correspondence between the encoded output obtained by the operation c = u·G and the original information code is shown in Table 1 below. From this, we can know the minimum Hamming distance d of the (36, 3) block code. min =20, assuming the number of erroneous code elements that need to be corrected is t, according to the formula for the error correction capability of linear block codes d min ≥2t+1 yields that the (36,3) linear block code can correct up to 9 erroneous symbols, demonstrating excellent anti-interference capabilities.

[0044] Table 1 shows the encoded output corresponding to the information code elements.

[0045]

[0046]

[0047] The hardware implementation block diagram of the (36,3) linear block code encoder is shown below. Figure 4 As shown, the data storage module instantiates the 3×36 generator matrix column by column into a ROM. Since the (36,3) linear block code encoder is implemented in the FPGA with serial input and output, the input serial data is first converted into parallel data by a shift register according to the input enable signal. Then, matrix operation is performed with the data read from the ROM to obtain the encoded output. At this time, a counter is set to count so that the encoding operation is performed once every 3 bits of data and the operation result is buffered by cyclic shifting. After 36 encoding operations are completed, the operation result is output serially. Figure 5 The simulation waveform of the (36, 3) linear block code encoder is shown in the figure. The parameters are defined as follows: clk is the system clock input; rst_n is the system reset input signal, active low; u0 is the 3 serial input information symbols; u[2:0] is the parallel input data after conversion; G[2:0] is the output of the generator matrix; cnt3[1:0] is a counter used to indicate that the generator matrix stored in ROM encodes once every 3 bits of data output; cnt[6:0] is a counter used to indicate the number of encoding times. When the count reaches 37, it indicates that the encoding is complete and the encoding output begins; c_out[35:0] is the 36 symbols of the parallel output of the linear block code encoding; c is the single-bit serial output symbol of the linear block code encoding, which is output sequentially from the low bit to the high bit of c_out[35:0]; ecode_rdy is the output enable signal. From the simulation waveform of the (36,3) linear block code encoder, it can be seen that when the input enable signal is valid, the input SIG data is "001", and the code sequence output after the encoder encoding operation is "001111001000101110101011110100101110". Verification shows that the encoding output result is correct.

[0048] (2)(36,3) Design of Linear Block Code Decoder

[0049] Assume the transmitted codeword is c = (c0, c1, c2, ... c 35 The received symbol sequence is Y = (y0, y1, y2, ..., y). 35 During codeword transmission, the erroneous pattern generated by factors such as channel noise interference is e = (e0, e1, e2, ..., e...). 35 Then, we can obtain Y = c + e. The generator matrix G has already been given above, so the parity check matrix H can be obtained from the generator matrix. Thus, the syndrome expression is as follows, which indicates whether an error has occurred in the codeword during transmission:

[0050] S = YH T =(c+e)H T =cH T +eH T

[0051] From cH T =0 yields:

[0052] S = YH T =eH T

[0053] Therefore, when the syndrome S = YH T =0, then the error pattern e=0, which indicates that there is no error in the received symbol sequence. However, when the syndrome S=YH T If e ≠ 0, then the incorrect pattern e ≠ 0, where e i =1 indicates that the i-th bit of the received symbol sequence has a decoding error. Therefore, we can determine the error location of the received symbol sequence and correct it through the error pattern. The corrected codeword is: In the design and implementation of a conventional linear block code decoder, the first step is to obtain e = S(H T ) -1 The error pattern is obtained, and then error detection and correction are performed based on the error pattern and the received symbol sequence. However, in actual hardware implementation, finding the pseudo-inverse of a non-full-rank matrix is ​​a very complex and difficult process, and it wastes a lot of hardware resources. To simplify the decoding process as much as possible and save hardware resources while ensuring good decoding performance, the decoding block diagram of the (36,3) linear block code is designed as follows: Figure 6 As shown, it mainly consists of seven modules: data storage, shift buffer, search value calculation, number of search error symbols, minimum value calculation, result judgment, and serial output.

[0054] The decoding process is as follows:

[0055] (1) Data storage: The encoded output results are obtained according to c = u·G, as shown in Table 1 above. Since the original information code element is 111, it is a reserved bit and does not carry any useful information, so it does not need to be considered. Here, 7 registers are used to store the correct encoded output results respectively.

[0056] (2) Shift buffer: In order to facilitate the next step of the operation, the input serial data is converted into 36 bits of parallel data through shift register and counter.

[0057] (3) Find the search value: Perform an XOR operation on the received 36-bit symbol sequence and the correct encoded output stored in the register to obtain multiple search values.

[0058] (4) Search for the number of error symbols: Use multiple counters to count the number of "1"s in the output of the above XOR operation, and store the values ​​of each counter to obtain the number of error symbols.

[0059] (5) Minimum value calculation: By using the parallelism of the FPGA, the values ​​of each counter are compared pairwise to obtain the minimum value of the counter. This minimum value is the actual number of error symbols.

[0060] (6) Result judgment: The correct decoding output can be obtained by making a judgment based on the minimum value of the counter calculated above.

[0061] (7) Serial output: In order to facilitate the related calculations of subsequent modules, the decoded results are output serially.

[0062] Figure 7The simulation waveform for the (36, 3) linear block code decoder is shown below. decode_in[35:0] is the decoder input sequence at the receiver, valid_in is the input enable signal, sig_encode_reg1[35:0],…, sig_encode_reg7[35:0] are the various possible encoded output results stored in the registers, and compare_reg1[35:0],…, compare_reg7[35:0] are the results of XOR operations between the decoder input and each possible encoded output result. The comparison values ​​are calculated separately for each. The number of "1"s in _reg1[35:0],…,compare_reg7[35:0] is used to obtain cnt1[5:0],…,cnt7[5:0]. Then, pairwise comparisons are performed on cnt1[5:0],…,cnt7[5:0] to obtain the minimum count value min_cnt[5:0] within three clock cycles. Finally, a case statement is called to match min_cnt[5:0] with cnt1[5:0],…,cnt7[5:0] to obtain the correct decoded output result decode_dout[3:0]. From the simulation waveform of the (36,3) linear block code decoder, it can be seen that from the input enable signal valid_in=1 when the decoded input sequence is input into the decoder to the generation of the decoded output result when valid_out=1, a total of 7 clock cycles are used. This shows that the decoding process can be completed within 7 clock cycles. Suppose the correct encoding output of the encoder at the transmitting end is "011010011111011101101100111000010100011", but during channel transmission, due to interference, noise, and other factors, the transmitted symbols are incorrect. Figure 7 It can be seen that when the input enable signal valid_in is valid, the actual decoded input sequence decode_in[35:0] received at the receiver is “100010011011011101100111001010100010”. min_cnt[5:0] = 6 indicates that there are 6 erroneous code elements in the decoded input sequence, which can be analyzed to include 3 information code elements and 3 check code elements. After the designed (36,3) linear block code decoder, the check code elements are used to correct the erroneous information code elements, and the correct decoded output result decode_dout[3:0] is “011”. Therefore, it can be concluded that the (36,3) linear block code decoder can completely obtain the correct decoded output result even when there are 6 erroneous information code elements.

[0063] In summary, 1) this invention combines the (36,3) linear block code encoding and decoding method with symbol stuffing, scrambling and other methods to provide a channel encoding and decoding design method with excellent decoding performance, and gives a specific implementation method for FPGA;

[0064] 2) This invention utilizes the high-speed parallelism of FPGA to design a (36,3) linear block code encoder and adopts pipeline technology, which greatly improves the coding efficiency;

[0065] 3) In the design process of the (36,3) linear block code decoder, the present invention makes full use of the check code element, so that the (36,3) linear block code decoder has good error correction capability for the decoded input sequence;

[0066] 4) This invention improves the hardware implementation method of the (36,3) linear block code decoder. It proposes to store the encoded output result in a register and then compare it with the decoding input sequence to count the number of erroneous code elements to obtain the correct decoded output. This method not only ensures decoding performance but also reduces decoding delay and saves hardware resources.

[0067] In addition, this invention provides a (36,3) block code encoding and decoding design method applicable to wireless communication systems, and improves the reliability of signal transmission by combining symbol stuffing, scrambling and other methods. The basic idea of ​​this design method can also be applied to other (n,k) block code encoding and decoding designs to achieve the purpose of the invention.

[0068] refer to Figure 8 Another embodiment of this application provides an electronic device, including: at least one processor 110; and a memory 111 communicatively connected to the at least one processor; wherein the memory 111 stores instructions executable by the at least one processor 110, the instructions being executed by the at least one processor 110 to enable the at least one processor 110 to perform any of the above method embodiments.

[0069] The memory 111 and processor 110 are connected via a bus, which may include any number of interconnecting buses and bridges, connecting various circuits of one or more processors 110 and memory 111. The bus may also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver may be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by processor 110 is transmitted over a wireless medium via an antenna, which further receives data and transmits it to processor 110.

[0070] Processor 110 is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory 111 can be used to store data used by processor 110 during operation.

[0071] Another embodiment of this application relates to a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the method embodiments described above.

[0072] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0073] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for encoding and decoding linear block codes, characterized in that, Includes the following steps: The transmitting end encodes the input 3-bit information code element according to the generator matrix to obtain a 36-bit encoded output sequence; wherein, the 36-bit encoded output sequence includes the 3-bit information code element and a 33-bit check code element; The 36-bit encoded output is sign-padded to expand it into a 96-bit data sequence. The 96-bit data sequence is scrambled and the data is output. The receiving end descrambles the received data to obtain the descrambled data. The descrambled data is then merged to obtain a 36-bit data sequence. The 36-bit data sequence is decoded to obtain the original SIG data; The decoding process also includes: according to Obtain the encoded output result; The input serial data is converted into 36 bits of parallel data using a shift register and a counter. The received 36-bit symbol sequence and the correctly encoded output stored in the register are XORed to obtain multiple search values; The number of 1s in the output of the XOR operation is counted using multiple counters, and the values ​​of each counter are stored to obtain the number of error symbols. By using the parallelism of the FPGA, the values ​​of each counter are compared pairwise to obtain the minimum value of the counter; The correct decoded output is obtained based on the minimum value of the counter; The decoded results are output serially.

2. The linear block code encoding and decoding method according to claim 1, characterized in that, The step of encoding the input 3-bit information code elements according to the generator matrix at the transmitting end to obtain a 36-bit encoded output sequence includes: The formula for the generating matrix is: ; The input information symbol sequence is: A 3×36 matrix G is generated. This matrix is ​​then instantiated column-by-column into a ROM. A counter is set to count the bits, performing an encoding operation every 3 bits of data. The result of the operation is buffered using a circular shift method. After 36 encoding operations, the result is output serially, yielding the encoded output. The first 3 bits of the encoded output are information code elements, and the last 33 bits are the check code elements obtained by linear operation of the first 3 information code elements.

3. The linear block code encoding and decoding method according to claim 1, characterized in that, The step of performing sign padding on the 36-bit encoded output to expand it into a 96-bit data sequence includes: The 36-bit encoded output is copied to expand it into a 96-bit data sequence.

4. The linear block code encoding and decoding method according to claim 1, characterized in that, The step of scrambling the 96-bit data sequence and outputting the data includes: The 96-bit data sequence is XORed with a repeating pseudo-random noise sequence generated by a scrambling polynomial to obtain the data and output it; wherein, the scrambling polynomial is: ; The steps of descrambling the received data at the receiving end to obtain the descrambled data include: The 96-bit data sequence is XORed with a descrambling polynomial to recover the original data and output it. The descrambling polynomial is consistent with the scrambling code polynomial.

5. The linear block code encoding and decoding method according to claim 1, characterized in that, The decoding process includes: The parity-check matrix H is obtained from the generator matrix, and the adjoint equation is: ； Depend on get: ； The codeword sent is The received symbol sequence is Error patterns caused by channel noise interference during codeword transmission are as follows: Then we get ; When the concomitant Then the error pattern This indicates that there are no errors in the received symbol sequence; When the concomitant Then the error pattern ,in This indicates that the i-th bit of the received code sequence has a decoding error, and the corrected codeword is... .

6. A linear block code encoding and decoding system, characterized in that, The system includes a transmitter and a receiver. The transmitter includes a block code encoding module, a symbol filling module, and a scrambling module. The block code encoding module is used to encode the input 3-bit information code elements according to the generator matrix to obtain a 36-bit encoded output sequence. The symbol padding module is used to perform symbol padding on the 36-bit encoded output, expanding the 36-bit encoded output into a 96-bit data sequence; The scrambling module is used to scramble the 96-bit data sequence and output the data; The receiving end includes a descrambling module, a data merging module, and a block code decoding module; The descrambling module is used to descramble the received data to obtain descrambled data; The data merging module is used to perform data merging processing on the descrambled data to obtain a 36-bit data sequence. The block code decoding module is used to decode the 36-bit data sequence to obtain the original SIG data; The block code decoding module includes a data storage unit, a shift buffer unit, a search value calculation unit, a search error code number unit, a minimum value calculation unit, a result decision unit, and a serial output unit. The data storage unit is used to... Obtain the encoded output result; The shift buffer unit is used to convert the input serial data into 36 bits of parallel data through a shift register and a counter; The search value unit is used to perform an XOR operation on the received 36-bit symbol sequence and the correct encoded output stored in the register to obtain multiple search values. The error code element counting unit is used to count the number of 1s in the output result of the XOR operation using multiple counters, and store the values ​​of each counter to obtain the number of error code elements. The minimum value calculation unit is used to compare the values ​​of each counter pairwise using the parallelism of the FPGA to obtain the minimum value of the counter. The result decision unit is used to obtain the correct decoding output based on the minimum value of the counter; The serial output unit is used to serially output the obtained decoding results.

7. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the linear block code encoding and decoding method as described in any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the linear block code encoding and decoding method according to any one of claims 1 to 5.

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