A dynamic signal modulation method for reducing data transmission

Abstract

This invention proposes a dynamic signal modulation method to reduce data transmission volume, comprising the following steps: S1, generating a high-frequency digital small signal, the frequency of which is half the sampling frequency of the dynamic signal analyzer; S2, modulating the high-frequency digital small signal and the normal channel acquisition signal of the dynamic signal analyzer to obtain a modulated signal; S3, performing AD sampling, processing, and transmission on the modulated signal, and waiting for a sufficient amount of data to be buffered before proceeding to S4; S4, performing digital filtering on the buffered data to obtain digitally filtered data. This invention significantly reduces the amount of communication data with negligible dynamic range performance loss under the same sampling rate and number of channels.

Description

Technical Field

[0001] This invention relates to the field of dynamic signal technology, and in particular to a dynamic signal modulation method for reducing data transmission volume. Background Technology

[0002] Dynamic signal analyzers are widely used in the monitoring and analysis of various physical quantities. Because physical quantities vary widely, most dynamic signal analyzers are equipped with multiple ranges to meet measurement needs. However, since range switching can cause data fluctuations, for single measurements requiring a wide range, the analyzer's single-range range needs to be sufficiently large. A large single-range requires a higher sampling bit depth, thus increasing the workload of data transmission, storage, and computation.

[0003] The number of bits in an AD (digital-to-analog converter) determines the theoretical single-range dynamic range of a dynamic signal analyzer. The theoretical dynamic range of a 16-bit AD is 20 * log(2π / 2). 16 -1)≈96(dB), the theoretical dynamic range of a 24-bit ADC is 20*log(2 24 -1)≈144(dB). Therefore, in order to obtain a large single-range dynamic range, a high-bit AD converter is required.

[0004] The raw data acquired by the dynamic signal analyzer needs to be transmitted to a PC for analysis. The data transmission volume is: AD bit depth * sampling rate * number of channels. When the dynamic signal analyzer has a large number of channels and a high sampling rate, its data transmission volume is extremely high.

[0005] A. According to the Nyquist theorem, the analysis frequency < sampling frequency / 2; reducing the sampling frequency will lower the upper limit of the analysis frequency of the dynamic signal analyzer.

[0006] B. Multi-channel measurements are often used in modal analysis, sound source localization, and other fields, and can have dozens to hundreds of channels. Reducing the number of channels will lead to a decrease in application accuracy.

[0007] Current technologies primarily address the high data volume problem by increasing communication bandwidth and hardware performance, adjusting sampling rates, and using multiple devices for separate measurements.

[0008] High data transfer volumes present three main challenges for applications:

[0009] 1. High bandwidth requirements are needed. Hardware supporting higher bandwidth is required, such as upgrading from 100 Mbps to 1 Gbps; this will increase hardware costs, but more importantly, it will reduce the versatility of the equipment.

[0010] 2. Increased pressure on data parsing. All received data needs to be re-parsed into AD sampling data, and large data volumes will increase the parsing load.

[0011] 3. Larger storage capacity is required. Summary of the Invention

[0012] This invention addresses the problems of high hardware costs and heavy data parsing pressure in existing technologies by proposing a dynamic signal modulation method to reduce data transmission volume. Under the same sampling rate and number of channels, it significantly reduces the amount of communication data through negligible dynamic range performance loss.

[0013] To achieve the above objectives, the following technical solution is proposed:

[0014] A dynamic signal modulation method for reducing data transmission volume includes the following steps:

[0015] S1, Generate a high-frequency digital small signal, wherein the frequency of the high-frequency digital small signal is half the sampling frequency of the dynamic signal analyzer;

[0016] S2, the modulated signal is obtained by modulating the high-frequency digital small signal and the normal channel acquisition signal of the dynamic signal analyzer;

[0017] S3, perform AD sampling, processing and transmission on the modulated signal, and wait for a sufficient amount of data to be buffered before proceeding to S4;

[0018] S4 performs digital filtering on the cached data to obtain the digitally filtered data.

[0019] This invention modulates a normal test signal into a high-frequency small signal, biasing the analog data before AD conversion onto a known background signal. The amplitude of the modulated high-frequency signal is greater than the amplitude range represented by the lower 8 bits of the AD converter, causing the signal originally acquired only in the lower 8 bits to be included in the higher 16 bits; thus, the maximum input voltage is reduced. Since the amplitude range represented by the lower 8 bits is small, typically in the μV range, the reduction in the maximum input voltage is negligible. The higher 16 bits of data after AD conversion are selected for transmission, and then filtered to eliminate the modulated high-frequency signal, achieving the original 24-bit measurement dynamic range. This invention ensures the measurement dynamic range and reduces the data transmission rate through high-frequency small-signal modulation.

[0020] Preferably, step S1 specifically includes the following steps:

[0021] S101, set the frequency of the high-frequency small signal to half of the sampling frequency of the dynamic signal analyzer;

[0022] S102 generates a high-frequency master clock through the FPGA's PLL, counts the rising edges of the master clock, and generates an output clock when the corresponding multiplication factor is reached.

[0023] S103 connects the required clock signal to the FPGA's IO pin for clock output;

[0024] S104 uses a processing circuit to filter and attenuate the clock output signal to obtain an approximately sinusoidal signal.

[0025] Because the dynamic signal analyzer's circuitry includes a low-pass anti-aliasing filter, signals above the analysis frequency are rapidly attenuated and filtered out; while lower frequency signals enter the analyzer's frequency analysis range. Therefore, the frequency of the high-frequency small signal is set to half the sampling frequency. At this point, the digital clock of the AD signal can be used to directly divide the frequency to obtain the required high-frequency signal components, thereby reducing the computational power required for signal calculation.

[0026] In this invention, a high-frequency master clock is generated by the PLL of the FPGA. The rising edges of the master clock are counted, and when the corresponding multiplication factor is reached, an output clock is generated, thereby realizing the digital generation of clocks with various multiplication factors. The required clock signal is then linked to the FPGA's I / O pins to achieve clock output. The clock signal directly generated by the FPGA is a square wave signal with a relatively large amplitude. Before being modulated with the acquired signal, it needs to be filtered and attenuated to obtain a small, approximately sinusoidal signal.

[0027] Preferably, the processing circuit includes an operational amplifier U89B, resistors R769 and R770, and a capacitor C429. One end of the capacitor C429 is connected to the IO pin of the FPGA, and the other end of the capacitor C429 is connected to one end of resistor R769. The other end of resistor R769 and one end of resistor R770 are connected in parallel to the non-inverting input of operational amplifier U89B, and the other end of resistor R770 is connected to signal ground. The inverting input and signal output of operational amplifier U89B are connected in parallel as the output of a high-frequency digital small signal.

[0028] In this invention, Vout is connected to the FPGA clock output; C249, R769, R770, and U89B form an active high-pass filter amplifier circuit. By adjusting the resistors and capacitors, on the one hand, the output signal of the high-frequency digital small signal is made to be approximately 1mV, covering the measurement range of the lower 8 bits of the AD converter, while ensuring that the upper limit of the measurement is reduced to a negligible level; on the other hand, low-frequency interference signals are filtered out to ensure that the entire circuit has a good noise floor; through operational amplifier buffering, the load-carrying capacity of the high-frequency digital small signal is increased to drive the multi-channel modulation circuit of the back-end analyzer.

[0029] Preferably, step S2 specifically includes the following steps:

[0030] An adder is used to modulate the high-frequency digital small signal and the normal channel acquisition signal of the dynamic signal analyzer to generate a modulated signal. The adder includes an operational amplifier U19B, resistors R23, R24, and R25, and a coupling capacitor C489. One end of resistor R23, one end of resistor R24, and one end of resistor R25 are connected in parallel to the non-inverting input of operational amplifier U19B. The inverting input and signal output of operational amplifier U19B are connected in parallel as the modulated signal output. The other end of resistor R23 is connected to the output of the high-frequency digital small signal. The other end of resistor R24 ​​is connected to the normal channel acquisition signal output of the dynamic signal analyzer through coupling capacitor C489. The other end of resistor R25 is connected to signal ground.

[0031] In this invention, coupling capacitor C489 is used to isolate the front-end DC voltage, and R23, R24, R25 and U19B form an adder to achieve signal modulation. The modulated signal is output through the modulation signal output terminal CH1_OUT.

[0032] Preferably, step S3 specifically includes the following steps:

[0033] Data acquisition is achieved by using an FPGA in conjunction with an AD converter. The FPGA generates the clock signal and control signal required for the AD converter to operate. After the measurement is started, the AD converter serially sends the bit data of a single sample on each bit clock rising edge. The FPGA reads the data synchronously. After receiving 24 bits of sample data, it buffers the data and waits for it to be sent.

[0034] Before sending, the cached AD data is packaged, and after the data is filled, it is sent to the designated PC address through the network port;

[0035] After receiving data from the front end of the dynamic signal analyzer, the PC establishes a buffer to cache the data. Once enough data has been cached, it triggers subsequent analysis.

[0036] Preferably, the digital filtering includes two methods: one is to directly perform spectrum analysis; the other is to first perform low-pass filtering on the signal to filter out high-frequency signals, and then perform subsequent analysis.

[0037] Because the received data contains high-frequency modulated signal components, without processing, it's equivalent to artificially adding high background noise. Therefore, digital filtering is necessary before use. One approach is to directly perform spectrum analysis, such as FFT analysis, to separate the signal's frequency components and discard the high-frequency modulated signal portion during use. Another approach is to first perform a low-pass filter to remove the high-frequency signal before proceeding with subsequent analysis. The first method is suitable when only spectrum analysis is required; however, if multiple subsequent analysis functions are needed, the second method should be chosen, performing a unified filter on the data before further analysis to save computational resources.

[0038] Preferably, for the second method, a 4th-order FIR filter is used, and its system function is:

[0039] ;

[0040] Where z -1 This represents a unit delay unit, where n is the filter order. For specific filter implementations, please refer to the documentation for the fdatool toolkit in MATLAB.

[0041] The beneficial effects of this invention are: by using high-frequency small-signal modulation, this invention ensures the dynamic range of measurement and reduces the data transmission rate. Attached Figure Description

[0042] Figure 1 This is a flowchart of the method in an embodiment;

[0043] Figure 2 This is a topology diagram of the processing circuit in the embodiment;

[0044] Figure 3 This is a topology diagram of the adder in the embodiment;

[0045] Figure 4 It is the time-domain waveform of a high-frequency modulated small signal;

[0046] Figure 5 It is the time-domain waveform of a 1.6kHz signal modulated to a high-frequency signal. Detailed Implementation

[0047] Example:

[0048] This embodiment modulates the normal test signal with a high-frequency small signal, biasing the analog data before AD conversion onto a known background signal. The amplitude of the modulated high-frequency signal is greater than the amplitude range represented by the lower 8 bits of the AD converter, causing the signal originally acquired only in the lower 8 bits of the AD converter to enter the higher 16 bits; while the maximum input voltage is reduced. Since the amplitude range represented by the lower 8 bits is small, typically in the μV range, the reduction in the maximum input voltage is negligible. The higher 16 bits of data after AD conversion are selected for transmission, and then filtered to eliminate the modulated high-frequency signal, achieving the original 24-bit measurement dynamic range. This invention ensures the measurement dynamic range and reduces the data transmission rate through high-frequency small-signal modulation.

[0049] This embodiment proposes a dynamic signal modulation method to reduce data transmission volume, referencing... Figure 1 This includes the following steps:

[0050] S1 generates a high-frequency digital small signal, the frequency of which is half the sampling frequency of the dynamic signal analyzer;

[0051] S1 specifically includes the following steps:

[0052] S101, set the frequency of the high-frequency small signal to half of the sampling frequency of the dynamic signal analyzer;

[0053] S102 generates a high-frequency master clock through the FPGA's PLL, counts the rising edges of the master clock, and generates an output clock when the corresponding multiplication factor is reached.

[0054] S103 connects the required clock signal to the FPGA's IO pin for clock output;

[0055] S104 uses a processing circuit to filter and attenuate the clock output signal to obtain an approximately sinusoidal signal.

[0056] Because the dynamic signal analyzer's circuitry includes a low-pass anti-aliasing filter, signals above the analysis frequency are rapidly attenuated and filtered out; while lower frequency signals enter the analyzer's frequency analysis range. Therefore, the frequency of the high-frequency small signal is set to half the sampling frequency. At this point, the digital clock of the AD signal can be used to directly divide the frequency to obtain the required high-frequency signal components, thereby reducing the computational power required for signal calculation.

[0057] In this invention, a high-frequency master clock is generated by the PLL of the FPGA. The rising edges of the master clock are counted, and when the corresponding multiplication factor is reached, an output clock is generated, thereby realizing the digital generation of clocks with various multiplication factors. The required clock signal is then linked to the FPGA's I / O pins to achieve clock output. The clock signal directly generated by the FPGA is a square wave signal with a relatively large amplitude. Before being modulated with the acquired signal, it needs to be filtered and attenuated to obtain a small, approximately sinusoidal signal.

[0058] refer to Figure 2 The processing circuit includes an operational amplifier U89B, resistors R769 and R770, and capacitor C429. One end of capacitor C429 is connected to the IO pin of the FPGA, and the other end of capacitor C429 is connected to one end of resistor R769. The other end of resistor R769 and one end of resistor R770 are connected in parallel to the non-inverting input of operational amplifier U89B. The other end of resistor R770 is connected to signal ground. The inverting input and signal output of operational amplifier U89B are connected in parallel as the output of a high-frequency digital small signal.

[0059] In this invention, Vout is connected to the FPGA clock output; C249, R769, R770, and U89B form an active high-pass filter amplifier circuit. By adjusting the resistors and capacitors, on the one hand, the output signal of the high-frequency digital small signal is made to be approximately 1mV, covering the measurement range of the lower 8 bits of the AD converter, while ensuring that the upper limit of the measurement is reduced to a negligible level; on the other hand, low-frequency interference signals are filtered out to ensure that the entire circuit has a good noise floor; through operational amplifier buffering, the load-carrying capacity of the high-frequency digital small signal is increased to drive the multi-channel modulation circuit of the back-end analyzer.

[0060] S2, modulating the high-frequency digital small signal and the normal channel acquisition signal of the dynamic signal analyzer to obtain the modulated signal; S2 specifically includes the following steps:

[0061] The modulated signal is generated by modulating the high-frequency digital small signal and the normal channel acquisition signal of the dynamic signal analyzer using an adder, and referenced... Figure 3 The adder includes an operational amplifier U19B, resistors R23, R24, and R25, and a coupling capacitor C489. One end of resistor R23, one end of resistor R24, and one end of resistor R25 are connected in parallel to the non-inverting input of operational amplifier U19B. The inverting input and signal output of operational amplifier U19B are connected in parallel as the modulation signal output. The other end of resistor R23 is connected to the high-frequency digital small signal output. The other end of resistor R24 ​​is connected to the normal channel acquisition signal output of the dynamic signal analyzer through coupling capacitor C489. The other end of resistor R25 is connected to signal ground.

[0062] In this invention, coupling capacitor C489 is used to isolate the front-end DC voltage. R23, R24, R25, and U19B form an adder to achieve signal modulation. The modulated signal is output through the modulated signal output terminal CH1_OUT. See the reference for the effect before and after modulation. Figure 4 and Figure 5 .

[0063] S3 involves AD sampling, processing, and transmission of the modulated signal. After buffering sufficient data, proceed to S4. S3 specifically includes the following steps:

[0064] Data acquisition is achieved by using an FPGA in conjunction with an AD converter. The FPGA generates the clock signal and control signal required for the AD converter to operate. After the measurement is started, the AD converter serially sends the bit data of a single sample on each bit clock rising edge. The FPGA reads the data synchronously. After receiving 24 bits of sample data, it buffers the data and waits for it to be sent.

[0065] Before sending, the cached AD data is packaged, and after the data is filled, it is sent to the designated PC address through the network port;

[0066] After receiving data from the front end of the dynamic signal analyzer, the PC establishes a buffer to cache the data. Once enough data has been cached, it triggers subsequent analysis.

[0067] S4 performs digital filtering on the cached data to obtain the digitally filtered data.

[0068] Digital filtering includes two methods: one is to directly perform spectrum analysis; the other is to first perform low-pass filtering on the signal to remove high-frequency signals, and then perform subsequent analysis.

[0069] Because the received data contains high-frequency modulated signal components, without processing, it's equivalent to artificially adding high background noise. Therefore, digital filtering is necessary before use. One approach is to directly perform spectrum analysis, such as FFT analysis, to separate the signal's frequency components and discard the high-frequency modulated signal portion during use. Another approach is to first perform a low-pass filter to remove the high-frequency signal before proceeding with subsequent analysis. The first method is suitable when only spectrum analysis is required; however, if multiple subsequent analysis functions are needed, the second method should be chosen, performing a unified filter on the data before further analysis to save computational resources.

[0070] For method two, a 4th-order FIR filter is used, and its system function is:

[0071] ;

[0072] Where z -1 This represents a unit delay unit, where n is the filter order. For specific filter implementations, please refer to the documentation for the fdatool toolkit in MATLAB.

[0073] Finally, this implementation presents a data analysis example:

[0074] The digitally filtered data can be processed using conventional digital signal processing methods. The performance of unprocessed 24-bit data transmission, unmodulated 16-bit data transmission, data transmission processed using this method, and conventional 16-bit ADC is compared in the table below:

[0075] Serial Number Data format Linear range Dynamic range 1 Raw 24-bit transmission 93dB 102dB 2 Unmodulated 16-bit truncation 70dB 103dB 3 This plan is excerpted. 86dB 92dB 4 Standard 16-bit AD 74dB 80dB

[0076] The original 24-bit transmission has the best linear and dynamic range; the data transmission with 16-bit truncation without signal modulation is equivalent to directly removing the background, which has a higher dynamic range, but its actual usable linear range is greatly reduced; the data processed by this scheme inevitably introduces noise due to modulation, and its dynamic and linear range is lower than that of the original 24-bit transmission, but both are much greater than the conventional 16-bit AD performance.

Claims

1. A dynamic signal modulation method for reducing the amount of data transmission, characterized by, Includes the following steps: S1, Generate a high-frequency digital small signal, wherein the frequency of the high-frequency digital small signal is half the sampling frequency of the dynamic signal analyzer; S2, using an adder to modulate a high-frequency digital small signal and a normal channel acquisition signal from a dynamic signal analyzer to obtain a modulated signal; modulating the normal test signal into a high-frequency small signal, so that the analog data before AD conversion is biased onto a known background signal; S3: Perform AD sampling, processing, and transmission on the modulated signal; the amplitude of the modulated high-frequency signal is greater than the amplitude range represented by the lower 8 bits of the AD, so that the signal originally sampled only in the lower 8 bits of the AD enters the higher 16 bits; select to transmit the higher 16 bits of data after AD conversion; establish a buffer for buffering, and wait for a sufficient amount of data to be buffered before proceeding to S4; S4 performs digital filtering on the cached data to obtain the digitally filtered data.

2. The dynamic signal modulation method for reducing data transmission volume according to claim 1, characterized in that, S1 specifically includes the following steps: S101, set the frequency of the high-frequency small signal to half of the sampling frequency of the dynamic signal analyzer; S102 generates a high-frequency master clock through the FPGA's PLL, counts the rising edges of the master clock, and generates an output clock when the corresponding multiplication factor is reached. S103 connects the required clock signal to the FPGA's IO pin for clock output; S104 uses a processing circuit to filter and attenuate the clock output signal to obtain an approximately sinusoidal signal.

3. The method of claim 2, wherein the data transmission amount is reduced by modulating the dynamic signal. The processing circuit includes an operational amplifier U89B, resistors R769 and R770, and a capacitor C429. One end of capacitor C429 is connected to the IO pin of the FPGA, and the other end of capacitor C429 is connected to one end of resistor R769. The other end of resistor R769 and one end of resistor R770 are connected in parallel to the non-inverting input of operational amplifier U89B. The other end of resistor R770 is connected to signal ground. The inverting input and signal output of operational amplifier U89B are connected in parallel as the output of a high-frequency digital small signal.

4. The dynamic signal modulation method for reducing data transmission volume according to claim 3, characterized in that, S2 specifically includes the following steps: An adder is used to modulate the high-frequency digital small signal and the normal channel acquisition signal of the dynamic signal analyzer to generate a modulated signal. The adder includes an operational amplifier U19B, resistors R23, R24, and R25, and a coupling capacitor C489. One end of resistor R23, one end of resistor R24, and one end of resistor R25 are connected in parallel to the non-inverting input of operational amplifier U19B. The inverting input and signal output of operational amplifier U19B are connected in parallel as the modulated signal output. The other end of resistor R23 is connected to the output of the high-frequency digital small signal. The other end of resistor R24 ​​is connected to the normal channel acquisition signal output of the dynamic signal analyzer through coupling capacitor C489. The other end of resistor R25 is connected to signal ground.

5. The dynamic signal modulation method for reducing data transmission volume according to claim 1, characterized in that, S3 specifically includes the following steps: Data acquisition is achieved by using an FPGA in conjunction with an AD converter. The FPGA generates the clock signal and control signal required for the AD converter to operate. After the measurement is started, the AD converter serially sends the bit data of a single sample on each bit clock rising edge. The FPGA reads the data synchronously. After receiving 24 bits of sample data, it buffers the data and waits for it to be sent. Before sending, the cached AD data is packaged, and after the data is filled, it is sent to the designated PC address through the network port; After receiving data from the front end of the dynamic signal analyzer, the PC establishes a buffer to cache the data. Once enough data has been cached, it triggers subsequent analysis.

6. The dynamic signal modulation method for reducing data transmission volume according to claim 1, characterized in that, The digital filtering includes two methods: one is to directly perform spectrum analysis; the other is to first perform low-pass filtering on the signal to remove high-frequency signals, and then perform subsequent analysis.

7. A dynamic signal modulation method for reducing data transmission volume according to claim 6, characterized in that, For the second method, a fourth-order FIR filter is used.

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