A flash memory and a method of manufacturing the same
By employing an upper and lower bit structure of select gate and erase gate and vertical shallow trench isolation in flash memory, the problem of large memory cell area is solved, low operating voltage and high reliability are achieved, and the needs of small-size integrated circuits are met.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2023-04-27
- Publication Date
- 2026-07-21
AI Technical Summary
Existing discrete gate flash memory structures occupy a large area of memory cells in small-size integrated circuits, and the programming and erasing voltages have not decreased as the memory cell size shrinks.
The select gate is located in the first trench within the semiconductor substrate, and the erase gate is located on the semiconductor surface to form an upper and lower structure. By forming a shallow trench isolation structure in the vertical direction, the area occupied by the memory cell is reduced. At the same time, the resistance is reduced by using the PN junction, thus lowering the erase voltage.
It achieves low operating voltage and high reliability flash memory, suitable for small-size integrated circuits, reduces the storage cell footprint and shields against channel current degradation caused by high-voltage erase operations.
Smart Images
Figure CN116390489B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a flash memory and its fabrication method. Background Technology
[0002] Flash memory comprises a MOSFET having one or more floating gates (FGs) between a control gate (CG) and a channel region, wherein the FG and CG are isolated by a dielectric layer. As semiconductor manufacturing technology has improved, the size of the FG has gradually shrunk. However, while the size of the memory cell has decreased, the voltage required for programming and erasing the memory cell has not decreased to the same extent.
[0003] Therefore, to reduce programming and erasing voltages, a common solution is to use an additional erase gate, resulting in a split-gate flash memory structure where the memory cell includes an erase gate EG, a select gate SG, a control gate CG, and a floating gate FG. Because the split-gate flash memory structure with a select gate SG and an erase gate EG offers advantages such as high reliability, good manufacturing process compatibility, lower startup voltage, and prevention of over-erasure, it is widely used as an embedded flash memory.
[0004] However, the split-gate flash memory structure integrating the erase gate EG and the select gate SG has advantages such as lower startup voltage and prevention of over-erasure. However, since the erase gate EG and the select gate SG are formed on the surface of the substrate and on both sides and between the floating gate FG and the control gate CG of the split-gate memory cell, the memory cells in the existing split-gate flash memory devices will inevitably have a large memory cell area, which means that they cannot be applied to small-size integrated circuits where the size of the FG is also gradually decreasing. Summary of the Invention
[0005] The purpose of this invention is to provide a novel flash memory structure and its fabrication method, so that the novel flash memory can have low operating voltage and high reliability, while also reducing the area of the wafer occupied by the memory cells, thus adapting to the purpose of small-size integrated circuits with gradually shrinking dimensions.
[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for manufacturing a flash memory, which may include at least the following steps:
[0007] A semiconductor substrate is provided, wherein a gate oxide layer, a floating gate layer, and a sacrificial layer are stacked sequentially from bottom to top on the surface of a first side of the semiconductor substrate, and a shallow trench isolation structure disposed along a first direction is formed in the sacrificial layer, the floating gate layer, the gate oxide layer, and a portion of the semiconductor substrate.
[0008] Rotate the semiconductor substrate formed with the shallow trench isolation structure to a second direction, and etch the semiconductor substrate again to form a first trench disposed along the second direction in the sacrificial layer, floating gate layer, gate oxide layer, and a part of the semiconductor substrate, wherein the first direction is perpendicular to the second direction;
[0009] Form a select gate dielectric layer and a select gate layer. The select gate dielectric layer at least covers the inner surface of the lower space of the first trench, and the select gate layer at least fills the lower space of the first trench to form a select gate in a part of the first trench located in the semiconductor substrate;
[0010] Perform a first ion implantation process on the semiconductor substrate to respectively form a first ion implantation region in the semiconductor substrate on both sides of the first trench. The conductivity type of the first ion implantation region is opposite to that of the semiconductor substrate;
[0011] Form an erase gate dielectric layer and an erase gate layer. The erase gate dielectric layer covers the top surface of the select gate and the inner wall of a second trench surrounded by the floating gate layer, sacrificial layer, and the top surface of the select gate exposed by the remaining space of the first trench. The erase gate layer fills the second trench to form an erase gate on the semiconductor substrate;
[0012] Perform subsequent processes on the semiconductor substrate to form a control gate layer covering the surface of the floating gate layer and source electrodes in the semiconductor substrate on both sides of the stacked floating gate layer and control gate layer.
[0013] Further, the ions implanted in the first ion implantation region can be N-type ions.
[0014] Further, the trench pitch between the second trench and the first trench is the same in the second direction.
[0015] Further, the shapes of the second trench and the first trench can be the same.
[0016] Further, part of the trench pitch of the second trench can also be wider than the trench pitch of the first trench in the second direction.
[0017] Further, the shapes of the second trench and the first trench can also be different. When their shapes are different, the shape of the second trench can also be an inverted "convex" shape.
[0018] Further, after forming the select gate and before forming the erase gate dielectric layer, the preparation method can further include the following steps:
[0019] The sacrificial layer exposed in the remaining space of the first trench is etched back to increase the trench spacing of the remaining space of the first trench in a direction parallel to the second direction, and the remaining space of the first trench after the increased trench spacing is used as the second trench.
[0020] Furthermore, after forming the erase gate, the fabrication method may further include the following steps:
[0021] Remove the sacrificial layer to expose the surfaces of the floating gate layers located on both sides of the erased gate;
[0022] An inter-gate dielectric layer and a control gate layer are formed, the inter-gate dielectric layer covering the surface of the exposed floating gate layer and extending to cover the top surface of the erase gate, and the control gate layer covering the surface of the exposed floating gate layer.
[0023] Furthermore, after forming the control gate layer, the fabrication method further includes:
[0024] The control gate layer, inter-gate dielectric layer and floating gate layer on both sides of the erase gate are etched to form a discrete memory structure on both sides of the erase gate, and the surfaces of the semiconductor substrates corresponding to both sides of the memory structure are exposed; and a second ion implantation process is performed on the exposed surfaces of the semiconductor substrates to form the source.
[0025] Furthermore, one side of the semiconductor substrate on which the gate oxide layer, floating gate layer, and sacrificial layer are formed is defined as the first side, and the other side of the semiconductor substrate opposite to the first side is defined as the second side;
[0026] After forming the shallow trench isolation structure and before forming the first trench, the fabrication method further includes: performing a third ion implantation process on the second surface of the semiconductor substrate to form the drain of the flash memory.
[0027] Furthermore, the ion type implanted in the third ion implantation process can be N-type ions, while the ion type implanted in the second ion implantation process in other examples can also be P-type ions.
[0028] Furthermore, the bottom of the first trench formed by etching the semiconductor substrate again exposes the semiconductor substrate after the ions have been implanted.
[0029] Secondly, based on the same inventive concept as the method for manufacturing the aforementioned flash memory, the present invention also provides a flash memory, comprising:
[0030] A semiconductor substrate, the semiconductor substrate includes a first surface and a second surface which are oppositely arranged, a gate oxide layer, a floating gate layer, an inter-gate dielectric layer and a control gate layer are sequentially stacked from bottom to top on the surface of the first surface, and a shallow trench isolation structure arranged along a first direction is formed in the control gate layer, the inter-gate dielectric layer, the floating gate layer, the gate oxide layer and a part of the semiconductor substrate, wherein, a well region is further formed in the semiconductor substrate corresponding to the position directly below the shallow trench isolation structure;
[0031] A select gate dielectric layer and a select gate, located in a first trench arranged along the second direction formed in the semiconductor substrate after rotating the semiconductor substrate to be perpendicular to the first direction, the select gate dielectric layer covers the inner surface of the lower space of the first trench, and the select gate fills the lower space of the first trench;
[0032] Two PN junctions, composed of a first ion implantation region in the semiconductor substrate on both sides of the first trench and the semiconductor substrate, wherein the conduction type of the first ion implantation region is opposite to the conduction type of the semiconductor substrate;
[0033] An erase gate dielectric layer and an erase gate, located in a second trench surrounded by the top surfaces of the gate oxide layer, the floating gate layer, the inter-gate dielectric layer, the control gate layer and the select gate exposed by the remaining space of the first trench, the erase gate dielectric layer covers the inner wall of the second trench, and the erase gate fills the second trench;
[0034] A storage structure, including a gate oxide layer, a floating gate layer, an inter-gate dielectric layer and a control gate layer stacked in sequence, located on the surface of the semiconductor substrate corresponding to both sides of the erase gate;
[0035] A source electrode, located in the semiconductor substrate exposed on both sides of the storage structure;
[0036] A drain electrode, located in the semiconductor substrate corresponding to the second surface.
[0037] Further, the trench pitch between the second trench and the first trench may be the same in the second direction.
[0038] Further, the shapes of the second trench and the first trench may be the same.
[0039] Further, the trench pitch of a part of the second trench may be wider than the trench pitch of the first trench in the second direction.
[0040] Further, the shapes of the second trench and the first trench may also be different, and the shape of the second trench may be an inverted "convex" shape.
[0041] Furthermore, the doping type of the semiconductor substrate corresponding to the drain can be N-type, while in other examples the doping type of the semiconductor substrate corresponding to the drain can also be P-type ions, the well region is a P-type well, and the ions implanted in the first ion implantation region are N-type ions.
[0042] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:
[0043] This invention provides a novel flash memory and its fabrication method. Specifically, the select gate is located in a first trench within a semiconductor substrate, while the erase gate is located on the surface of the semiconductor substrate corresponding to the first trench. This allows the select gate and erase gate to form an upper and lower structure along a direction perpendicular to the surface of the semiconductor substrate. This ensures that the gate-separated flash memory device has both low operating voltage and high reliability, while also reducing the wafer area occupied by the memory cells, thus enabling its application in small-size integrated circuits with gradually decreasing dimensions.
[0044] Furthermore, in the gate-splitting flash memory device of the present invention, the first trench used to form the select gate and the shallow trench isolation structure such as the STI structure that plays a role in device isolation are respectively formed in two semiconductor substrates corresponding to different mutually perpendicular directions, thereby further reducing the area of the wafer occupied by the memory cell and better meeting the design requirements of small-size integrated circuits with gradually shrinking dimensions.
[0045] Furthermore, in the gate-splitting flash memory device of the present invention, a first ion implantation region with the opposite conductivity type to the semiconductor substrate is formed in the semiconductor substrate on both sides of the select gate located in the semiconductor substrate. In this way, the PN junction formed by the first ion implantation region and the semiconductor substrate reduces the resistance between the select gate channel and the floating gate channel, further shielding the channel current degradation problem caused by the degradation of the insulating layer between the EG and the substrate due to the high voltage erase operation of the EG gate, thereby reducing the erase voltage and operating voltage of the gate-splitting flash memory device. Attached Figure Description
[0046] Figure 1 This is a schematic diagram of the structure of a flash memory provided in one embodiment of the present invention;
[0047] Figure 2 This is a schematic diagram of another flash memory structure provided in one embodiment of the present invention;
[0048] Figure 3 This is a schematic flowchart of a method for fabricating a flash memory according to an embodiment of the present invention;
[0049] Figures 4 to 13This is a schematic diagram of the fabrication process of a flash memory according to an embodiment of the present invention.
[0050] The accompanying figure is labeled as follows:
[0051] 100 - Semiconductor substrate; 110 - Gate oxide layer;
[0052] 120 - Floating gate layer; 130 - Inter-gate dielectric layer;
[0053] 140 - Control gate layer; 150 - Select gate dielectric layer;
[0054] 160 - Select gate layer; 170 - Erase gate dielectric layer;
[0055] 180 - Sacrificial layer; 101 - First trench;
[0056] 102 - Second trench; A - First surface of semiconductor substrate;
[0057] B - The second side of the semiconductor substrate; Y - The first direction;
[0058] X - Second direction; SG - Select gate;
[0059] EG - Erase gate; 251 - Memory structure. Detailed Implementation
[0060] As described in the background section, currently, in discrete gate flash memory devices consisting of an erase gate EG, a select gate SG, a control gate CG, and a floating gate FG, the erase gate EG, the select gate SG, and the memory structure composed of the control gate CG and the floating gate FG are all formed on the semiconductor substrate in a lateral unfolding manner. This results in a large wafer area occupied by the memory cells, the inability to integrate more memory cells on the wafer, and the inability to apply them to small-sized integrated circuits where the FG size is gradually shrinking.
[0061] To address this problem, the present invention provides a novel flash memory structure and its fabrication method, so that the novel flash memory can have low operating voltage and high reliability, while also reducing the area of the wafer occupied by the storage cells, thus adapting to the purpose of small-size integrated circuits with gradually shrinking dimensions.
[0062] The flash memory and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention can also be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.
[0063] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0064] Example 1:
[0065] refer to Figure 1 , Figure 1 This is a schematic diagram of a flash memory provided in one embodiment of the present invention; as shown below. Figure 1 As shown, the flash memory provided in one embodiment of the present invention may specifically include:
[0066] A semiconductor substrate 100 includes a first surface A and a second surface B disposed opposite to each other. On the surface of the first surface A, a gate oxide layer 110, a floating gate layer 120, an inter-gate dielectric layer 130, and a control gate layer 140 are stacked sequentially from bottom to top. A shallow trench isolation structure, such as a shallow trench isolation structure (STI), is formed within the control gate layer 140, the inter-gate dielectric layer 130, the floating gate layer 120, the gate oxide layer 110, and a portion of the semiconductor substrate 100. A P-type trap ion implantation region (PW) is also formed between the bottom of the shallow trench isolation structure (STI) and the bottom of the semiconductor substrate 100. Figure 4 As shown.
[0067] The selected gate dielectric layer 150 and the selected gate SG are located in a first trench formed in the semiconductor substrate 100 along the second direction X after the semiconductor substrate 100 is rotated to a second direction X perpendicular to the first direction Y. The selected gate dielectric layer 150 covers the inner surface of the lower space of the first trench, and the selected gate 160 fills the lower space of the first trench.
[0068] A PN junction is formed by a first ion implantation region M located on both sides of the first trench within the semiconductor substrate 100 and the semiconductor substrate 100, wherein the conductivity type of the first ion implantation region M is opposite to the conductivity type of the semiconductor substrate 100.
[0069] The erase gate dielectric layer 170 and the erase gate EG are located in a second trench formed by the gate oxide layer 110, the floating gate layer 120, the inter-gate dielectric layer 130, the control gate layer 140, and the top surface of the select gate SG exposed in the remaining space of the first trench. The erase gate dielectric layer 170 covers the inner wall of the second trench, and the erase gate EG fills the second trench.
[0070] The storage structure 251 includes a gate oxide layer 110, a floating gate layer 120, an inter-gate dielectric layer 130 and a control gate layer 140 stacked sequentially, located on the surface of the semiconductor substrate 100 corresponding to both sides of the erase gate EG.
[0071] The source S is located within the semiconductor substrate 100 exposed on both sides of the memory structure 251; and the drain D is located within the semiconductor substrate 100 corresponding to the second surface B.
[0072] Wherein, the semiconductor substrate 100 corresponding to the drain D and the first ion implantation region M can both be N-type doped, and the semiconductor substrate 100 is a P-type semiconductor substrate, so as to form a PN junction between M and the semiconductor 100.
[0073] In this embodiment, the first trench for forming the select gate SG and the second trench for forming the erase gate EG have the same shape, and both are regular polygons. For example, both can preferably be regular quadrilaterals to simplify the semiconductor manufacturing process. Furthermore, when the first trench and the second trench have the same shape, their trench spacing is the same in the second direction X.
[0074] Example 2:
[0075] refer to Figure 2 , Figure 2 This is a schematic diagram of another flash memory structure provided in one embodiment of the present invention; as shown. Figure 2 As shown, in another embodiment of the present invention, the flash memory may specifically include:
[0076] A semiconductor substrate 100 includes a first surface A and a second surface B disposed opposite to each other. On the surface of the first surface A, a gate oxide layer 110, a floating gate layer 120, an inter-gate dielectric layer 130, and a control gate layer 140 are stacked sequentially from bottom to top. A shallow trench isolation structure, such as a shallow trench isolation structure (STI), is formed within the control gate layer 140, the inter-gate dielectric layer 130, the floating gate layer 120, the gate oxide layer 110, and a portion of the semiconductor substrate 100. A P-type trap ion implantation region (PW) is also formed between the bottom of the shallow trench isolation structure (STI) and the bottom of the semiconductor substrate 100. Figure 4 As shown.
[0077] The selected gate dielectric layer 150 and the selected gate SG are located in a first trench formed in the semiconductor substrate 100 along the second direction X after the semiconductor substrate 100 is rotated to a second direction X perpendicular to the first direction Y. The selected gate dielectric layer 150 covers the inner surface of the lower space of the first trench, and the selected gate 160 fills the lower space of the first trench.
[0078] The PN junction is formed by a first ion implantation region M located on both sides of the first trench within the semiconductor substrate 100 and the semiconductor substrate 100, wherein the conductivity type of the first ion implantation region M is opposite to the conductivity type of the semiconductor substrate 100.
[0079] The erase gate dielectric layer 170 and the erase gate EG are located in a second trench formed by the gate oxide layer 110, the floating gate layer 120, the inter-gate dielectric layer 130, the control gate layer 140, and the top surface of the select gate SG exposed in the remaining space of the first trench. The erase gate dielectric layer 170 covers the inner wall of the second trench, and the erase gate EG fills the second trench.
[0080] The storage structure 251 includes a gate oxide layer 110, a floating gate layer 120, an inter-gate dielectric layer 130 and a control gate layer 140 stacked sequentially, located on the surface of the semiconductor substrate 100 corresponding to both sides of the erase gate EG.
[0081] The source S is located within the semiconductor substrate 100 exposed on both sides of the memory structure 251; and the drain D is located within the semiconductor substrate 100 corresponding to the second surface B.
[0082] Wherein, the semiconductor substrate 100 corresponding to the drain D and the first ion implantation region M can both be N-type doped, and the semiconductor substrate 100 is a P-type semiconductor substrate, so as to form a PN junction between M and the semiconductor 100.
[0083] In this embodiment, the first trench for forming the select gate SG and the second trench for forming the erase gate EG have different shapes; one is a regular quadrilateral, and the other is an irregular polygon. For example, when the shape of the second trench differs from that of the first trench, the shape of the second trench is preferably an inverted "convex" shape. This increases the capacitive coupling between the erase gate EG and the floating gate layer FG by increasing the area of the erase gate EG, thereby better reducing the operating voltage of the gate-splitting flash memory device. Furthermore, when the shapes of the first trench and the second trench are different, a portion of the trench spacing of the second trench is wider than the trench spacing of the first trench in the second direction X.
[0084] It is understood that, based on the two embodiments of the present invention described above, as long as the selected gate SG is located in the first trench within the semiconductor substrate, and the erase gate EG is located on the surface of the semiconductor substrate corresponding to the first trench forming the selected gate SG, thereby allowing the selected gate SG and the erase gate EG to form an upper and lower structure along a direction perpendicular to the substrate surface, and the first trench used to form the selected gate SG and the shallow trench isolation structure, such as the STI structure, which serves as device isolation, are respectively formed in substrates corresponding to two mutually perpendicular directions, then all of these technical solutions fall within the protection scope of the embodiments of the present invention. As for whether the shapes of the first trench and the second trench are the same, this also falls within the overall inventive concept of the present invention; only the technical effects they can achieve are different.
[0085] It is understood that in this embodiment of the invention, the drain of the formed flash memory device is of N-type ion type, that is, the flash memory device is an N-type channel gate flash memory device, which is only shown as an example, as above. Figure 1 and Figure 2 The device structure shown can also be a P-channel gate-divided flash memory device, which is not specifically limited in this invention.
[0086] Furthermore, in the gate-splitting flash memory device of the present invention, a first ion implantation region with the opposite conductivity type to the semiconductor substrate is formed in the semiconductor substrate on both sides of the select gate located in the semiconductor substrate. In this way, the PN junction formed by the first ion implantation region and the semiconductor substrate reduces the resistance between the select gate channel and the floating gate channel, further shielding the channel current degradation problem caused by the degradation of the insulating layer between the EG and the substrate due to the high voltage erase operation of the EG gate, thereby reducing the erase voltage and operating voltage of the gate-splitting flash memory device.
[0087] The following is a detailed explanation of the above. Figure 1 and Figure 2 In addition to the aforementioned flash memory device fabrication process, this embodiment of the invention also provides a method for fabricating a flash memory.
[0088] See Figure 3 , Figure 3 This is a schematic flowchart illustrating a method for fabricating a flash memory according to an embodiment of the present invention. Figure 3 As shown, the method for fabricating the flash memory provided in this embodiment of the invention may include at least the following steps:
[0089] Step S101: A semiconductor substrate is provided, wherein a gate oxide layer, a floating gate layer, and a sacrificial layer are stacked sequentially from bottom to top on the surface of the first side of the semiconductor substrate, and a shallow trench isolation structure disposed along a first direction is formed in the sacrificial layer, the floating gate layer, the gate oxide layer, and a portion of the semiconductor substrate.
[0090] In step S102, the semiconductor substrate with the shallow trench isolation structure is rotated to the second direction and the semiconductor substrate is etched again to form a first trench disposed along the second direction in the sacrificial layer, the floating gate layer, the gate oxide layer and a portion of the semiconductor substrate, wherein the first direction is perpendicular to the second direction.
[0091] Step S103: Form a select gate dielectric layer and a select gate layer, wherein the select gate dielectric layer at least covers the inner surface of the lower space of the first trench, and the select gate layer at least fills the lower space of the first trench to form a select gate in a portion of the first trench located within the semiconductor substrate.
[0092] Step S104: Perform a first ion implantation process on the semiconductor substrate to form a first ion implantation region in the semiconductor substrate on both sides of the first trench, wherein the conductivity type of the first ion implantation region is opposite to that of the semiconductor substrate.
[0093] Step S105: An erase gate dielectric layer and an erase gate layer are formed. The erase gate dielectric layer covers the top surface of the selected gate and the inner wall of the second trench formed by the floating gate layer, the sacrificial layer, and the top surface of the selected gate exposed by the remaining space of the first trench. The erase gate layer fills the second trench to form an erase gate on the semiconductor substrate.
[0094] Step S106: Perform subsequent processes on the semiconductor substrate to form a control gate layer covering the surface of the floating gate layer and a source electrode located in the semiconductor substrate on both sides of the stacked floating gate layer and control gate layer.
[0095] Example 3:
[0096] See Figure 4 In step S101 above, a semiconductor substrate 100 can be provided first. The semiconductor substrate 100 is used to provide an operating platform for subsequent processes to generate a split-gate flash memory device with the selected gate SG and erase gate EG having the above-mentioned upper and lower structure. Preferably, the semiconductor substrate 100 is a silicon substrate. The three-dimensional structure of the semiconductor substrate 100 is then divided into a first direction Y and a second direction X. A gate oxide layer 110, a floating gate layer 120, a sacrificial layer 180, and a photoresist layer (not shown) are sequentially deposited on the surface (first surface) of the two-dimensional plane containing the first direction Y. The sacrificial layer 180 is made of silicon nitride. Then, an etching process is used to form a trench for forming a shallow trench isolation structure within the gate oxide layer 110, the floating gate layer 120, the sacrificial layer 180, the photoresist layer (not shown), and a portion of the semiconductor substrate 100. Subsequently, an ion implantation process is used to implant ions into the semiconductor substrate 100 exposed at the bottom of the trench along its depth direction to form a P-type ion implantation well region PW. Finally, the trench is filled to form a structure as shown in the image. Figure 5 The shallow trench isolation structure (STI) shown is a memory cell isolation component for a gated flash memory device, wherein the material filled in the shallow trench isolation structure STI is silicon dioxide.
[0097] It is understood that the semiconductor substrate 100 can be any suitable substrate known in the art, such as at least one of the following materials: silicon, germanium, germanium silicon, silicon carbon, germanium silicon carbon, indium arsenide, gallium arsenide, indium phosphide, or other III / V compound semiconductors, and also includes multilayer structures composed of these semiconductors. For example, in this embodiment, the semiconductor substrate 100 is, for example, a silicon wafer.
[0098] Furthermore, in this embodiment, one side of the semiconductor substrate 100 on which the gate oxide layer 110, the floating gate layer 120, and the sacrificial layer 180 are formed can be defined as the first side A, and the other side of the semiconductor substrate 100 opposite to the first side A can be defined as the second side B.
[0099] After forming the shallow trench isolation structure STI and before forming the first trench 101 as described below, the fabrication method further includes performing an ion implantation process on the second surface of the semiconductor substrate 100 to form the drain D of the flash memory.
[0100] The ion type of the drain electrode D is N-type ions.
[0101] It should be noted that, as an example, in this embodiment of the invention, the flash memory device is preferably configured as an N-channel gate flash memory device. Therefore, the semiconductor substrate 100 in this embodiment of the invention is preferably a P-type doped semiconductor substrate.
[0102] In other embodiments, as described above Figure 1 and Figure 2 The device structure shown is a P-channel gate-divided flash memory device, and the semiconductor substrate 100 is an N-type doped semiconductor substrate. This invention does not specifically limit the semiconductor substrate in this respect.
[0103] See Figures 5-6 In step S102 above, first, as shown... Figure 4 The semiconductor substrate 100 shown is rotated from a first direction Y to a second direction X on which the shallow trench isolation structure STI is formed, wherein Figure 5 yes Figure 4 The diagram shown is a three-dimensional structure of the semiconductor substrate 100 after being rotated from the first direction Y to the second direction X where the shallow trench isolation structure STI is formed. Figure 6 Yes Figure 5 A schematic diagram of a structure in which a first trench 101 disposed along the second direction X is formed in the sacrificial layer 180, the floating gate layer 120, the gate oxide layer 110 and a portion of the semiconductor substrate 100 is etched.
[0104] Wherein, the first direction Y is perpendicular to the second direction X. Furthermore, the bottom of the first trench 101 formed by etching the semiconductor substrate 100 again exposes the semiconductor substrate 100 after the N-type ions have been implanted.
[0105] It should be noted that, due to Figure 5It is only used to show the difference between the two-dimensional plane in which the first trench 101 used to form the selected gate SG is located and the shallow trench isolation structure STI, that is, the positional relationship between the first direction Y and the second direction X as described above, and does not fully characterize the other film layers, wherein SG PR is the photoresist layer used to form the first trench 101.
[0106] See Figures 7-8 In step S103 above, a selection gate dielectric layer 150 and a selection gate layer 160 filling the remaining area of the first trench 101 can be uniformly formed on the inner wall of the first trench 101 using a deposition process. Then, a portion of the selection gate layer 160 is etched away to form the selection gate SG in the lower space of the first trench 101.
[0107] Furthermore, regarding Figure 8 The semiconductor structure 100 shown is subjected to an ion implantation process to form a first ion implantation region M in the semiconductor substrate 100 on both sides of the first trench 101, wherein the conductivity type of the first ion implantation region M is opposite to that of the semiconductor substrate 100.
[0108] For example, in this embodiment of the invention, the semiconductor substrate 100 has a P-type conductivity and the M region has an N-type conductivity. That is, a PN junction is formed in a portion of the semiconductor substrate 100 corresponding to both sides of the first trench 101 to shield the channel current change caused by the degradation of the gate oxide in the EG region under a high electric field.
[0109] See Figure 9 After forming the select gate SG and before forming the erase gate dielectric layer 170, the fabrication method further includes:
[0110] Step S102.1, along the direction of the first trench 101, a protective layer (not shown) is formed on the surface of the select gate SG that is filled in the lower space of the first trench 101, and the top surface of the protective layer is flush with the top surface of the floating gate layer 120 exposed by the sidewall of the remaining space of the first trench 101.
[0111] Step S102.2: Perform a back etching process on the sacrificial layer 180 exposed in the remaining space of the first trench 101 to increase the trench spacing of the remaining space of the first trench 101 in a direction parallel to the second direction X.
[0112] Step S102.3: Remove the protective layer so that the remaining space of the first trench 101 after increasing the trench spacing becomes the second trench 102, wherein the second trench 102 is surrounded by the floating gate layer 120, the sacrificial layer 180 and the top surface of the select gate SG exposed by the remaining space of the first trench 101.
[0113] See Figure 10 After step S102.3 above, and in step S104 above, an erase gate dielectric layer 170 and an erase gate layer filling the remaining space of the second trench 102 can be formed on the inner wall of the second trench 102 using a deposition process, so as to form an erase gate EG on the semiconductor substrate 100.
[0114] In this embodiment, the first trench 101 and the second trench 102 have the same projection along a direction perpendicular to the semiconductor substrate 100, with one located inside the semiconductor substrate 100 and the other on the surface of the semiconductor substrate 100, thereby forming the upper and lower structure of the select gate SG and the erase gate EG. Because the shape used to form the erase gate EG is as follows... Figure 10 The inverted "convex" shaped second trench 102 shown increases the area of the erase gate EG in the lateral direction, which increases the capacitive coupling between the erase gate EG and the floating gate layer FG, thereby achieving the purpose of better reducing the operating voltage of the gate-splitting flash memory device.
[0115] See Figure 11 In step S105 above, after forming the erase gate EG, the fabrication method may further remove the sacrificial layer 180 to expose the surfaces of the floating gate layers 120 located on both sides of the erase gate EG; then, an inter-gate dielectric layer 130 and a control gate layer 140 are formed, the inter-gate dielectric layer 130 covering the surface of the exposed floating gate layer 120 and extending to cover the top surface of the erase gate EG, and the control gate layer 140 covering the surface of the exposed floating gate layer 120.
[0116] See Figure 12 After forming the control gate layer 140, the fabrication method further includes:
[0117] The control gate layer 140, the inter-gate dielectric layer 130, the floating gate layer 120, and the gate oxide layer 110 on both sides of the erase gate EG are etched to form a discrete memory structure 251 on both sides of the erase gate EG, and to expose the surface of the semiconductor substrate 100 corresponding to both sides of the memory structure 251; and a first ion implantation process is performed on the exposed surface of the semiconductor substrate 100 to form the source S.
[0118] Example 4:
[0119] Specifically, Example 4 is used to form Figure 1 The fabrication process of the gate-splitting flash memory device with the same shape for forming the first trench of the select gate SG and the second trench of the erase gate EG is based on... Figure 1 and Figure 2 As can be seen from the structure shown, the difference between the two lies in whether the shape of the second trench is the same as that of the first trench, while the other steps are the same. Therefore, in this embodiment, only the inventive steps that are different from those in Embodiment 3 above will be described, as follows:
[0120] See Figures 4-8 After forming the selection gate SG in the lower space of the first trench 101 in step S103, the back etching process in a direction parallel to the second direction X for the remaining portion of the first trench 101 located on the surface of the semiconductor substrate 100 in steps S102.1 to S102.3 can be skipped. Instead, the following steps can be performed:
[0121] See Figure 13 The select gate dielectric layer 150 not covered by the select gate SG in the first trench 101 is removed to expose the gate oxide layer 110, floating gate layer 120, and sacrificial layer 180 corresponding to the remaining space of the first trench 101. The erase gate dielectric layer 170 and the erase gate layer are sequentially formed in the remaining space (second trench 102) of the first trench 101 where the gate oxide layer 110, floating gate layer 120, and sacrificial layer 180 are exposed to form the erase gate EG.
[0122] It should be noted that in any embodiment of the invention, after the deposition process, it may also include processes such as chemical mechanical polishing and cleaning of the corresponding film layer formed by the deposition process. This invention will not be specifically limited.
[0123] In summary, this invention provides a novel flash memory and its fabrication method. Specifically, the select gate is located in a first trench within a semiconductor substrate, while the erase gate is located on the surface of the semiconductor substrate corresponding to the first trench. This allows the select gate and erase gate to form an upper and lower structure along a direction perpendicular to the surface of the semiconductor substrate. This ensures that the gate-separated flash memory device has both low operating voltage and high reliability, while also reducing the wafer area occupied by the memory cells, thus enabling its application in small-size integrated circuits with gradually decreasing dimensions.
[0124] Furthermore, in the gate-splitting flash memory device of the present invention, the first trench used to form the select gate and the shallow trench isolation structure such as the STI structure that plays a role in device isolation are respectively formed in two semiconductor substrates corresponding to different mutually perpendicular directions, thereby further reducing the area of the wafer occupied by the memory cell and better meeting the design requirements of small-size integrated circuits with gradually shrinking dimensions.
[0125] Furthermore, in the gate-splitting flash memory device of the present invention, a first ion implantation region with the opposite conductivity type to the semiconductor substrate is formed in the semiconductor substrate on both sides of the select gate located in the semiconductor substrate. In this way, the PN junction formed by the first ion implantation region and the semiconductor substrate reduces the resistance between the select gate channel and the floating gate channel, further shielding the channel current degradation problem caused by the degradation of the insulating layer between the EG and the substrate due to the high voltage erase operation of the EG gate, thereby reducing the erase voltage and operating voltage of the gate-splitting flash memory device.
[0126] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.
[0127] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.
[0128] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.
Claims
1. A method for fabricating a flash memory, characterized in that, Comprising: Providing a semiconductor substrate, on the surface of the first side of the semiconductor substrate, a gate oxide layer, a floating gate layer, and a sacrificial layer are stacked in sequence from bottom to top, and a shallow trench isolation structure arranged in a first direction is further formed in the sacrificial layer, the floating gate layer, the gate oxide layer, and a part of the semiconductor substrate; Rotating the semiconductor substrate formed with the shallow trench isolation structure to a second direction, and etching the semiconductor substrate again to form a first trench arranged in the second direction in the sacrificial layer, the floating gate layer, the gate oxide layer, and a part of the semiconductor substrate, wherein the first direction is perpendicular to the second direction; Forming a select gate dielectric layer and a select gate layer, the select gate dielectric layer at least covers the inner surface of the lower space of the first trench, and the select gate layer at least fills the lower space of the first trench to form a select gate in a part of the first trench located in the semiconductor substrate; Performing a first ion implantation process on the semiconductor substrate to respectively form a first ion implantation region in the semiconductor substrate on both sides of the first trench, and the conductivity type of the first ion implantation region is opposite to the conductivity type of the semiconductor substrate; Forming an erase gate dielectric layer and an erase gate layer, the erase gate dielectric layer covers the top surface of the select gate and the inner wall of a second trench surrounded by the floating gate layer, the sacrificial layer, and the top surface of the select gate exposed by the remaining space of the first trench, and the erase gate layer fills the second trench to form an erase gate on the semiconductor substrate; Performing subsequent processes on the semiconductor substrate to form a control gate layer covering the surface of the floating gate layer and source electrodes in the semiconductor substrate on both sides of the stacked floating gate layer and control gate layer; 2. The method for fabricating a flash memory as described in claim 1, characterized in that, The ions implanted in the first ion implantation region are N-type ions; 3. The method for manufacturing a flash memory as described in claim 1, characterized in that, The trench pitch between the second trench and the first trench is the same in the second direction; 4. The method for manufacturing a flash memory as described in claim 3, characterized in that, The shape of the second trench is the same as that of the first trench; 5. The method for fabricating a flash memory as described in claim 1, characterized in that, Part of the trench pitch of the second trench is wider than the trench pitch of the first trench in the second direction; 6. The method for manufacturing a flash memory as described in claim 5, characterized in that, The shape of the second trench is different from that of the first trench, and the shape of the second trench is an inverted "convex" shape; 7. The method for manufacturing a flash memory as described in claim 1, characterized in that, After forming the select gate and before forming the erase gate dielectric layer, the preparation method further includes: Performing a back-etching process on the sacrificial layer exposed in the remaining space of the first trench to increase the trench pitch of part of the remaining space of the first trench along a direction parallel to the second direction, and using the remaining space of the first trench with the increased trench pitch as the second trench; 8. The method for manufacturing a flash memory as described in claim 7, characterized in that, After forming the erase gate, the preparation method further includes: Removing the sacrificial layer to expose the surfaces of the floating gate layers on both sides of the erase gate; Forming an inter-gate dielectric layer and a control gate layer, the inter-gate dielectric layer covers the exposed surface of the floating gate layer and extends to cover the top surface of the erase gate, and the control gate layer covers the exposed surface of the floating gate layer; 9. The method for manufacturing a flash memory as described in claim 8, characterized in that, After forming the control gate layer, the preparation method further includes: Etch the control gate layer, the inter-gate dielectric layer, and the floating gate layer on both sides of the erase gate to form a discrete storage structure on each side of the erase gate, and expose the surfaces of the semiconductor substrate corresponding to both sides of the storage structure; and perform a second ion implantation process on the exposed surfaces of the semiconductor substrate to form the source electrode.
10. The method for manufacturing a flash memory as described in claim 7, characterized in that, After forming the shallow trench isolation structure and before forming the first trench, the manufacturing method further includes: performing a third ion implantation process on the second surface of the semiconductor substrate to form the drain of the flash memory, where the second surface is disposed opposite to the first surface.
11. A flash memory, characterized in that, Comprising: A semiconductor substrate, the semiconductor substrate includes a first surface and a second surface disposed opposite to each other. On the surface of the first surface, a gate oxide layer, a floating gate layer, an inter-gate dielectric layer, and a control gate layer are stacked in sequence from bottom to top. And a shallow trench isolation structure is formed in the control gate layer, the inter-gate dielectric layer, the floating gate layer, the gate oxide layer, and a part of the semiconductor substrate and is disposed along a first direction. Wherein, a well region is further formed in the semiconductor substrate corresponding to the position directly below the shallow trench isolation structure. A select gate dielectric layer and a select gate electrode, located in a first trench formed in the semiconductor substrate along the second direction after rotating the semiconductor substrate to be perpendicular to the first direction. The select gate dielectric layer covers the inner surface of the lower space of the first trench, and the select gate electrode fills the lower space of the first trench. A PN junction, composed of a first ion implantation region in the semiconductor substrate on both sides of the first trench and the semiconductor substrate, where the conductivity type of the first ion implantation region is opposite to the conductivity type of the semiconductor substrate. An erase gate dielectric layer and an erase gate, located in a second trench surrounded by the top surfaces of the gate oxide layer, the floating gate layer, the inter-gate dielectric layer, the control gate layer, and the select gate electrode exposed by the remaining space of the first trench. The erase gate dielectric layer covers the inner wall of the second trench, and the erase gate fills the second trench. A storage structure, including a gate oxide layer, a floating gate layer, an inter-gate dielectric layer, and a control gate layer stacked in sequence, located on the surfaces of the semiconductor substrate corresponding to both sides of the erase gate. A source electrode, located in the semiconductor substrate exposed on both sides of the storage structure. A drain electrode, located in the semiconductor substrate corresponding to the second surface.
12. The flash memory as claimed in claim 11, characterized in that, The trench pitch between the second trench and the first trench is the same in the second direction.
13. The flash memory as claimed in claim 12, characterized in that, The shapes of the second trench and the first trench are the same.
14. The flash memory as claimed in claim 11, characterized in that, Part of the trench pitch of the second trench is wider than the trench pitch of the first trench in the second direction.
15. The flash memory as claimed in claim 14, characterized in that, The shapes of the second trench and the first trench are different, and the shape of the second trench is an inverted "convex" shape.
16. The flash memory as claimed in claim 11, characterized in that, The doping type of the semiconductor substrate corresponding to the drain is N-type, the well region is a P-type well, and the ions implanted in the first ion implantation region are N-type ions.