Method of fabricating a semiconductor structure

Abstract

A method for manufacturing a semiconductor structure includes: providing a substrate (10), a heterojunction structure (11) and a P-type semiconductor layer (12) distributed from bottom to top; forming a patterned mask layer (13) on the P-type semiconductor layer (12), the patterned mask layer (13) covering at least the P-type semiconductor layer (12) of a gate region (11a); using a corrosive gas to etch and remove the exposed P-type semiconductor layer (12) in situ with the patterned mask layer (13) as a mask; and then activating P-type doping ions in the P-type semiconductor layer (12). When the P-type semiconductor layer (12) on the heterojunction structure (11) is patterned, the P-type semiconductor layer (12) of certain materials can react with the targeted corrosive gas to complete etching and removal, so that etching of the P-type semiconductor layer (12) can be realized in situ by introducing the corrosive gas into the process chamber in the previous step. The transfer process of the etching chamber can be avoided, the risk of contamination is avoided, and the production efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure. Background Technology

[0002] As a typical representative of third-generation semiconductor materials, group III nitrides, with their wide bandgap semiconductors, have excellent properties such as large bandgap, high voltage resistance, high temperature resistance, high electron saturation velocity and drift velocity, and easy formation of high-quality heterostructures. They are very suitable for manufacturing high-temperature, high-frequency, and high-power electronic devices.

[0003] For example, AlGaN / GaN heterojunctions have strong spontaneous polarization and piezoelectric polarization, resulting in a high concentration of two-dimensional electron gas (2DEG) at the AlGaN / GaN interface. They are widely used in semiconductor structures such as high electron mobility transistors (HEMTs).

[0004] Enhancement-mode devices have a wide range of applications in power electronics due to their normally-off nature. There are many ways to implement enhancement-mode devices, such as by depleting the two-dimensional electron gas by placing a P-type semiconductor layer at the gate.

[0005] However, etching away the P-type semiconductor layer outside the gate region must be done in an etching chamber. The semiconductor process involves multiple chamber transfers, which increases the risk of contamination and reduces production efficiency.

[0006] In view of this, it is necessary to provide a new method for fabricating semiconductor structures to solve the above-mentioned technical problems. Summary of the Invention

[0007] The purpose of this invention is to provide a method for fabricating semiconductor structures, thereby reducing the risk of contamination and improving production efficiency.

[0008] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor structure, comprising:

[0009] It provides a substrate, heterojunction structure, and P-type semiconductor layer distributed from bottom to top;

[0010] A patterned mask layer is formed on the P-type semiconductor layer, the patterned mask layer at least covering the P-type semiconductor layer in the gate region; using the patterned mask layer as a mask, the exposed P-type semiconductor layer is removed by in-situ etching with a corrosive gas;

[0011] Activate the P-type doped ions in the P-type semiconductor layer.

[0012] Optionally, the in-situ etching includes: the step of forming a patterned mask layer and the etching step are performed in the same reaction chamber or in a different chamber of the vacuum interconnect device.

[0013] Optionally, the material of the P-type semiconductor layer is GaN, and the in-situ etching to remove the exposed P-type semiconductor layer is performed at a temperature higher than 300°C. The corrosive gas includes: H2 and / or NH3, or a mixture of Cl2 and N2, or HCl.

[0014] Optionally, in-situ etching to remove the exposed P-type semiconductor layer is performed at a temperature above 700°C.

[0015] Optionally, before activating the P-type doped ions in the P-type semiconductor layer, the patterned mask layer is removed to expose the P-type semiconductor layer in the gate region.

[0016] Optionally, after activating the P-type doping ion step in the P-type semiconductor layer, an N-type semiconductor layer is grown on both sides of the P-type semiconductor layer and on the heterojunction structure using the patterned mask layer as a mask.

[0017] Optionally, the material of the N-type semiconductor layer is GaN or AlGaN.

[0018] Optionally, after activating the P-type doping ion step in the P-type semiconductor layer, an N-type semiconductor layer is grown on top of the patterned mask layer, on both sides of the patterned mask layer and the P-type semiconductor layer, and on the heterojunction structure.

[0019] Optionally, the material of the N-type semiconductor layer is AlN.

[0020] Optionally, the material of the heterojunction structure adjacent to the P-type semiconductor layer is AlGaN.

[0021] Optionally, after the in-situ etching step to remove the exposed P-type semiconductor layer, a cooling step is performed; during the cooling step, the supply of the corrosive gas is stopped.

[0022] Optionally, during the cooling step, the supply of the corrosive gas is stopped when the temperature is not lower than 600°C.

[0023] Optionally, an inert protective gas is provided during the cooling step.

[0024] Optionally, activation of the P-type doped ions in the P-type semiconductor layer is achieved by annealing at a temperature greater than 500°C.

[0025] Optionally, the material of the patterned mask layer is silicon dioxide, silicon nitride, or silicon oxynitride.

[0026] Optionally, the fabrication method further includes: forming a source on the source region, forming a drain on the drain region, and forming a gate on the activated P-type semiconductor layer.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] 1) When patterning a P-type semiconductor layer on a heterojunction structure, the P-type semiconductor layer of certain materials can react with a targeted corrosive gas to complete the etching removal. Therefore, etching the P-type semiconductor layer can be achieved by introducing the corrosive gas into the process chamber of the previous step; that is, the etching is an in-situ process. The advantages are: it avoids the need to transfer the etching chamber, avoids the risk of contamination, and also improves production efficiency.

[0029] 2) In the optional scheme, the material of the P-type semiconductor layer is GaN, and the corrosive gases include H2 and / or NH3. H2 can react with solid GaN material at high temperature to generate gaseous Ga and NH3; NH3 can catalyze the conversion of solid GaN material into gaseous GaN material. H2 and / or NH3 react completely with solid GaN material and will not corrode other materials, such as the patterned mask layer and heterojunction structure. Therefore, the patterned P-type semiconductor layer has good etching selectivity and will not cause etching damage to the heterojunction structure.

[0030] 3) In an optional scheme, when activating the P-type doped ions in the P-type semiconductor layer, a patterned mask layer is covered on the P-type semiconductor layer, and the material of the patterned mask is silicon dioxide. Oxygen ions in silicon dioxide can adsorb H ions in the P-type semiconductor layer and release them to the outside through the surface. Therefore, the H ion release rate during the activation process of the P-type semiconductor layer can be accelerated.

[0031] 4) In an optional embodiment, after activating the P-type doping ions in the P-type semiconductor layer, an N-type semiconductor layer is grown on both sides of the P-type semiconductor layer and on the heterojunction structure, using a patterned mask layer as a mask. The N-type semiconductor layer can provide electron carriers to the heterojunction structure, thereby reducing the resistance between the source and drain when they are turned on. The N-type semiconductor layer can be formed by doping N-type elements within the semiconductor layer, or it can be an unintentionally doped semiconductor layer.

[0032] 5) In the optional scheme, after activating the P-type doping ions in the P-type semiconductor layer, an N-type semiconductor layer is grown on top of the patterned mask layer, on both sides of the patterned mask layer and the P-type semiconductor layer, and on the heterojunction structure. The difference from the optional scheme 4) is that the specific material of the N-type semiconductor layer can be selected to determine whether it can be grown on the patterned mask layer.

[0033] 6) In the optional scheme, after the in-situ etching step to remove the exposed P-type semiconductor layer, a cooling step is performed; during the cooling step, the supply of corrosive gases H2 and NH3 is stopped. H ions will combine with P-type dopant ions (such as Mg ions), thus passivating the P-type dopant ions and preventing them from generating holes. Stopping the supply of H2 and NH3 can prevent the P-type dopant ions from being passivated. Attached Figure Description

[0034] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to the first embodiment of the present invention;

[0035] Figure 2 and Figure 3 yes Figure 1 A schematic diagram of the intermediate structure corresponding to the process in the document;

[0036] Figure 4 This is a schematic diagram of the intermediate structure corresponding to the semiconductor structure fabrication method of the second embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of the intermediate structure corresponding to the method for fabricating the semiconductor structure according to the third embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram of the intermediate structure corresponding to the semiconductor structure fabrication method of the fourth embodiment of the present invention;

[0039] Figure 7 This is a schematic diagram of the intermediate structure corresponding to the semiconductor structure fabrication method of the fifth embodiment of the present invention;

[0040] Figure 8 This is a schematic diagram of the intermediate structure corresponding to the method for fabricating the semiconductor structure according to the sixth embodiment of the present invention;

[0041] Figure 9 and Figure 10 This is a schematic diagram of an intermediate structure corresponding to the method for fabricating a semiconductor structure according to the seventh embodiment of the present invention.

[0042] To facilitate understanding of this invention, all reference numerals appearing in the accompanying drawings are listed below:

[0043] Substrate 10 Heterojunction structure 11

[0044] Channel layer 111 Barrier layer 112

[0045] Gate region 11a Source region 11b

[0046] Drain region 11c P-type semiconductor layer 12

[0047] Patterned mask layer 13 N-type semiconductor layer 14

[0048] Gate 15a Source 15b

[0049] Drain 15c Detailed Implementation

[0050] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0051] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to the first embodiment of the present invention; Figure 2 and Figure 3 yes Figure 1 The diagram shows the intermediate structure corresponding to the process flow.

[0052] First, refer to Figure 1 Step S1 and Figure 2 As shown, a substrate 10, a heterojunction structure 11, and a P-type semiconductor layer 12 are provided, distributed from bottom to top.

[0053] The substrate 10 can be made of sapphire, silicon carbide, silicon, silicon-on-insulator (SOI), lithium niobate, GaN, AlN, or diamond.

[0054] The heterojunction structure 11 may include group III nitride materials.

[0055] In this embodiment, the heterojunction structure 11 includes a channel layer 111 and a barrier layer 112 from bottom to top. A two-dimensional electron gas can be formed at the interface between the channel layer 111 and the barrier layer 112. The materials of the channel layer 111 and the barrier layer 112 can be group III nitride materials. In one optional embodiment, the channel layer 111 is an intrinsic GaN layer, and the barrier layer 112 is an N-type AlGaN layer. The N-type ions can be at least one of Si ions, Ge ions, Sn ions, Se ions, or Te ions. In other optional embodiments, the material combination of the channel layer 111 and the barrier layer 112 can also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. In addition, besides Figure 2 The channel layer 111 and the barrier layer 112 shown each have one layer; the channel layer 111 and the barrier layer 112 may also have multiple layers, which are alternately distributed; or one channel layer 111 and two or more barrier layers 112 to form a multi-barrier structure.

[0056] The epitaxial growth process of the channel layer 111 and the barrier layer 112 may include: atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or a combination thereof.

[0057] In some embodiments, the heterojunction structure 11 may also include a back barrier layer and a channel layer from bottom to top.

[0058] The heterojunction structure 11 includes a gate region 11a, and a source region 11b and a drain region 11c located on both sides of the gate region 11a. The gate region 11a is used to form the gate, the source region 11b is used to form the source, and the drain region 11c is used to form the drain.

[0059] The heterojunction structure 11 and the substrate 10 may also have a nucleation layer and a buffer layer (not shown) from bottom to top. The nucleation layer can be made of materials such as AlN or AlGaN, and the buffer layer can be made of at least one of AlN, GaN, AlGaN, and AlInGaN. The nucleation layer can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer, such as the channel layer 111 in the heterojunction structure 11, and the substrate 10. The buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, thereby improving the crystal quality.

[0060] The material of the P-type semiconductor layer 12 is a group III-V compound. In this embodiment, the P-type semiconductor layer 12 is specifically GaN. In other embodiments, other materials may also be used.

[0061] The epitaxial growth process of the P-type semiconductor layer 12 can refer to the epitaxial growth process of the channel layer 111 and the barrier layer 112. The P-type dopant ions can be at least one of Mg ions, Zn ions, Ca ions, Sr ions, or Ba ions, to deplete the two-dimensional electron gas below the gate region to form an enhancement-mode device. The P-type dopant ions in the P-type semiconductor layer 12 can be achieved through in-situ doping.

[0062] In some embodiments, the substrate 10, heterojunction structure 11, and P-type semiconductor layer 12 distributed from bottom to top in step S1 can also be existing semi-finished structures.

[0063] Next, refer to Figure 1 Step S2 and Figure 2 As shown, a patterned mask layer 13 is formed on the P-type semiconductor layer 12, and the patterned mask layer 13 at least covers the P-type semiconductor layer 12 of the gate region 11a; Refer to Figure 2 and Figure 3 As shown, using patterned mask layer 13 as a mask, the exposed P-type semiconductor layer 12 is removed by in-situ etching with corrosive gas.

[0064] The mask layer 13 can be made of silicon dioxide, silicon nitride, or silicon oxynitride, and can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical evaporation deposition (LPCVD), or atomic layer deposition (ALD), respectively. Patterning can be achieved using dry etching or wet etching. (Refer to...) Figure 2 As shown, in this embodiment, the size of the patterned mask layer 13 is slightly larger than the size of the gate region 11a.

[0065] In this embodiment, the material of the P-type semiconductor layer 12 is GaN, and the corresponding corrosive gases include H2 and / or NH3.

[0066] At high temperatures, such as above 300°C, the chemical equation for the reaction between H2 and the exposed P-type semiconductor layer 12 is as follows:

[0067] 3H2+2GaN=2Ga(g)↑+2NH3↑;

[0068]

[0069] At high temperatures, such as above 300°C, the chemical equation for the reaction between NH3 and the exposed p-type semiconductor layer 12 is as follows:

[0070]

[0071] The above reaction is preferably carried out at a temperature above 700°C.

[0072] The etching of the P-type semiconductor layer 12 described above is a dry etching process. Dry etching can be inductively coupled plasma etching (ICP).

[0073] Since the GaN-based P-type semiconductor layer 12 can react with targeted corrosive gases H2 and / or NH3 to complete the etching removal, the etching of the P-type semiconductor layer 12 can be achieved in situ by introducing corrosive gases into the process chamber of the previous step. The advantages are: it avoids the need for transferring the etching chamber, eliminates the risk of contamination, and improves production efficiency. The process chamber of the previous step may include: the chamber where the mask layer 13 is formed and patterned, and may also include: the chamber where the heterojunction structure 11 and the epitaxial growth of the P-type semiconductor layer 12 are located.

[0074] In other embodiments, the process chamber and the etching chamber in the previous step may also be different chambers of the vacuum interconnect device.

[0075] H2 and / or NH3 corrosive gases do not react with the patterned mask layer 13, thus providing good etching selectivity when patterning the P-type semiconductor layer 12. Furthermore, by selecting a material for the barrier layer 112, it is ensured that it does not react with H2 and / or NH3 corrosive gases. The barrier layer 112 can serve as an etching termination layer for the patterning of the P-type semiconductor layer 12, preventing etching damage to the heterojunction structure 11.

[0076] In some embodiments, the corrosive gas may also be a mixture of Cl2 and N2, or HCl. In the Cl2 and N2 mixture, the amount of Cl2 is preferably less than 10% of the total amount of the corrosive gas.

[0077] Then, refer to Figure 1 Step S3 and Figure 3 As shown, P-type doped ions in the P-type semiconductor layer 12 are activated.

[0078] In the process environment for growing the P-type semiconductor layer 12, such as the MOCVD growth environment, there are a large number of H ions. If they are not removed, the P-type dopant ions (acceptor dopants, such as Mg ions) in the group III nitride material will bond with the H ions, that is, they will be passivated by a large number of H ions and will not generate holes.

[0079] Activating the P-type dopant ions in the P-type semiconductor layer 12 can be achieved through high-temperature annealing, for example, at temperatures above 500°C, to allow H ions to escape. In some embodiments, high-temperature annealing is performed in an inert gas to prevent the introduction of H ions; for example, the P-type dopant ions can be activated in a hydrogen-free atmosphere such as nitrogen, a mixture of nitrogen and oxygen, nitrous oxide (NO), or argon. During high-temperature annealing, nitrogen molecules and their decomposition products can effectively penetrate into the surface of the group III nitride material, effectively compensating for nitrogen vacancies created during etching and improving the quality of the P-type semiconductor layer 12.

[0080] The activation of P-type doped ions in the P-type semiconductor layer 12 can also be performed in situ, i.e., in the same chamber as step S2.

[0081] Reference Figure 3 As shown, in this embodiment, when activating the P-type doped ions in the P-type semiconductor layer 12, a patterned mask layer 13 is covered on the P-type semiconductor layer 12. When the material of the patterned mask 13 is a silicon dioxide layer, the oxygen ions in the silicon dioxide can adsorb the H ions in the P-type semiconductor layer 12 and release them to the outside through the surface. Therefore, the release rate of H ions in the P-type semiconductor layer 12 can be accelerated.

[0082] Figure 4 This is a schematic diagram of an intermediate structure corresponding to the method for fabricating a semiconductor structure according to the second embodiment of the present invention. (Refer to...) Figure 4 As shown, the method for fabricating the semiconductor structure in this embodiment two is largely the same as the method for fabricating the semiconductor structure in embodiment one, except that a cooling step is performed between steps S2 and S3, during which the supply of corrosive gas is stopped.

[0083] The advantage is that it can prevent the P-type doped ions in the P-type semiconductor layer 12 from combining with H ions in the corrosive gas and being passivated.

[0084] Preferably, during the cooling step, the supply of corrosive gas is stopped at a temperature not lower than 600°C.

[0085] Figure 5 This is a schematic diagram of an intermediate structure corresponding to the method for fabricating a semiconductor structure according to the third embodiment of the present invention. (Refer to...) Figure 5 As shown, the method for fabricating the semiconductor structure in Embodiment 3 is largely the same as that in Embodiment 2, except that an inert protective gas is provided during the cooling step. The inert protective gas may include nitrogen or argon. The inert protective gas prevents the P-type semiconductor layer 12 from being oxidized.

[0086] Figure 6 This is a schematic diagram of an intermediate structure corresponding to the semiconductor structure fabrication method of the fourth embodiment of the present invention. (Refer to...) Figure 6 As shown, the method for fabricating the semiconductor structure in this embodiment four is roughly the same as the method for fabricating the semiconductor structure in embodiments one, two and three, except that: before step S3, which activates the P-type doped ions in the P-type semiconductor layer 12, the patterned mask layer 13 is removed to expose the P-type semiconductor layer 12 of the gate region 11a.

[0087] With the P-type semiconductor layer 12 of the gate region 11a exposed, H ions can also be released from the top surface of the P-type semiconductor layer 12 to the outside.

[0088] Figure 7This is a schematic diagram of an intermediate structure corresponding to the method for fabricating a semiconductor structure according to the fifth embodiment of the present invention. (Refer to...) Figure 7 As shown, the method for fabricating the semiconductor structure in this embodiment five is largely the same as the method for fabricating the semiconductor structure in embodiments one, two, three, and four, except that it further includes step S4, which uses the patterned mask layer 13 as a mask to grow an N-type semiconductor layer 14 on both sides of the P-type semiconductor layer 12 and on the heterojunction structure 11.

[0089] The N-type semiconductor layer 14 is made of a III-V compound, such as GaN or AlGaN, which are difficult to grow on the patterned mask layer 13. In the AlGaN material, the amount of Al is preferably less than 10%. The N-type semiconductor layer 14 can be achieved by doping the III-V compound with N-type ions, which can be at least one of Si ions, Ge ions, Sn ions, Se ions, and Te ions; since Si ions are present in the epitaxial growth environment, it can also be an unintentionally doped III-V compound.

[0090] The N-type semiconductor layer 14 can provide electron carriers to the heterojunction structure 11, thereby reducing the resistance between the source and drain when they are turned on.

[0091] The patterned mask layer 13 can then be removed to expose the P-type semiconductor layer 12. The patterned mask layer 13 can be removed using wet etching.

[0092] Figure 8 This is a schematic diagram of an intermediate structure corresponding to the method for fabricating the semiconductor structure according to the sixth embodiment of the present invention. (Refer to...) Figure 8 As shown, the method for fabricating the semiconductor structure in this embodiment six is ​​largely the same as the method for fabricating the semiconductor structure in embodiment five, except that in step S4, the N-type semiconductor layer 14 is also grown on top of and on both sides of the patterned mask layer 13.

[0093] The N-type semiconductor layer 14 can be made of AlN, for example, and can be grown on the patterned mask layer 13.

[0094] Then, the patterned mask layer 13 and the N-type semiconductor layer 14 above it can be removed to expose the P-type semiconductor layer 12. The patterned mask layer 13 and the N-type semiconductor layer 14 above it can be removed by dry etching.

[0095] Figure 9 and Figure 10 This is a schematic diagram of an intermediate structure corresponding to the method for fabricating the semiconductor structure according to the seventh embodiment of the present invention. (Refer to...) Figure 9 and Figure 10As shown, the method for fabricating the semiconductor structure in this embodiment seven is largely the same as the method for fabricating the semiconductor structure in embodiments one to six, except that: after step S4 (or after step S3 if step S4 is not performed), a source 15b is formed on the source region 11b, a drain 15c is formed on the drain region 11c, and a gate 15a is formed on the activated P-type semiconductor layer 12.

[0096] Specifically, a metal layer, such as Ti / Al / Ni / Au or Ni / Au, can be formed first by sputtering. The metal layer in areas other than the gate region 11a, source region 11b, and drain region 11c is then removed by etching. High-temperature annealing then forms ohmic contacts between the source 15b and the source region 11b, between the drain 15c and the drain region 11c, and between the gate 15a and the P-type semiconductor layer 12 of the gate region 11a.

[0097] Figure 9 and Figure 10 The difference in the methods for fabricating semiconductor structures lies in: Figure 9 In the middle, both the source electrode 15b and the drain electrode 15c are in contact with the barrier layer 112; Figure 10 In the middle, both the source electrode 15b and the drain electrode 15c are in contact with the channel layer 111.

[0098] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate (10), a heterojunction structure (11), and a P-type semiconductor layer (12) are provided in a bottom-up distribution. A patterned mask layer (13) is formed on the P-type semiconductor layer (12), the patterned mask layer (13) covering at least the gate region (11a) of the P-type semiconductor layer (12); using the patterned mask layer (13) as a mask, the exposed P-type semiconductor layer (12) is removed by in-situ etching with a corrosive gas; the material of the patterned mask layer (13) is silicon dioxide, silicon nitride or silicon oxynitride; After the in-situ etching process removes the exposed P-type semiconductor layer (12), a cooling process is performed; during the cooling process, the supply of the corrosive gas is stopped. Using the patterned mask layer (13) as a mask, the P-type doped ions in the P-type semiconductor layer (12) are activated; After activating the P-type doped ions in the P-type semiconductor layer (12), an N-type semiconductor layer (14) is grown on both sides of the P-type semiconductor layer (12) and on the heterojunction structure (11) using the patterned mask layer (13) as a mask.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The in-situ etching includes the step of forming a patterned mask layer (13) being performed in the same reaction chamber or in a different chamber of the vacuum interconnect device.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The material of the P-type semiconductor layer (12) is GaN. The exposed P-type semiconductor layer (12) is removed by in-situ etching at a temperature higher than 300°C. The corrosive gas includes H2 and / or NH3, or a mixture of Cl2 and N2, or HCl.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, In-situ etching to remove the exposed P-type semiconductor layer (12) is performed at a temperature above 700°C.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The material of the N-type semiconductor layer (14) is GaN or AlGaN.

6. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The material of the heterojunction structure (11) adjacent to the P-type semiconductor layer (12) is AlGaN.

7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, During the cooling step, the supply of the corrosive gas is stopped when the temperature is not lower than 600°C.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, In the cooling step, an inert protective gas is provided.

9. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Activation of the P-type doped ions in the P-type semiconductor layer (12) is achieved by annealing at a temperature greater than 500°C.

10. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Also includes: A source (15b) is formed on the source region (11b), a drain (15c) is formed on the drain region (11c), and a gate (15a) is formed on the activated P-type semiconductor layer (12).

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