System and method for monitoring leakage current

Abstract

The present disclosure relates to systems and methods for monitoring leakage current. A system for monitoring a MOSFET, the system comprising: a switching device configured to switchably isolate a gate terminal of the MOSFET and a source terminal of the MOSFET from a gate control voltage source; and a test circuit configured to detect a change in a gate-to-source voltage of the MOSFET over a test period, the test period occurring while the gate terminal and the source terminal are isolated.

Description

Technical Field

[0001] This invention generally relates to systems and methods for monitoring the health of MOSFETs. Background Technology

[0002] Typically, MOSFETs are used to turn current on and off paths. However, this functionality can degrade over time. In safety-critical applications, this degradation can lead to catastrophic results. Monitoring MOSFET gate leakage can help diagnose potential problems, allowing for preventative measures to be taken before failure occurs. Summary of the Invention

[0003] According to an embodiment of the present invention, a system for monitoring a MOSFET includes a switching device configured to switchably isolate the gate terminal and the source terminal of the MOSFET from a gate-controlled voltage source; and a test circuit configured to detect changes in the gate-to-source voltage of the MOSFET during a test cycle, the test cycle occurring when the gate terminal and the source terminal are isolated.

[0004] According to one embodiment, the system may further include: a gate terminal switch for switchably isolating the gate terminal from the gate-controlled voltage source; and a source terminal switch for switchably isolating the source terminal from the gate-controlled voltage source.

[0005] According to one embodiment, the system further includes a voltage sensing circuit configured to detect the gate-to-source voltage of the MOSFET.

[0006] According to one embodiment, the system further includes a test circuit comprising a sample and hold circuit coupled to the output of a voltage sensing circuit to store a sample voltage equal to the gate-to-source voltage at the sampling time.

[0007] According to one embodiment, the system further includes a voltage subtractor circuit coupled to the output of the voltage sensing circuit and the output of the sample and hold circuit, the voltage subtractor circuit being configured to output the difference between the sample voltage and the gate-to-source voltage.

[0008] According to an embodiment, the system further includes a test sampling and holding circuit configured to store the output of a voltage subtractor circuit at a test time, the difference at the test time being equal to the change in the gate-to-source voltage of the MOSFET over the test cycle.

[0009] According to one embodiment, the system further includes timing circuitry that communicates with the switching device, the sampling and holding circuitry, and the test sampling and holding circuitry to trigger operation of the switching device, the sampling and holding circuitry, and the test circuitry.

[0010] According to one embodiment, a method for monitoring a MOSFET includes floating the gate of the MOSFET; detecting a change in the gate-to-source voltage of the MOSFET; determining a leakage current based on the change in the gate-to-source voltage of the MOSFET; and triggering a warning when the leakage current exceeds a maximum threshold.

[0011] According to one embodiment, the method further includes wherein the gate of the floating MOSFET includes isolating the gate of the MOSFET from the gate driver.

[0012] According to one embodiment, the method further includes detecting a change in the gate-to-source voltage of the MOSFET by sensing a sample voltage of the gate-to-source voltage before the gate of the floating MOSFET is placed, and sensing a test voltage after the gate of the floating MOSFET, wherein the change in the gate-to-source voltage of the MOSFET is equal to the difference between the sample voltage and the test voltage.

[0013] According to one embodiment, the method further includes the MOSFET being in an on state.

[0014] According to one embodiment, the method further includes, wherein the leakage current includes leakage current from the gate of the MOSFET to the source of the MOSFET and leakage current from the gate of the MOSFET to the MOSFET.

[0015] According to one embodiment, the method further includes the MOSFET being in an off state.

[0016] According to one embodiment, the method further includes, wherein the leakage current includes leakage current from the drain of the MOSFET to the source of the MOSFET.

[0017] According to one embodiment, a test circuit for monitoring the leakage current of a MOSFET includes a voltage sensing circuit configured to detect the gate-to-source voltage of the MOSFET; a sample-and-hold circuit coupled to the output of the voltage sensing circuit and configured to store a sample value of the gate-to-source voltage of the MOSFET in the direction of a sampling control signal; a voltage subtractor circuit coupled to the output of the voltage sensing circuit and the output of the sample-and-hold circuit, the voltage subtractor circuit being configured to output the difference between the sample value and the gate-to-source voltage; and a test sample-and-hold circuit configured to store the output of the voltage subtractor circuit in the direction of a test control signal.

[0018] According to one embodiment, the test circuit further includes a voltage sensing circuit comprising a voltmeter.

[0019] According to one embodiment, the test circuit further includes a first comparator configured to receive a first reference voltage and receive the output of a voltage subtractor stored by a test sampling and holding circuit, the first comparator being configured to assert a warning signal in response to the output of the voltage subtractor stored by the test sampling and holding circuit exceeding the first reference voltage.

[0020] According to one embodiment, the test circuit further includes a second comparator configured to receive a second reference voltage and receive the output of a voltage subtractor stored by the test sampling and holding circuit, the second comparator being configured to assert a warning signal in response to the output of the voltage subtractor stored by the test sampling and holding circuit exceeding the second reference voltage.

[0021] According to one embodiment, the test circuit further includes a first reference voltage related to the maximum leakage current of the MOSFET in the on state, and a second reference voltage related to the maximum leakage current of the MOSFET in the off state.

[0022] According to one embodiment, the test circuit further includes a first temperature compensation circuit in communication with a temperature sensor that detects the temperature of the MOSFET, the first temperature compensation circuit being configured to adapt a first reference voltage according to the temperature of the MOSFET.

[0023] According to one embodiment, the test circuit further includes a second temperature compensation circuit in communication with a temperature sensor, the second temperature compensation circuit being configured to adapt a second reference voltage according to the temperature of the MOSFET. Attached Figure Description

[0024] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0025] Figure 1 The leakage current of the MOSFET is shown;

[0026] Figure 2 A system for monitoring MOSFETs according to an embodiment is shown;

[0027] Figure 3 A system for monitoring MOSFETs and test circuitry according to an embodiment is shown;

[0028] Figure 4 An embodiment of the processing circuit according to the embodiment is shown;

[0029] Figure 5 The leakage of a MOSFET in the on state is shown.

[0030] Figure 6 The leakage of a MOSFET in the off state is shown;

[0031] Figure 7 A timing diagram of a system for monitoring the leakage current of a MOSFET in the on-state, according to an embodiment, is shown.

[0032] Figure 8 A timing diagram of a system for monitoring the leakage current of a MOSFET in the off state, according to an embodiment, is shown.

[0033] Figure 9 A timing waveform with a delay according to an embodiment is shown;

[0034] Figure 10 A flowchart of a method for monitoring the leakage current of a MOSFET according to an embodiment is shown;

[0035] Figure 11 A system for monitoring MOSFET leakage according to an embodiment is shown;

[0036] Figure 12 A system for determining temperature compensation is shown; and

[0037] Figure 13 A flowchart illustrating the steps of a method according to an embodiment is shown. Detailed Implementation

[0038] MOSFETs and power MOSFETs are used in many safety-critical environments. For example, power MOSFETs can be used in electronic fuses. Electronic fuses can be used in many different applications, including automotive (and so on). Due to their critical function, electronic fuses may meet stringent safety standards. For example, when incorporated into automotive powertrains, it may be necessary to specify electronic fuses with a high automotive safety integrity level according to ISO 26262 (International Standard for Functional Safety of Electrical and / or Electronic Systems Installed in Road Vehicles). Detecting and managing potential MOSFET failures is important to ensure safety and functionality. In the case of a fuse, a MOSFET can be used to open a current path. If a MOSFET loses its ability to control current, it no longer provides its critical function. Faults in short circuits can severely compromise safety requirements because they may fail to disconnect runaway devices.

[0039] Two major physical degradations in the MOSFET gate structure can lead to serious failures that compromise the MOSFET's ability to control the current path: leakage in the gate oxide and charge trapping in the gate oxide. Monitoring changes in gate leakage allows for early detection of device degradation and prevention of potential failures. Performing such monitoring during device operation can be advantageous.

[0040] Figure 1 The leakage current of the MOSFET is shown.

[0041] System 100 may include a MOSFET 102, which includes a gate terminal 102G, a drain terminal 102D, and a source terminal 102S. MOSFET 102 may be coupled to a gate driver 104 and a controller 106. The drain-to-gate capacitance of MOSFET 102 is defined by C. DG This indicates that the gate-to-source capacitance is determined by C. GS This indicates that, depending on the voltage present at the gate of MOSFET 102, the current ID can flow between the drain and source. It can be understood that during normal operation, the path of current ID can be turned on and off by controlling the voltage supplied to the gate. Generally, for an N-type MOSFET, if the gate-to-source voltage of the MOSFET (V... GS () greater than the MOSFET threshold voltage (V) th If the current ID is short-circuited, the path can conduct electricity. In the case of a fuse, the path for current ID can be disconnected in the event of a short circuit to prevent damage or other malfunctions. The gate driver 104 can provide the gate voltage to the MOSFET 102 in the direction of the controller 106.

[0042] However, leakage can impair the ability of MOSFET 102 to operate as intended. Leakage current can be caused by... Figure 1 Path 108 in the diagram represents leakage. Leakage can reduce the gate threshold required to put the MOSFET into the on state. For example, when the drain-to-source voltage (V) of MOSFET 102... DS When the threshold voltage is exceeded, this voltage can be applied to the gate of MOSFET 102. This can put the MOSFET in the on state, and the controller 106 may lose its ability to put the MOSFET in the off state. When the fuse is operated by relying on this control, the fuse can no longer perform its critical function, and the MOSFET can remain on. Therefore, when needed, the MOSFET will lose its ability to interrupt the circuit. Moreover, this can lead to high temperatures, damage, and a fire hazard.

[0043] These risks can be mitigated by monitoring the gate leakage current of the MOSFET during operation. However, this presents challenges because the leakage current can be very small. The measurement range can fall within nA or even pA. Leakage may be a function of temperature. Furthermore, field-specific measurements are required.

[0044] Figure 2 A system for monitoring MOSFETs according to an embodiment is shown.

[0045] Unless otherwise specified in this disclosure, the same numerical identifiers may be used to identify the same elements in different figures. To avoid redundancy and for the sake of brevity, these elements will not be described for each figure. In various embodiments, the system 200 for monitoring MOSFET 102 may include a switching device 202 and a test circuit 204. MOSFET 102 may include a gate terminal 102G, a source terminal 102S, and a drain terminal 102D. The parasitic capacitance of the MOSFET may be determined by C. GD (Gate and Drain), C GS (gate source) and C DS (Drain-source) modeling. MOSFET 102 can be coupled with power supplies such as V... supply The circuit device 201 is coupled to the load 201A.

[0046] Gate driver 104 can receive a gate control signal and provide an output voltage to drive MOSFET 102. In various embodiments, gate driver 104 can be coupled to gate terminal 102G and source terminal 102S. Gate driver 104 can be controlled by controller 106. Figure 2 (Not shown in the image) Receives control signals.

[0047] In various embodiments, the switching device 202 may be configured to switchably isolate the gate terminal 102G and the source terminal 102S of the MOSFET 102 from a gate-controlled voltage source (such as the gate driver 104). The switching device 202 may receive a control signal 206 that can trigger the switching device 202 to couple or decouple the gate terminal 102G and the source terminal 102S.

[0048] In various embodiments, the switching device 202 may include a gate terminal switch S1 capable of switchingly isolating the gate terminal 102G from the gate-controlled voltage source. The switching device 202 may include a source terminal switch S2 capable of switchingly isolating the source terminal 102S. For example, an assertion control signal 206 may turn on both the gate terminal switch S1 and the source terminal switch S2, thereby isolating the gate terminal 102G and the source terminal 102S from the gate driver 104. It is understood that the switching device 202 may be implemented in a variety of ways. In various embodiments, the switching device 202 may be implemented using a single switch. In various embodiments, separate control signals may be used to turn on both the gate terminal switch S1 and the source terminal switch S2.

[0049] When the gate terminal 102G and source terminal 102S of MOSFET 102 are isolated, the gate of MOSFET 102 can be considered floating. This allows for the measurement of the gate-to-source voltage (V) of MOSFET 102. GSChanges in the ) are advantageous, and can be used to identify leaks.

[0050] Test circuit 204 can be configured to detect the V of MOSFET 102 GS The change in V during the test cycle. Test circuit 204 can determine the change in V during the test cycle. GS The duration of the test cycle can vary in different embodiments. In various embodiments, the duration of the test cycle can be programmable or variable. In various embodiments, the test circuit 204 may include a positive terminal IN+ and a negative terminal IN-. The positive terminal IN+ may be coupled to the gate terminal 102G and the negative terminal IN- may be coupled to the source terminal 102S to allow V GS The test circuit 204 can also receive one or more control signals 208. These control signals can determine when to start the test and can also be used to end the test. As will be understood, the test circuit 204 can be implemented in various ways in various embodiments.

[0051] Figure 3 A system and test circuit for monitoring MOSFETs according to an embodiment are shown.

[0052] In various embodiments of system 200, test circuit 204 may include voltage sensing circuit 302. Voltage sensing circuit 302 may be configured to detect the gate-to-source voltage of MOSFET 102. For example, voltage sensing circuit 302 may include a voltmeter. Voltage sensing circuit 302 may be coupled to gate terminal 102G at positive terminal IN+ and to source terminal at negative terminal IN-. Voltage sensing circuit 302 may provide the gate-to-source voltage V of MOSFET 102 at output 302A. GS .

[0053] In various embodiments, the voltage sensing circuit 302 may include a memory 304 to store V. GS The sample value. For example, V can be set at the start of a leak test. GS Sampling is performed to compare with V detected at a later time. GS The values ​​will be compared later. Sample V GS Value and Test V GS The difference between values ​​can be called V. GS Change (ΔV) GS )

[0054] In various embodiments, memory 304 may include sample-and-hold circuitry. Memory 304 may receive control signal 208A to determine when to store sample V. GS The memory 304 may include an input terminal 304A to receive V from the voltage sensing circuit 302. GSThe memory 304 may also include an input terminal 304B to receive control signals 208A. (Sample V) GS It can be provided to output 304C.

[0055] In stored sample V GS Then, it can be used as a reference frame to calculate V during the test cycle. GS The change. For example, V GS It can be resampled, and the difference can be used as V. GS Change (ΔV) GS As will be understood, various embodiments can be implemented to determine ΔV. GS Different methods. This can be achieved using digital or analog circuit devices.

[0056] In various embodiments, the test circuit 204 may include a voltage subtractor 306 coupled to the output 302A of the voltage sensing circuit and the output 304C of the memory 304. The voltage subtractor 306 circuit is configured to output a sample voltage V. GS The difference between the current level and the gate-to-source voltage.

[0057] Test circuit 204 may also include another sample-and-hold circuit, test sample-and-hold circuit 308, for storing the output of voltage subtractor 306 at a test time. Test sample-and-hold circuit 308 may include input 308A to receive the output of voltage subtractor 306. Test sample-and-hold circuit 308 may also include input 308B to receive control signal 208B. Control signal 208B can determine when to store the output of voltage subtractor 306. The value stored at this time may include ΔV GS(test) The difference at the test time can be equal to the change in the gate-to-source voltage of MOSFET 102 during the test cycle. This value can be provided to output 308C. Timing circuit 312 can coordinate the operation of switching device 202, the storage of sample VGS in memory 304, and ΔV GS(test) The data is stored in the test sample and hold circuit 308. In various embodiments, the timing circuit 312 may provide control signals 206, 208A, and 208B.

[0058] Once ΔV is determined GS (TEST) can then be provided to other circuit devices for additional processing. ΔV GS (TEST) can be used to calculate leakage current I. Leakage It is understandable that the calculations can differ depending on whether the gate control is on or off. When the gate control is on, the equation for calculating the leakage current is provided by Equation 1.

[0059]

[0060] In equation 1, I Leakage This represents the sum of gate-to-source leakage (GS) and gate-to-drain leakage (GD). ΔV GS (TEST) is the sample V GS and test V GS The difference between them. And C GS +C GD It is the sum of the gate-to-source capacitance and the gate-to-drain capacitance. T Open Gate It is the time when the gate terminal 102G and the source terminal 102S have been isolated by the switching device 202.

[0061] The equation for calculating the leakage current when the gate control is on is provided by Equation 2.

[0062]

[0063] In the equation, I Leakage This indicates leakage from the drain to the source.

[0064] In various embodiments, system 200 may further include processing circuitry 310. The processing circuitry may receive ΔV at input 310A. GS (TEST). The processing circuit 310 may also receive a gate control signal at input 310B. The processing circuit 310 may include a non-transient computer-readable medium storing instructions to calculate the leakage current according to Equation 1 or Equation 2 based on whether the MOSFET is in an on or off state (as determined by the gate control signal). In various embodiments, measured values ​​from measurements may be stored to indicate trends in leakage current. The processing circuit 310 may be implemented using circuitry embedded in the device or via an external, independent processor.

[0065] Figure 4 An embodiment of the processing circuit according to the embodiment is shown.

[0066] In various embodiments, the processing circuitry 310 may include a non-transient computer-readable storage 311 to store a set of instructions that enable the processing circuitry 310 to determine the leakage current according to Equations 1 and 2 based on whether the MOSFET is on or off.

[0067] As mentioned, system 200 can be used to monitor leakage of MOSFET 102 when it is in the on or off state.

[0068] Figure 5 The leakage of a MOSFET in the on state is shown.

[0069] To keep the MOSFET in the on state, the gate driver 104 can polarize the gate of the MOSFET 102 with the voltage required for MOSFET saturation (switching device 202 is in the closed state), so that the MOSFET can have a sufficiently low (≈0) V0. DS ON activates the load. This can be achieved by monitoring the gate voltage change ΔV. GS (T TEST The leakage in the gate oxide of the MOSFET is measured by turning on the switching device 202 for a certain period of time to float the gate. When the gate is floating, no current flows outside the MOSFET structure, so the change in gate voltage may be related to the current flowing into the MOSFET, which discharges the capacitance of the gate oxide itself. The leakage from the gate to the drain of the MOSFET (Id) is measured. Leakage GD) and from the gate to the source of the MOSFET (I Leakage Current leakage may occur in GDS. This is because the MOSFET is turned on and V... DS Since ON≈0, the current can originate from the gate-to-source oxide, the gate-to-drain oxide, or both.

[0070] This internal leakage current can discharge the gate oxide capacitor, and Equation 1 can be used to calculate ΔV. GS (T TEST The leakage test measures the gate voltage (V) of the MOSFET. This test can be performed during MOSFET operation. The leakage test does not interfere with load activation because, under normal operating conditions, the gate voltage will remain constant and the MOSFET V... DS ON remains unchanged. In various embodiments, the timing of the leakage test can be selected to limit gate voltage variations to a low value that is fully compatible with MOSFET turn-on. For example, the test period during which the switching device 202 holds the gate in a floating state can be selected to include a duration that does not affect the operation of the MOSFET. Furthermore, the gate can be overdriven with a slightly higher voltage to compensate for the final gate voltage variation caused by the leakage test. Because the gate will discharge according to charge Q = ∫i(t)dt, the leakage test can also be used to address non-constant leakage current.

[0071] Figure 6 The leakage of a MOSFET in the off state is shown.

[0072] To keep the MOSFET off, the gate driver 104 can polarize the MOSFET gate (switch 202 is closed) using the voltage required for the MOSFET to be off, which is 0, so that the MOSFET cannot activate the load and V DS =V supply. In this state, the gate voltage change ΔV can be measured.GS (T TEST ) to measure leakage in the gate oxide while the gate is floated by opening the switching device 202 for a test period of time. When the gate is floated, no current may flow from outside the MOSFET into the gate-source pin, so the change in gate voltage may be related to the current flowing into the MOSFET. The potential current from the drain to the gate can charge the capacitance of the gate-source oxide. Since the power MOSFET is off, the drain is polarized such that VDS=Vsupply and the current can originate from the drain to the gate oxide. It should be noted that no current leaks from the gate to the source because they are at the same voltage.

[0073] This internal leakage current can charge the gate-source oxide capacitance, and Equation 2 can be used to calculate ΔV GS (T TEST ) as a function of leakage. The test operation can be performed without affecting load activation, because under normal operating conditions, the gate voltage will remain constant (equal to zero) and the state of the MOSFET will not change. The timing of the leakage test (the time period during which the gate remains floated) can also be selected so as to limit the gate voltage change to a low value compatible with the off-state of the MOSFET (V GS <VTH). As mentioned when discussing the on-state, in the case of non-constant leakage current, the method can still be used, because the gate capacitance will be charged according to the charge Q=∫i(t)dt. When in the off-state, it can be verified that the leakage is caused by leakage in the oxide drain-source of the MOSFET. This may be useful if leakage is detected in the on-state. When the MOSFET is in the off-state, another test can be performed to determine whether leakage occurs in the oxide gate-source or oxide gate-drain.

[0074] Figure 7 shows a timing diagram of a system for monitoring leakage current of a MOSFET in an on-state according to an embodiment.

[0075] In various embodiments, timing signals can be used to trigger the operation of the system 200. An example waveform of a test signal for monitoring leakage during the on-state of a MOSFET can include a test enable signal. The test enable signal can initiate the leakage test. In various embodiments, the test enable signal can be received by the timing circuit 312 at the test enable input 312A (as depicted in Figure 3 ). Additional timing signals can also include a sampling V GS signal, which can enable the gate-source voltage of the MOSFET 102 to be sampled (and stored). In various embodiments, the sample V GSIt can be carried on the control signal 208A from the timing circuit 312 and provided to the input terminal 304B of the memory 304 so that the memory stores the gate-source voltage value at this time as the sample gate-source voltage.

[0076] The disconnect / connect gate signal can operate the switching device 202. For example, when the disconnect / connect gate signal is asserted, the switching device 202 can isolate the gate terminal 102G and the source terminal 102S. When the assertion is de-asserted, the switching device 202 can cancel the isolation between the gate terminal 102G and the source terminal 102S.

[0077] Additional timing signals may include a test leakage signal. When asserted, the test leakage signal can cause the system to store ΔV. GS The value of . In other words, the time between the disconnection of the switching device 202 (the assertion of the disconnection / connection of the gate signal) and the assertion of the test leakage signal can be T. OPEN GATE In various embodiments, the disconnect / connect gate signal can be carried to input 202A by control signal 206. The test leakage signal can be received at input 308B by sample-and-hold circuit 308 and carried on control signal 208B.

[0078] For example, at time T0, the gate can be polarized relative to the source to the turn-on voltage V. GSON At time T1, the test enable signal can be asserted. This allows sampling V... GS The signal is asserted, which allows memory 304 to set V at that time. GS Store as V GS (Sample). At time T2, the disconnect / connect gate can be asserted, thus making the gate float. In various embodiments, a delay may exist between T1 and T2 to allow storage of V. GS (Sample) and resolve any internal delays. V GS The voltage may begin to decrease due to any current leakage. After a duration of the desired length, the leakage signal can be asserted at T3. V at time T3 GS With V GS The difference between (Samples) can be stored as ΔV. GS (TEST), which can then be used to determine the leakage current. At time T4, the disconnect / connect gate signal can be deasserted, and the gate can be recoupled to gate driver 104. V GS Can be restored to V GS ON. The time period between T2 and T3 can be considered as the time period for measuring the change in leakage current, and is used as T.OPEN GATE .

[0079] Figure 8 A timing diagram of a system for monitoring the leakage current of a MOSFET in the off state, according to an embodiment, is shown.

[0080] Test enable, sample V GS The disconnect / connect gate signal can operate in the same way, regardless of whether the MOSFET is on or off. At T0, V GS Can remain at V GS OFF. At time T1, the test enable signal can be asserted. In response, the sampled V can also be asserted. GS This could cause the memory to store V. GS (Sample). When the MOSFET is in the off state, V GS It can be equal to zero. This is after V has already been stored. GS After (Sample), an assertion can be made at time T2 to disconnect / connect the gate signal. In various embodiments, a delay may exist between T1 and T2 to allow storage of V. GS (Sample) and resolves any internal delays. After the disconnect / connect gate signal is asserted, the gate may become floating due to the operation of switching device 202. See reference Figure 6 As discussed, when the MOSFET is in the off state, the capacitance of the gate-source oxide can be charged through leakage. Therefore, when the gate is floating, V GS The value may increase. After the expected time period, the leakage signal can be asserted at time T3, and ΔV can be stored. GS (Test). At time T4, the disconnect / connect gate can be deasserted, and the gate and source can be coupled to gate driver 104. V GS It can return to zero. The time period between T2 and T3 can be considered as the time period for measuring the change in leakage current, and is used as T. OPEN GATE .

[0081] In various embodiments, a delay can be utilized so that when storing V GS (Sample) V GS The value is stable. This can be advantageous because there may be time to raise or lower the voltage level to V after the assertion of the gate control signal. GS ON or V GSOFF. It is understood that gate driver 104 can receive a gate control signal that determines the output voltage provided by gate driver 104. Gate driver 104 can receive the gate control signal at input 104A (see...). Figure 2 The gate control signal interval changes according to the desired state (on or off) of MOSFET 102. Furthermore, the gate driver 104 can respond by providing a corresponding voltage output. However, there may be a hysteresis between the assertion of the gate control signal and the completion of the MOSFET state transition. Introducing a delay period after the gate control change may be beneficial, so that when sampled, V... GS It is stable.

[0082] Figure 9 A timing waveform with a delay is shown according to an embodiment.

[0083] The gate control signal can be asserted at time T0. In response, VGS can start from V GS The shutdown state transitions to V. GS On state. V GS A stable conduction value can be reached at time T2. However, at time T1, the test enable signal can be asserted. However, because the test enable signal asserted at time T1 occurs during the delay period between T0 and T2, the leakage test can be stopped. At time T3, the test enable signal can be asserted again, thereby triggering a leakage test on the MOSFET in the ON state. VGS can decrease as a function of any leakage current. When the MOSFET is in the ON state at times T4 and T5, an additional leakage test can be initiated by the test enable signal. At time T6, the gate control state can be switched, thereby transitioning the MOSFET from the ON state to the OFF state. At time T8, VGS can stabilize at VGS-OFF. Simultaneously, at time T7, the test enable signal can be asserted. However, because T7 falls between T6 and T8, the leakage test can be prevented. After the delay period ends, at times T9 and T1, the test enable signal can be asserted again. 10 and T 11 The shutdown state leakage test begins at this point. When the shutdown state leakage test is performed, V GS This can be added when the gate is floating, as per the reference. Figure 6 The discussion.

[0084] In various embodiments, the gate control provided to the gate driver 104 can also be provided to the timing circuit 312 for communication during the transition from the on state to the off state. The timing circuit can receive the gate control signal (e.g., at input 312B) at input 312B. Figure 3(As shown). The timing circuit 312 can then delay the initiation of the leakage test until the delay period has elapsed. In various embodiments, the delay period can be determined based on stabilizing the MOSFET at V. GS On or V GS The time required for shutdown varies. In various embodiments, leakage testing can be initiated once the delay period has elapsed after the test enable signal has been asserted. In various embodiments, a gate control signal may also be provided at input 310B to the processing circuitry 310 to convey the state of the MOSFET (on or off).

[0085] Figure 10 A flowchart of a method for monitoring the leakage current of a MOSFET according to an embodiment is shown.

[0086] In various embodiments, a method for monitoring the leakage current of a MOSFET may include initiating a leakage current test at step 1002. At step 1004, a test enable signal may be asserted. In various embodiments, this may include setting the test enable signal to "1". As step 1006, it may be determined whether a delay is required. This may depend on the most recent transition of the MOSFET from one state (off or on) to another. If not within a delay period, method 1000 may include reading V at step 1008. GS And V GS The value is stored as sample V GS At step 1010, the MOSFET gate can be isolated from the gate driver. At step 1012, the method may include waiting for T to equal... OPEN GATE The period. In T OPEN GATE After passing, V can be read again. GS At step 1016, the gate can be recoupled to the gate driver. At step 1018, the state of the MOSFET can be determined. In various embodiments, this can be determined based on the gate control signal.

[0087] If the MOSFET is in the off state, method 1000 can proceed to step 1019. At step 1019, ΔV can be determined. GS(Test) Furthermore, at step 1021, ΔV can be used. GS(Test) To determine leakage in a MOSFET that is in the off state.

[0088] If the MOSFET is in the ON state, method 1000 can proceed to step 1020. At step 1020, ΔV can be determined. GS(Test) Furthermore, at step 1022, ΔV can be used. GS(Test)To determine the leakage of a MOSFET that is in the on state.

[0089] At step 1024, the leakage current can be stored. In various embodiments, the leakage current can be compared with a reference, and an assertion warning can be issued if the leakage current exceeds the reference voltage. In various embodiments, additional actions can be taken based on the leakage current. In some embodiments, the leakage current can be determined from ΔV before the comparison. GS(Test) Determine the current.

[0090] In various embodiments, ΔV can be GS(Test) Compare with a reference voltage to determine whether to issue an assertion warning.

[0091] Figure 11 A system for monitoring MOSFET leakage according to an embodiment is shown.

[0092] System 200 may include a first reference voltage generator 1102 and a second reference voltage generator 1104. The first reference voltage generator 1102 can generate a reference voltage associated with maximum gate-source and gate-drain leakage. When the MOSFET is in the on state, this reference voltage can be used in conjunction with ΔV GS(Test) A comparison is performed. The output of the first reference voltage generator 1102 can be coupled to the first comparator 1106. In various embodiments, the system may also include a temperature compensation circuit 1105 and a temperature sensor 1101. The temperature sensor 1101 can detect the temperature at or near the MOSFET 102. And, based on the detected temperature, the temperature compensation circuit 1105, which can communicate with the first reference voltage generator 1102 and the temperature sensor 1101, can output a compensated reference voltage. The first comparator 1106 can receive the compensated reference voltage and ΔV. GS(Test) The first comparator 1106 can generate an indication ΔV. GS(Test) When does the signal exceed the compensation reference voltage? For example, when ΔV GS(Test) When the voltage exceeds the compensation reference voltage, the output 1106A of the first comparator may go high.

[0093] The second reference voltage generator 1104 can generate ΔV associated with drain-to-gate leakage. GS(Test) The reference voltage associated with the maximum change in MOSFET value. This reference voltage can be used in conjunction with a leakage test performed during the MOSFET's off-state. The reference voltage provided by the second reference voltage generator 1104 can be provided to the temperature compensation circuit 1107. The temperature compensation circuit 1107 adjusts the reference voltage based on the temperature sensed by the temperature sensor 1101 and outputs the compensated reference voltage to the comparator 1108. The comparator 1108 can also receive ΔV GS(Test) And an indication ΔV is provided at output 1108A.GS(Test) The signal indicating when the current exceeds the compensated reference voltage. Outputs 1106A and 1108A (when asserted) can trigger warnings or other actions in response to determining that the current has exceeded the expected level.

[0094] In various embodiments, temperature compensation can be achieved using a lookup table addressed by the output of a thermal sensor. The address values ​​of the lookup table can define a multiplication factor and the measured values ​​are normalized to a defined temperature (e.g., 25°C) via a digital multiplier. An A / D converter can be used to convert analog measurements into digital values ​​for temperature compensation, and it can also be applied to leak measurements.

[0095] Figure 12 A system for determining temperature compensation is shown.

[0096] System 1200 may include a first A / D converter 1202 and a second A / D converter 1204. The first A / D converter can receive ΔV GS(TEST The first A / D converter 1202 and the second A / D converter 1204 can receive data from the temperature sensor 1101. The first A / D converter 1202 and the second A / D converter 1204 can convert their respective inputs into digital data. The digital data from the first A / D converter can be used by the processing circuit 310 with the leakage calculator 1206 to determine the leakage current. The temperature calculator 1208 of the processing circuit 310 can use the sensor data provided by the temperature sensor 1101 from the output of the second A / D converter 1204 to determine the temperature. Temperature compensation can then be performed at 1210 for a given leakage current and temperature using a lookup table or other process.

[0097] As will be understood, the reference voltages generated by the first reference voltage generator 1102 and the second reference voltage generator 1104 may differ in different embodiments. Equation 3 provides an example of determining the value of the reference voltage associated with the maximum leakage from the gate to the source and from the gate to the drain.

[0098]

[0099] In Equation 3, Max I Leakage It is the expected maximum leakage from gate to source and from gate to drain, which can be associated with a leakage test performed when the MOSFET is in the on state.

[0100] Equation 4 provides an example of determining the value of a reference voltage associated with the maximum leakage from the drain to the gate.

[0101]

[0102] In Equation 3, Max I LeakageIt is the expected maximum leakage from the drain to the gate, which can be associated with a leakage test performed when the MOSFET is in the off state.

[0103] When the MOSFET is in the on or off state, V GS Measurements can occur.

[0104] Figure 13 A flowchart illustrating the steps of a method according to an embodiment is shown.

[0105] In various embodiments, the method 1300 for monitoring a MOSFET may include, at step 1302, floating the gate of the MOSFET; at step 1304, detecting a change in the gate-to-source voltage of the MOSFET; at step 1306, determining a leakage current based on the change in the gate-to-source voltage of the MOSFET; and at step 1308, triggering a warning when the leakage current exceeds a maximum threshold.

[0106] In various embodiments, method 1300 may further include wherein floating the gate of the MOSFET includes isolating the gate of the MOSFET from the gate driver.

[0107] In various embodiments, method 1300 may further include, wherein detecting a change in the gate-to-source voltage of the MOSFET includes sensing a sample voltage of the gate-to-source voltage before the gate of the floating MOSFET is placed, and sensing a test voltage after the gate of the floating MOSFET is placed, wherein the change in the gate-to-source voltage of the MOSFET is equal to the difference between the sample voltage and the test voltage.

[0108] In various embodiments, method 1300 may further include the MOSFET being in an on state.

[0109] In various embodiments, method 1300 may further include, wherein the leakage current includes leakage from the gate of the MOSFET to the source of the MOSFET and leakage from the gate of the MOSFET to the drain of the MOSFET.

[0110] In various embodiments, method 1300 may further include the MOSFET being in a turned-off state.

[0111] In various embodiments, method 1300 may further include, wherein the leakage current includes leakage from the drain of the MOSFET to the source of the MOSFET.

[0112] It should be understood that this disclosure is not limited to specific features or MOSFETs, and leakage current can be tested for P-type MOSFETs with opposite polarities.

[0113] Example 1. A system for monitoring a MOSFET, the system comprising a switching device configured to switchably isolate the gate terminal and the source terminal of the MOSFET from a gate-controlled voltage source; and a test circuit configured to detect a change in the gate-to-source voltage of the MOSFET during a test period, the test period occurring when the gate terminal and the source terminal are isolated.

[0114] Example 2. The system according to Example 1, wherein the switching device includes a gate terminal switch and a source terminal switch, the gate terminal switch being capable of switchingly isolating the gate terminal from the gate-controlled voltage source, and the source terminal switch being capable of switchingly isolating the source terminal from the gate-controlled voltage source.

[0115] Example 3. The system according to Examples 1 and 2, wherein the test circuit includes a voltage sensing circuit configured to detect the gate-to-source voltage of the MOSFET.

[0116] Example 4. The system according to Examples 1 to 3, wherein the test circuit includes a sampling and holding circuit coupled to the output of the voltage sensing circuit to store a sample voltage equal to the gate-to-source voltage at the sampling time.

[0117] Example 5. The system according to Examples 1 to 4, wherein the test circuit further includes a voltage subtractor circuit coupled to the output of the voltage sensing circuit and the output of the sample and hold circuit, the voltage subtractor circuit being configured to output the difference between the sample voltage and the gate-to-source voltage.

[0118] Example 6. The system according to Examples 1 to 5 further includes a test sampling and holding circuit configured to store the output of the voltage subtractor circuit at a test time, the difference at the test time being equal to the change in the gate-to-source voltage of the MOSFET over the test period.

[0119] Example 7. The system according to Examples 1 to 6 further includes a timing circuit that communicates with the switching device, the sampling and holding circuit, and the test sampling and holding circuit to trigger operation of the switching device, the sampling and holding circuit, and the test circuit.

[0120] Example 8. A method for monitoring a MOSFET, comprising: floating the gate of the MOSFET; detecting a change in the gate-to-source voltage of the MOSFET; determining a leakage current based on the change in the gate-to-source voltage of the MOSFET; and triggering a warning when the leakage current exceeds a maximum threshold.

[0121] Example 9. The method according to embodiment 8, wherein floating the gate of the MOSFET includes isolating the gate of the MOSFET from the gate driver.

[0122] Example 10. The method according to Examples 8 and 9, wherein detecting the change in the gate-to-source voltage of the MOSFET comprises: sensing a sample voltage of the gate-to-source voltage before floating the gate of the MOSFET, and sensing a test voltage after floating the gate of the MOSFET, the change in the gate-to-source voltage of the MOSFET being equal to the difference between the sample voltage and the test voltage.

[0123] Example 11. The method according to Examples 8 to 10, wherein the MOSFET is in the ON state.

[0124] Example 12. The method according to Examples 8 to 11, wherein the leakage current includes leakage from the gate of the MOSFET to the source of the MOSFET and leakage from the gate of the MOSFET to the drain of the MOSFET.

[0125] Example 13. The method according to Examples 8 to 12, wherein the MOSFET is in the off state.

[0126] Example 14. The method according to Examples 8 to 13, wherein the leakage current includes leakage from the drain of the MOSFET to the source of the MOSFET.

[0127] Example 15. A test circuit for monitoring leakage current of a MOSFET, the test circuit comprising: a voltage sensing circuit configured to detect a gate-to-source voltage of the MOSFET; a sample-and-hold circuit coupled to an output of the voltage sensing circuit and configured to store a sample value of the gate-to-source voltage of the MOSFET in the direction of a sampling control signal; a voltage subtractor circuit coupled to the output of the voltage sensing circuit and the output of the sample-and-hold circuit, the voltage subtractor circuit being configured to output the difference between the sample value and the gate-to-source voltage; and a test sample-and-hold circuit configured to store the output of the voltage subtractor circuit in the direction of a test control signal.

[0128] Example 16. The test circuit according to Example 15, wherein the voltage sensing circuit includes a voltmeter.

[0129] Example 17. The test circuit according to Examples 15 and 16 further includes a first comparator configured to receive a first reference voltage and receive the output of the voltage subtractor stored by the test sample and hold circuit, the first comparator being configured to assert a warning signal in response to the output of the voltage subtractor stored by the test sample and hold circuit exceeding the first reference voltage.

[0130] Example 18. The test circuit according to Examples 15 to 17 further includes a second comparator configured to receive a second reference voltage and receive the output of the voltage subtractor stored by the test sample and hold circuit, the second comparator being configured to assert a warning signal in response to the output of the voltage subtractor stored by the test sample and hold circuit exceeding the second reference voltage.

[0131] Example 19. A test circuit according to Examples 15 to 18, wherein the first reference voltage is related to the maximum leakage current of the MOSFET in the on state, and the second reference voltage is related to the maximum leakage current of the MOSFET in the off state.

[0132] Example 20. The test circuit according to Examples 15 to 19 further includes a first temperature compensation circuit in communication with a temperature sensor that detects the temperature of the MOSFET, the first temperature compensation circuit being configured to adapt the first reference voltage according to the temperature of the MOSFET.

[0133] Example 21. The test circuit according to Examples 15 to 20 further includes a second temperature compensation circuit in communication with the temperature sensor, the second temperature compensation circuit being configured to adapt the second reference voltage according to the temperature stated by the MOSFET.

[0134] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art based on the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A system for monitoring a MOSFET, the system comprising: Switching device, including: A gate terminal switch is arranged between the gate terminal of the MOSFET and the gate driver to switchably isolate the gate terminal from the gate-controlled voltage source; A source terminal switch, disposed between the source terminal of the MOSFET and the gate driver, to switchably isolate the source terminal from the gate-controlled voltage source; and A test circuit configured to detect the change in the gate-to-source voltage of the MOSFET during a test period by detecting a sample voltage of the gate-to-source voltage of the MOSFET during a sampling time before the gate terminal and the source terminal are isolated, and by detecting a test voltage of the gate-to-source voltage of the MOSFET after the gate terminal and the source terminal are isolated.

2. The system of claim 1, wherein the test circuit includes a voltage sensing circuit configured to detect the gate-to-source voltage of the MOSFET.

3. The system of claim 2, wherein the test circuit includes a sample and hold circuit coupled to the output of the voltage sensing circuit to store the sample voltage equal to the gate-to-source voltage during the sampling time.

4. The system of claim 3, wherein the test circuit further comprises a voltage subtractor circuit coupled to the output of the voltage sensing circuit and the output of the sample and hold circuit, the voltage subtractor circuit being configured to output the difference between the sample voltage and the gate-to-source voltage.

5. The system of claim 4, further comprising a test sampling and holding circuit configured to store the output of the voltage subtractor circuit during a test time, the difference in the test time being equal to the change in the gate-to-source voltage of the MOSFET during the test period.

6. The system of claim 5, further comprising a timing circuit in communication with the switching device, the sampling and holding circuit, and the test sampling and holding circuit to trigger operation of the switching device, the sampling and holding circuit, and the test circuit.

7. A method for monitoring a MOSFET, comprising: Operate the gate switch and source switch to float the gate of the MOSFET; The change in the gate-to-source voltage of the MOSFET is detected by sensing a sample voltage of the gate-to-source voltage of the MOSFET before the gate of the MOSFET is floated and a test voltage of the gate-to-source voltage of the MOSFET after the gate of the MOSFET is floated. The leakage current is determined based on the change in the gate-to-source voltage of the MOSFET; as well as A warning is triggered when the leakage current exceeds the maximum threshold. The gate switch is disposed between the gate and the gate driver of the MOSFET, and the source switch is disposed between the source and the gate driver of the MOSFET.

8. The method of claim 7, wherein floating the gate of the MOSFET includes isolating the gate of the MOSFET from the gate driver.

9. The method of claim 7, wherein the change in the gate-to-source voltage of the MOSFET is equal to the difference between the sample voltage and the test voltage.

10. The method of claim 9, wherein the MOSFET is in the ON state.

11. The method of claim 10, wherein the leakage current includes leakage from the gate of the MOSFET to the source of the MOSFET and leakage from the gate of the MOSFET to the drain of the MOSFET.

12. The method of claim 9, wherein the MOSFET is in an off state.

13. The method of claim 12, wherein the leakage current comprises leakage from the drain of the MOSFET to the source of the MOSFET.

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