A method for FPGA dynamic reconfiguration for radar systems

Abstract

The present application relates to the technical field of radar signal processing, and particularly relates to a FPGA dynamic reconfiguration method for a radar system, which can improve the flexibility of FPGA development in radar signal processing and reduce the resource consumption of FPGA. The present application improves the flexibility of FPGA development in radar signal processing and reduces the resource consumption of FPGA through the partial reconfiguration capability of FPGA, thereby reducing the FPGA capacity required in a complete radar system to reduce the cost. Not only the hardware interface is set as a static area, but also the common steps of algorithm modules are refined and then set as static modules, so that compared with the prior art, the size of the configuration file of partial reloading can be reduced, the time overhead of partial reconfiguration is reduced, and the real-time performance of partial reconfiguration is improved, so that the present application can be better applied in a radar system with strong real-time performance.

Description

Technical Field

[0001] This invention relates to the field of radar signal processing technology, and more specifically to an FPGA dynamic reconfiguration method for radar systems. Background Technology

[0002] Currently, most FPGA partial reconfiguration technologies are based on Xilinx FPGA chips and use tools such as PlanAhead or Vivado. When dividing the static and dynamic areas, these technologies are task-based, meaning only the hardware interfaces are designated as the static area, while the entirety of specific tasks that do not operate simultaneously are designated as the dynamic area. Existing technologies place only the hardware interfaces in the static area of ​​the radar system. This leads to redundant configuration of common subtasks between different radar tasks, resulting in a larger dynamic configuration area and increased dynamic reconfiguration time, which is detrimental to the rapid switching of the radar system between tasks.

[0003] Currently, some reconfigurable radar systems divide the hardware interface into static areas, based on the tasks that can be time-division multiplexed by the FPGA. In radar systems, different tasks often share the same sub-tasks, such as linear frequency modulated signals (LFM signals). Figure 1 ) and frequency step signal ( Figure 2 Both tasks located in the dynamic region have two subtasks: digital down-conversion and inverse FFT. Therefore, reconfiguration of these two subtasks is unnecessary. However, radar systems are highly real-time systems; excessive switching overhead between different tasks significantly reduces the application scope of some reconfigurations. The size of the dynamic region directly affects the switching overhead between different tasks. Therefore, existing reconfiguration methods that use the entire task as a granularity suffer from the technical drawback of excessive switching overhead between tasks. Summary of the Invention

[0004] In view of this, the present invention proposes a partial FPGA reconfiguration method for radar systems, which can improve the flexibility of FPGA development in radar signal processing and reduce FPGA resource consumption.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows: A dynamic reconfiguration method for FPGAs in radar systems includes the following steps: Step 1: Implement the hardware interfaces required by the radar system, standardize its external interfaces, and allocate them to the static area; Step 2: Based on the functions of the radar system, determine the implementation methods for various working modes and decompose them into sub-tasks. Step 3: Compare the subtasks of each working mode in Step 2, and implement their common subtasks as dynamically configurable. Step 4: Based on various working modes and the static processing modules implemented in Step 3, write the processing state machine and data path for each module, and implement the subtasks that cannot be processed in the static module separately and divide them into the dynamic area; through the control state machine of the dynamic area, the data path connects the various hardware interface modules and processing modules in the static area, and implements the processing modules that are not in the static area in the dynamic area. Step 6: During operation, configure the dynamic zone function according to the working mode through the FPGA configuration interface and the processor configuration interface, and send the corresponding static zone processing module parameters to realize the dynamic switching of radar functions.

[0006] In step 1, the specific division method is as follows: DDR interface: It uses the AXI Full interface form in the Xilinx memory interface IP core, and then uses the Xilinx AXI Datamover IP core to convert the AXI Memory Map interface into two bidirectional data stream AXI Stream interface and control flow AXI Stream interface. PCIe interface: Uses Xilinx XDMA IP core and configures it in AXI Stream interface mode, enabling the three base address register spaces BAR0, BAR1 and BAR2. BAR0 is an AXI Lite interface, used to configure the parameters of each IP in the FPGA or read and write single data through the host. BAR1 is a bidirectional AXI Stream interface, used for uploading and downloading large amounts of data between the FPGA and the host computer. BAR2 is an AXI Full interface, used for the host computer to quickly read and write the RAM inside the FPGA and send batch data. ADC and DAC interfaces: The ADC is encapsulated as an AXI Stream Master interface, and the DAC is encapsulated as an AXI StreamSlave interface.

[0007] In step 2, in the PD working mode of the radar system, the raw ADC data is input and then subjected to orthogonal downconversion and time-domain matched filtering; in the LFM working mode, the raw ADC data is input and then subjected to orthogonal downconversion and pulse compression, wherein pulse compression is divided into three sub-processes: Fourier transform, complex multiplication, and inverse Fourier transform; in the LFMCW working mode, the raw ADC data is input and then subjected to orthogonal downconversion, windowing, and Fourier transform, wherein the windowing operation is the same as the complex multiplication operation.

[0008] In step 3, parameters are configured through registers and standardized interfaces are used.

[0009] In step 3, their common subtasks include: orthogonal downconversion, Fourier transform, inverse Fourier transform, and complex multiplication; they are implemented as general-purpose modules with AXI Lite configuration ports and AXI Stream input / output interfaces. The quadrature downconverter module consists of a cascaded digital frequency synthesis module with adjustable frequency, a complex multiplication module, and a low-pass filter module with adjustable passband. The frequency of the DDS and the passband range of the LPF are configured through the AXI Lite bus, thereby adjusting the function of the DDC. The Fourier transform and inverse Fourier transform modules are implemented by instantiating the Xilinx FFT IP core. The number of FFT points is set according to the maximum number of points required in the entire radar system. The runtime configurable options in the IP core are selected, and finally, its configuration interface is encapsulated from the AXI Stream interface into the AXI Lite interface. Through the AXI Lite interface, the FFT IP core can be configured to perform Fourier transform or inverse Fourier transform with the corresponding number of points. The complex multiplication module calls the Xilinx floating-point operation IP core and encapsulates it into a floating-point complex multiplication module according to the complex multiplication operation rules (a+bi)×(c+di)=(ac-bd)+(ad+bc)i. The external interface is the AXI Stream interface.

[0010] For the PD working mode in step 2, the control state machine and data path are as follows: Data is read from the ADC interface according to the enable signal and sent to the quadrature downconversion module. The data output from the quadrature downconversion is then input to the time-domain matched filter module in the dynamic zone. Finally, the processing result is cached in DDR, waiting for the host computer to retrieve data from DDR and send it to PCIe. For the LFM working mode in step 2, the control state machine and data path are as follows: Data is read from the ADC interface according to the enable signal and sent to the quadrature downconversion module. The data output from the quadrature downconversion is sent to the Fourier transform module. The Fourier transform module outputs to the complex multiplication module, where the pulse of the complex multiplier... The compression coefficient is read from the ROM in the dynamic area, and the output of the complex multiplier is input to the inverse Fourier transform module. Finally, the processing result is cached in DDR, waiting for the host computer to retrieve data from DDR and send it to PCIe. For the LFMCW working mode in step 2, the control state machine and data path are as follows: the control data is read from the ADC interface according to the enable signal and sent to the quadrature downconverter module. The quadrature downconverter output is sent to the complex multiplier module, where the window coefficient of the complex multiplier is read from the ROM in the dynamic area. The complex multiplier output is sent to the fast Fourier transform module, and finally, the processing result is cached in DDR, waiting for the host computer to retrieve data from DDR and send it to PCIe.

[0011] In step 5, Vivado is used to synthesize and implement the various static and dynamic modules, specifically as follows: First, create the PCIe, DDR, ADC, and FPGA configuration port interface circuits from step 1. Based on the hardware cores associated with these interfaces, determine their location constraints, perform placement and routing, and observe the resource distribution consumed by these hardware interfaces. Write the common subtask obtained in step 2 as code with AXI Lite configuration ports and AXI Stream input / output interfaces, and constrain it to the designated location. Merge the code and constraints obtained in the first two steps and perform a third synthesis implementation, modifying the location constraints according to Vivado's prompts. Based on the external interfaces obtained in step 3, create the corresponding RTL modules for those interfaces. Open the Device view after Vivado synthesis, manually draw the location of the RTL module (i.e., the dynamic area), and run the design rule check after saving. If a violation is detected, modify accordingly based on the prompts and run DRC again until there are no design rule violations. Under the corresponding interface constraints, write the control state machines, data paths, and dedicated submodules for each mode in step 4. In the static processing module, the data bit width is the maximum value of the data bit width of the corresponding module for each mode. In the dynamic module, the data path module adds a data bit width conversion module as needed to match the static area processing module.

[0012] Specifically, a dedicated address region is allocated in the DDR to store partial bitstreams for each mode. When the FPGA is a ZYNQ series, a portion of the DDR space on the processing system side is used to store the configuration files for each mode in the dynamic area. The host computer informs the PS (Power Supply Unit) via the BAR0 register of the PCIe interface that a new configuration file needs to be loaded. The PS then calls the PCAP (Programmable Array of Applications) function to read and load the configuration file from the corresponding DDR region. When the FPGA does not have an ARM CPU, the onboard DDR space of the FPGA is used to store the configuration files for each mode in the dynamic area. A soft-core CPU is connected to the ICAP interface. When a mode switch is needed, the host computer triggers an interrupt for this CPU via the BAR0 register of the PCIe interface and informs it that a new configuration file needs to be loaded. The CPU then calls the ICAP function to read and load the configuration file from the corresponding DDR region. When the FPGA program needs to be updated remotely from the host computer, the configuration file is pre-stored in the aforementioned DDR space via PCIe before dynamic reconfiguration is performed.

[0013] Beneficial effects 1. This invention improves the flexibility of FPGA development in radar signal processing by leveraging the partial reconfiguration capability of FPGA, reduces FPGA resource consumption, and thus reduces the FPGA capacity required in the complete radar system, thereby reducing costs.

[0014] 2. This invention does not only set the hardware interface as a static area, but also refines the common steps of the algorithm module and sets them as static modules. Therefore, compared with the existing solution, it can reduce the size of the configuration file for partial reloading, thereby reducing the time overhead of partial reconfiguration and improving the real-time performance of partial reconfiguration, making it better suited for application in radar, a highly real-time system.

[0015] 3. In this invention, based on the partial reconfiguration function of Xilinx FPGA, the compatible FPGA models include ZYNQ series FPGAs using the PCAP interface and ordinary FPGAs using the ICAP interface. The hardware interfaces and processing modules are standardized and packaged. Their external interfaces are AXI protocol interfaces that are easy to integrate with other systems, including an AXI Lite interface for parameter configuration, an AXI Stream interface for data stream transmission, and an AXI Full interface for memory access. The processing flow of various modes in some radar systems is decomposed, and common processing flows are extracted. These common processing flows are fixed in the static area, while the control state machines and data paths of each mode, as well as processing flows not in the static area, are implemented in the dynamic area. This achieves finer-grained FPGA dynamic reconfiguration, which is achieved in comparison with existing embodiments that implement all modes in the dynamic area.

[0016] 4. The host computer of this invention remotely updates the partial reconfiguration file to the DDR via PCIe, which can send multiple partial reconfiguration files at once. Then, by defining the signal bit width of the interface module of the static area processing flow as the maximum value of the signal bit width required by various modes, the partial reconfiguration file of the specific mode is loaded. This method can avoid repeatedly starting the PCIe DAM to send configuration bits, and further improve the performance of partial reconfiguration.

[0017] 5. The common processing flow of the radar system in this invention includes orthogonal down-conversion, Fourier transform, inverse Fourier transform, and complex multiplication modules. The signal bit width of the interface module in the static region processing flow is defined as the maximum value of the signal bit width required for various modes to meet the throughput requirements of various modes. Furthermore, to adapt to the fixed bit width processing module, a bit width conversion module is added in the dynamic region.

[0018] 6. This invention caches some reconfiguration files in DDR, which can avoid repeated distribution of configuration files when the multi-mode radar system repeatedly switches modes, thus improving the performance of some reconfiguration. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a commonly used linear frequency modulation signal.

[0020] Figure 2 This is a schematic diagram of a commonly used frequency step signal.

[0021] Figure 3 This is a schematic diagram of the process of the present invention.

[0022] Figure 4 This is a schematic diagram of the static region division in this invention.

[0023] Figure 5 This is a schematic diagram of the three operating modes of the radar system of the present invention.

[0024] Figure 6 This diagram illustrates the orthogonal downconversion, Fourier transform, inverse Fourier transform, and complex multiplication of the present invention. Detailed Implementation

[0025] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] This invention provides a method for partial reconfiguration of FPGA components in a radar system, the process of which is as follows: Figure 3 As shown, it includes the following steps: Step 1: Implement the hardware interfaces required by the radar system, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR), High-Speed ​​Serial Bus (PCIe), Digital-to-Analog Converter (DAC), and Analog-to-Digital Converter (ADC), and standardize their external interfaces, for example, by implementing them as AXI Stream or AXI Memory Map protocols, and allocate them in the static area. Figure 4In this process, the ADCs required by the system are encapsulated as AXI Stream interfaces; the PCIe is encapsulated as AXI Lite interfaces for parameter configuration, AXI Full interfaces for accessing on-chip RAM, and AXI Stream interfaces for streaming data uplink and downlink; and the DDR is encapsulated as bidirectional AXI Stream interfaces. The specific division method is as follows: DDR interface: Use the AXIFull interface form in the Xilinx Memory Interface (MIG) IP core, and then use the Xilinx AXI Datamover IP core to convert the AXI Memory Map interface into two bidirectional data stream AXI Stream interfaces and a control flow AXI Stream interface, reducing the difficulty of use; PCIe interface: Use the Xilinx XDMA IP core and configure it in AXI Stream interface mode, enabling the three base address register spaces (BAR0, BAR1, and BAR2). BAR0 is an AXI Lite interface, used to configure the parameters of each IP in the FPGA or read and write single data through the host. BAR1 is a bidirectional AXI Stream interface, used for uploading and downloading large amounts of data between the FPGA and the host computer. BAR2 is an AXI Full interface, mainly used for the host computer to quickly read and write the RAM inside the FPGA and send some small batches of data; ADC and DAC interfaces: The ADC is encapsulated as an AXI Stream Master interface, and the DAC is encapsulated as an AXI Stream Slave interface.

[0027] Step 2: Based on the functions of the radar system, determine the implementation methods for various operating modes and decompose them into sub-tasks. The radar system has three operating modes, such as... Figure 5 The diagram shows the PD working mode, which requires the raw ADC data to be input and then processed by orthogonal downconversion and time-domain matched filtering; the LFM working mode, which requires the raw ADC data to be input and then processed by orthogonal downconversion and pulse compression, where pulse compression can be further divided into three sub-processes: Fourier transform, complex multiplication, and inverse Fourier transform; and the LFMCW working mode, which requires the raw ADC data to be input and then processed by orthogonal downconversion, windowing, and Fourier transform, where the windowing operation is the same as the complex multiplication operation.

[0028] Step 3: Compare the subtasks of each working mode in Step 2, and implement their common subtasks as dynamically configurable, i.e., through register configuration parameters and standard interfaces, such as implementing them as AXI Stream and AXI Lite processing modules, and placing them in the static area; for example, the common subtasks of the radar system's working modes analyzed in Step 2 include: quadrature downconversion, Fourier transform, inverse Fourier transform, and complex multiplication; implement them as general-purpose modules with AXI Lite configuration ports and AXI Stream input / output interfaces. Quadrature downconversion, Fourier transform, inverse Fourier transform, and complex multiplication are as follows: Figure 6 As shown, their specific implementations are as follows: The quadrature downconverter module (DDC) consists of a frequency-adjustable digital frequency synthesis (DDS) module, a complex multiplication module, and a passband-adjustable low-pass filter (LPF) module cascaded together. The frequency of the DDS and the passband range of the LPF are configured via the AXILite bus, thereby adjusting the function of the DDC. The Fourier transform (FFT) and inverse Fourier transform (IFFT) modules are instantiated using the Xilinx FFT IP core. The number of FFT points is set according to the maximum number of points required in the entire radar system. The runtime configurable options in the IP core are selected, and its configuration interface is encapsulated from the AXI Stream interface into an AXI Lite interface. Through this AXI Lite interface, the FFT IP core can be configured for a Fourier transform or inverse Fourier transform with the corresponding number of points. The complex multiplication module is configured by calling the Xilinx... The floating-point operation IP core is encapsulated as a floating-point complex multiplication module according to the complex multiplication operation rules (a+bi)×(c+di)=(ac-bd)+(ad+bc)i. The external interface is the AXIStream interface. This module does not require the AXI Lite configuration interface.

[0029] Step 4: Based on various working modes and the static processing modules implemented in Step 3, write the processing state machine and data path for each module. Implement subtasks that cannot be processed in the static module separately and allocate them to the dynamic area. Use the control state machine and data path in the dynamic area to connect the various hardware interface modules and processing modules in the static area, and implement processing modules not in the static area in the dynamic area. For the PD working mode in Step 2, the control state machine and data path are as follows: Data is read from the ADC interface according to the enable signal and sent to the quadrature downconversion module. The data output from the quadrature downconversion is then input to the time-domain matched filter module in the dynamic area, and finally, the processing result is cached in DDR, waiting for the host computer to retrieve data from DDR and send it to PCIe. For the LFM working mode in Step 2, the control state machine and data path are as follows: Data is read from the ADC interface according to the enable signal and sent to the quadrature downconversion module. The data output from the quadrature downconversion is sent to the Fourier transform module, and the Fourier transform module output is sent to the complex multiplication module. The pulse voltage of the complex multiplier... The window coefficients are read from the ROM in the dynamic area, and the output of the complex multiplier is input to the inverse Fourier transform module. Finally, the processing result is cached in DDR, waiting for the host computer to retrieve data from DDR and send it to PCIe. For the LFMCW working mode in step 2, the control state machine and data path are as follows: the control data is read from the ADC interface according to the enable signal and sent to the quadrature downconverter module. The quadrature downconverter output is sent to the complex multiplier module, where the window coefficients of the complex multiplier are read from the ROM in the dynamic area. The complex multiplier output is sent to the fast Fourier transform module, and the processing result is cached in DDR, waiting for the host computer to retrieve data from DDR and send it to PCIe.

[0030] Step 5: Use Vivado synthesis to implement the various static and dynamic modules. Specifically, first create the interface circuits such as PCIe, DDR, ADC, and FPGA configuration ports from Step 1. Based on the hardware cores associated with these interfaces, determine their positional constraints, perform placement and routing, and observe the resource distribution consumed by these hardware interfaces. Then, write the common subtask obtained in Step 2 as having an AXI Lite configuration port and AXI... Create the code for the Stream input / output interface and constrain it to the appropriate location; merge the code and constraints obtained in the first two steps and perform a third synthesis, modifying the position constraints according to Vivado's prompts; create the corresponding RTL module (which can be empty) based on the external interface obtained in step 3; open the Device view after Vivado synthesis, manually draw the location of the RTL module, i.e., the dynamic area, and run the Design Rule Check (DRC) after saving. If a violation is prompted, make the corresponding modifications according to the prompts and run DRC again until there are no design rule violations; under the corresponding interface constraints, write the control state machine, data path, and dedicated sub-modules for each mode in step 4; in particular, in order to make the data bit widths match between modules, the data bit width in the static processing module is the maximum value of the data bit width of the corresponding module in each mode. Therefore, the data path module in the dynamic module needs to add a data bit width conversion module as needed to match the static area processing module.

[0031] Step 6: During operation, the dynamic zone function is configured according to the working mode through the FPGA configuration interface (Internal Configuration Interface (ICAP) and Processor Configuration Interface (PCAP)), and the parameters of the corresponding static zone processing module are issued to realize the dynamic switching of radar functions. To speed up the configuration, a dedicated address area is allocated in DDR to store part of the bit stream for each mode. Specifically: when the FPGA is a ZYNQ series (with an ARM CPU), part of the DDR space on the processing system (PS) side is used to store the configuration files for each dynamic zone mode. The host computer informs the PS that a new configuration file needs to be loaded through the BAR0 register of PCIe. The PS reads and loads the configuration file from the corresponding DDR area by calling the PCAP through the driver function. When the FPGA does not have an ARM CPU, the onboard DDR space of the FPGA is used to store the configuration files for each dynamic zone mode. A soft-core CPU can be connected to the ICAP interface. When a mode switch is required, the host computer triggers an interrupt for this CPU through the BAR0 register of PCIe and informs it that a new configuration file needs to be loaded. The CPU reads and loads the configuration file from the corresponding DDR area by calling the ICAP through the driver function. When it is necessary to remotely update the FPGA program from the host computer, the configuration file can be pre-stored in the above-mentioned DDR space via PCIe, and then dynamic reconfiguration can be performed.

[0032] In summary, the above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dynamic reconfiguration method for FPGAs in radar systems, characterized in that, Includes the following steps: Step 1: Implement the hardware interfaces required by the radar system, standardize its external interfaces, and allocate them to the static area; Step 2: Based on the functions of the radar system, determine the implementation methods for various working modes and decompose them into sub-tasks. The sub-tasks include: In the PD mode of the radar system, the raw ADC data is input and then subjected to orthogonal down-conversion and time-domain matched filtering; in the LFM mode, the raw ADC data is input and then subjected to orthogonal down-conversion and pulse compression, where pulse compression is divided into three sub-processes: Fourier transform, complex multiplication, and inverse Fourier transform; in the LFMCW mode, the raw ADC data is input and then subjected to orthogonal down-conversion, windowing, and Fourier transform, where the windowing operation is the same as the complex multiplication operation. Step 3: Compare the subtasks of each working mode in Step 2, and implement their common subtasks as dynamically configurable. Step 4: Based on various working modes and the static processing modules implemented in Step 3, write the processing state machine and data path for each module, and implement the subtasks that cannot be processed in the static module separately and divide them into the dynamic area; through the control state machine of the dynamic area, the data path connects the various hardware interface modules and processing modules in the static area, and implements the processing modules that are not in the static area in the dynamic area. Step 5: During operation, the dynamic zone function is configured according to the working mode through the FPGA configuration interface and the processor configuration interface, and the parameters of the corresponding static zone processing module are sent out to realize the dynamic switching of radar functions.

2. The method as described in claim 1, characterized in that, In step 1, the specific division method is as follows: DDR interface: It uses the AXI Full interface form in the Xilinx memory interface IP core, and then uses the Xilinx AXIDatamover IP core to convert the AXI Memory Map interface into two bidirectional data stream AXI Stream interface and control flow AXI Stream interface. PCIe interface: Uses Xilinx XDMA IP core and configures it in AXI Stream interface mode, enabling the three base address register spaces BAR0, BAR1 and BAR2. BAR0 is an AXI Lite interface, used to configure the parameters of each IP in the FPGA or read and write single data through the host. BAR1 is a bidirectional AXI Stream interface, used for uploading and downloading large amounts of data between the FPGA and the host computer. BAR2 is an AXI Full interface, used for the host computer to quickly read and write the RAM inside the FPGA and send batch data. ADC and DAC interfaces: The ADC is encapsulated as an AXI Stream Master interface, and the DAC is encapsulated as an AXI Stream Slave interface.

3. The method as described in claim 1, characterized in that, In step 3, parameters are configured through registers and standardized interfaces are used.

4. The method as described in claim 3, characterized in that, In step 3, their common subtasks include: orthogonal downconversion, Fourier transform, inverse Fourier transform, and complex multiplication; they are implemented as general-purpose modules with AXI Lite configuration ports and AXI Stream input / output interfaces. The quadrature downconverter module consists of a cascaded digital frequency synthesis module with adjustable frequency, a complex multiplication module, and a low-pass filter module with adjustable passband. The frequency of the DDS and the passband range of the LPF are configured through the AXI Lite bus, thereby adjusting the function of the DDC. The Fourier transform and inverse Fourier transform modules are implemented by instantiating the Xilinx FFT IP core. The number of FFT points is set according to the maximum number of points required in the entire radar system. The runtime configurable options in the IP core are selected, and finally, its configuration interface is encapsulated from the AXI Stream interface into the AXI Lite interface. Through the AXI Lite interface, the FFT IP core can be configured to perform Fourier transform or inverse Fourier transform with the corresponding number of points. The complex multiplication module calls the Xilinx floating-point operation IP core and encapsulates it into a floating-point complex multiplication module according to the complex multiplication operation rules (a+bi)×(c+di)=(ac-bd)+(ad+bc)i. The external interface is the AXI Stream interface.

5. The method as described in claim 1, characterized in that, For the PD operating mode in step 2, the control state machine and data path are as follows: Data is read from the ADC interface according to the enable signal and sent to the quadrature downconversion module. The data output from the quadrature downconversion is then input to the time-domain matched filter module in the dynamic zone. Finally, the processing result is cached in DDR, waiting for the host computer to retrieve data from DDR and send it to PCIe. For the LFM operating mode in step 2, the control state machine and data path are as follows: Data is read from the ADC interface according to the enable signal and sent to the quadrature downconversion module. The data output from the quadrature downconversion is sent to the Fourier transform module. The Fourier transform module outputs to the complex multiplication module, where the pulse voltage of the complex multiplier... The window coefficients are read from the ROM in the dynamic area, and the output of the complex multiplier is input to the inverse Fourier transform module. Finally, the processing result is cached in DDR, waiting for the host computer to retrieve data from DDR and send it to PCIe. For the LFMCW working mode in step 2, the control state machine and data path are as follows: the control data is read from the ADC interface according to the enable signal and sent to the quadrature downconverter module. The quadrature downconverter output is sent to the complex multiplier module, where the window coefficients of the complex multiplier are read from the ROM in the dynamic area. The complex multiplier output is sent to the fast Fourier transform module, and the processing result is cached in DDR, waiting for the host computer to retrieve data from DDR and send it to PCIe.

6. The method as described in claim 5, characterized in that, In step 5, Vivado is used to synthesize and implement the various static and dynamic modules, specifically as follows: First, create the PCIe, DDR, ADC, and FPGA configuration port interface circuits from step 1. Based on the hardware cores associated with these interfaces, determine their location constraints, perform placement and routing, and observe the resource distribution consumed by these hardware interfaces. Write the common subtask obtained in step 2 as code with AXI Lite configuration ports and AXI Stream input / output interfaces, and constrain it to the designated location. Merge the code and constraints obtained in the first two steps and perform a third synthesis implementation, modifying the location constraints according to Vivado's prompts. Based on the external interfaces obtained in step 3, create the corresponding RTL modules for those interfaces. Open the Device view after Vivado synthesis, manually draw the location of the RTL module (i.e., the dynamic area), and run the design rule check after saving. If a violation is detected, modify accordingly based on the prompts, and run DRC again until there are no design rule violations. Under the corresponding interface constraints, write the control state machines, data paths, and dedicated submodules for each mode in step 4.

7. The method as described in claim 6, characterized in that, The data bit width in the static processing module is the maximum value of the data bit width of the corresponding module for each mode. In the dynamic module, a data bit width conversion module is added to the data path module as needed to match the static area processing module.

8. The method as described in claim 5, 6, or 7, characterized in that, Dedicated address regions are allocated in the DDR to store partial bitstreams for each mode. Specifically: When the FPGA is a ZYNQ series, a portion of the DDR space on the processing system side is used to store the configuration files for each mode in the dynamic area. The host computer informs the PS (Power Supply Unit) via the BAR0 register of PCIe that a new configuration file needs to be loaded. The PS then calls the PCAP (Programmable Array Components) function to read and load the configuration file from the corresponding DDR region. When the FPGA does not have an ARM CPU, the onboard DDR space of the FPGA is used to store the configuration files for each mode in the dynamic area. A soft-core CPU is connected to the ICAP interface. When a mode switch is required, the host computer triggers an interrupt for this CPU via the BAR0 register of PCIe and informs it that a new configuration file needs to be loaded. The CPU then calls the ICAP function to read and load the configuration file from the corresponding DDR region. When the FPGA program needs to be updated remotely from the host computer, the configuration file is pre-stored in the aforementioned DDR space via PCIe before dynamic reconfiguration is performed.

Images