OPI PSRAM Control System and Method Based on AXI Bus

Abstract

The application relates to an OPI PSRAM control system and method based on an AXI bus in the technical field of integrated circuits, which comprises an XPI unit, a cache unit, a protocol conversion control unit, a protocol conversion unit and an IO unit; the XPI unit is used for splitting or combining processing of commands and data in an AXI clock domain, and controls writing of the commands and data in the AXI clock domain into a cache module, or reading of data from the cache module, and splitting and combining of the read data according to the requirement of a read command, and transmission of the read data to a bus interface in the AXI clock domain; the cache unit is used for conversion between asynchronous clock domains; the protocol conversion control unit is used for reading data and commands from the cache module according to state jumping of a state machine, and converting the data and commands into timing commands satisfying an OPI protocol; and the protocol conversion unit is used for converting timing of a single edge under one frequency into timing under double edges of one frequency of an OPI interface through a two-frequency clock, so that the problems of low conversion efficiency and strict clock requirement of a conventional controller are solved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to an OPI PSRAM control system and method based on the AXI bus. Background Technology

[0002] With the rapid development of internet and mobile communication technologies, the Internet of Things (IoT) has become a reality. As the IoT becomes increasingly prevalent, the demands on power consumption for memory chip packaging technology are rising. There is a strong desire for low-power, miniaturized products. To meet this demand, memory manufacturers have launched various products, among which OPPI PSRAM holds a significant advantage in low power consumption and small packaging. In terms of packaging, conventional DDR SDRAM includes clock pins, command pins, address pins, and data pins; while OPI PSRAM shares command, address, and data pins, greatly saving packaging pins and enabling miniaturization. Furthermore, due to the structural differences between PSRAM and SDRAM, PSRAM has lower power consumption than DRAM.

[0003] To facilitate access to OPI PSRAM devices, the controller serves as a bridge for communication between the user and the OPI PSRAM. However, existing conventional controllers suffer from low conversion efficiency and stringent clock requirements. Summary of the Invention

[0004] This invention addresses the shortcomings of existing technologies by providing an OPI PSRAM control system and method based on the AXI bus, which solves the problems of low conversion efficiency and strict clock requirements of conventional controllers.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] An OPI PSRAM control system based on the AXI bus includes an XPI unit, a cache unit, a protocol conversion control unit, a protocol conversion unit, and an I / O unit.

[0007] The XPI unit is used to split or combine commands and data from the AXI clock domain, and control the commands and data from the AXI clock domain to be written to the cache module or read from the cache module. According to the requirements of the read command, the read data is split and combined and transmitted to the bus interface of the AXI clock domain.

[0008] The cache unit is used for conversion between asynchronous clock domains;

[0009] The protocol conversion control unit is used to read data and commands from the cache module according to the state transition of the state machine, and convert them into timing commands that meet the OPI protocol.

[0010] The protocol conversion unit is used to convert the timing of a single edge under a first-fold frequency multiplier into the timing of a double-fold frequency multiplier dual edge multiplier for the OPI interface through a second-fold frequency multiplier clock.

[0011] The I / O unit is used to provide signal input and output ports.

[0012] Optionally, the XPI unit includes a write address channel unit, which is used to perform the following steps:

[0013] When both the write address channel valid signal and the write address channel ready signal are valid, the write address channel signal data is collected.

[0014] Based on the write address channel signal data and the boundary constraints of OPI, the starting address of OPI access and the amount of data accessed each time are obtained;

[0015] The starting address of the OPI access, the amount of data accessed each time, and the write address channel signal data are stored in the buffer unit.

[0016] Optionally, the XPI unit includes a write data channel unit, which is used to perform the following steps:

[0017] When both the write data channel valid signal and the write data channel ready signal are valid, the write data channel signal data is collected.

[0018] Based on the matching of the identifier signal of the write address channel signal data with the identifier signal of the write data channel signal data, as well as the access requirements of the write data channel signal data and OPI, the write channel data and write channel data mask of the bus are recombined to form new OPI interface data and mask signals, and then stored in the buffer unit.

[0019] Optionally, the XPI unit includes a write response channel unit, which is used to respond to write-back data.

[0020] Optionally, the XPI unit includes a read address channel unit, the control of which is the same as that of the write address channel.

[0021] Optionally, the XPI unit includes the read data channel unit performing the reverse process steps of the write data channel unit.

[0022] Optionally, the protocol conversion control unit is used to control the state jump between the system master control state machine, the configuration mode state machine, and the normal mode state machine.

[0023] Optionally, the protocol conversion unit includes a clock generation unit, an interface conversion control unit, and a phase delay control unit;

[0024] The clock generation unit is used to generate a first-frequency clock and an OPI interface gate enable clock.

[0025] The interface conversion control unit is used to convert double-edge single-bit-width data into single-edge double-bit-width data.

[0026] The phase delay control unit is used to perform timing phase delay of the input and output ports.

[0027] An OPI PSRAM control method based on an AXI bus, wherein the control method is applied to an OPI PSRAM control system of an AXI bus as described in any of the preceding claims.

[0028] A computer-readable storage medium storing a computer program, which, when executed by a processor, implements the OPI PSRAM control method based on the AXI bus as described above.

[0029] Compared with the prior art, the technical solution provided by this invention has the following advantages:

[0030] By using asynchronous sampling cache control technology in conjunction with bus burst access, the arbitrary relationship between clock frequencies between the application interface and the OPI interface is controlled. At the same time, access efficiency is improved by controlling the cache depth, and port timing stability is achieved by converting from double rate to single rate, reducing the generation of glitches. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a structural diagram of an OPI PSRAM control system based on the AXI bus proposed in Embodiment 1.

[0033] Figure 2 This is a diagram of the cache unit structure proposed in Embodiment 1;

[0034] Figure 3 This is the clock generation and output control diagram for the first-order frequency multiplier proposed in this embodiment;

[0035] Figure 4 Write a timing diagram for the protocol conversion proposed in Embodiment 1;

[0036] Figure 5 This is a sampling diagram of the interface read timing proposed in Embodiment 1;

[0037] Figure 6 This is the phase delay control diagram proposed in Embodiment 1. Detailed Implementation

[0038] The present invention will be further described in detail below with reference to the embodiments. The following embodiments are explanations of the present invention, but the present invention is not limited to the following embodiments.

[0039] Example 1

[0040] like Figure 1 As shown, an OPI PSRAM control system based on the AXI bus includes an XPI unit, a cache unit, a protocol conversion control unit, a protocol conversion unit, and an I / O unit. The XPI unit is used to split or combine commands and data from the AXI clock domain, and control the writing of commands and data from the AXI clock domain to the cache module, or to read data from the cache module. Based on the read command requirements, the XPI unit splits and combines the read data and transmits it to the bus interface of the AXI clock domain. The cache unit is used for conversion between asynchronous clock domains. The protocol conversion control unit is used to read data and commands from the cache module based on the state transitions of the state machine, and convert them into timing commands that meet the OPI protocol. The protocol conversion unit is used to convert the single-edge timing at first-multiplied frequency into the timing at first-multiplied frequency dual-edge timing of the OPI interface through a double-multiplied clock. The I / O unit provides signal input and output ports.

[0041] Specifically, the XPI unit splits and combines commands and data from the AXI clock domain to meet OPI transmission requirements. It also controls the writing of corresponding commands and data to the buffer space or the reading of data from the buffer space. Based on the read command requirements, it splits and combines the data before transmitting it to the AXI clock domain bus interface. The buffer unit is used for conversion between asynchronous clock domains and includes four buffer units: write command buffer, write data buffer, read command buffer, and read data buffer. The command buffer depth and data buffer depth can be configured according to parameters. The protocol conversion control unit mainly consists of different state machines. Based on the protocol requirements of the OPI PSRAM, it converts AXI protocol commands to OPI... The PSRAM requires control over the conversion of protocol commands; the protocol conversion unit mainly converts the timing of a single edge under a double-frequency clock to the timing of a double-frequency OPI interface under a double-frequency clock, solving problems such as the combinational logic of the port's double-edge transmission, ensuring that the timing meets the transmission requirements; and performs functions such as port delay control; the IO unit mainly includes signal ports such as CLK / CLKN, CE_N, DQS, DM, RESET, DQ0~7, and also includes IO power ground, digital power ground, reference voltage, ZQ adjustment and other units.

[0042] According to the requirements of the AXI protocol, the XPI unit is divided into a write address channel unit, a write data channel unit, a write response channel unit, a read address channel unit, and a read data channel unit. Each channel has its own handshake signal, namely a valid signal and a ready signal. In this embodiment, the control is based on the requirements of the AXI bus and will not be described in detail.

[0043] Furthermore, the XPI unit includes a write address channel unit, which performs the following steps: when the write address channel valid signal and the write address channel ready signal are both valid, the write address channel signal data is acquired; based on the write address channel signal data and the boundary constraints of OPI, the starting address of OPI access and the amount of data accessed each time are obtained; the starting address of OPI access, the amount of data accessed each time, and the write address channel signal data are stored in the buffer unit.

[0044] For the write address channel, when both the write address channel valid signal and the write address channel ready signal are valid, the write address channel signal data, including the write address channel identifier signal, write address channel address signal, write address channel size signal, write address channel burst signal, and write address channel length signal, is sampled. The write address channel identifier signal is used for matching with the write data channel identifier signal during data writing. Based on the write address channel address signal, write address channel size signal, write address channel burst signal, write address channel length signal, and the 1K boundary limit of OPI, the write address needs to start from an even-numbered address to obtain the starting address of the OPI access and the amount of data accessed each time. Then, the starting address of the OPI access, the amount of data accessed each time, and the write address channel size signal are stored in the buffer according to buffer control.

[0045] Optionally, the XPI unit includes a write data channel unit, which performs the following steps: when the write data channel valid signal and the write data channel ready signal are both valid, the write data channel signal data is acquired; based on the matching of the identifier signal of the write address channel signal data and the identifier signal of the write data channel signal data, as well as the access requirements of the write data channel signal data and OPI, the write channel data and write channel data mask of the bus are recombined to form new OPI interface data and mask signal, and then stored in the buffer unit.

[0046] For the write data channel, when the write channel valid signal and the write channel ready signal are both valid, the write channel identifier signal and the write data channel identifier signal are matched according to the write address channel identifier signal and the write address channel identifier signal, the write address channel address signal, the write address channel size signal, the write address channel burst signal and the access requirements of OPI. The write channel data and write channel data mask of the bus are then recombined into new data and mask signals that satisfy the OPI interface, and then stored in the buffer according to the buffer control.

[0047] The XPI unit includes a write response channel unit, which is used to respond to data write-back. After each burst access data is completely written to the buffer, a response signal is sent back to the master, indicating two states: normal (OK) and slave error (SLVERR). A slave error occurs when the write address channel identifier signal and the write data channel identifier signal do not match, indicating an error. Otherwise, it indicates a normal response.

[0048] The XPI unit includes a read address channel unit, whose control is the same as that of the write address channel. The XPI unit also includes a read data channel unit that executes the reverse process of the write data channel unit. That is, the read data channel control is the reverse process of the write data channel. Based on the commands and address control of the read address channel, it reads the data from the buffer and splits it to send it to the bus.

[0049] like Figure 2 As shown, the cache controller mainly implements data conversion between two clock domains, corresponding to the write clock and read clock domains. The write clock domain related signals include write reset, write enable, write data, a flag indicating how much data remains in the cache, and a write-full flag. The read clock domain related signals include read reset, read enable, read data, a flag indicating how much space remains in the cache, and a read-empty flag. When write enable is high and the write-full flag is low, write data is written into the cache. When read enable is high and the read-empty flag is low, data is read from the cache and onto the read data field. In this embodiment, "high" and "low" refer to high-level or low-level signals.

[0050] The protocol conversion control unit is used to control the state transitions between the system's main control state machine, configuration mode state machine, and normal mode state machine. The control unit mainly consists of the system's main control state machine, configuration mode state machine, and normal mode state machine. Based on the state transitions, it reads data and commands from the buffer and converts them into timing commands that conform to the OPI protocol. The three state machines are described below:

[0051] In the system's main control state, there are four phases: initial state, initialization phase 1 state, control configuration state, and normal access mode state. Upon system reset, the system is in the initial state, releasing the reset and configuring relevant registers. The system then jumps to the initialization phase 1 state via `ctrl_start`. After the timeout period for TPU initialization in the initialization phase 1 state, `ctrl_start` is used to jump back to the control configuration state. In the control configuration state, operations such as hardware reset, global reset, data read / write, mode register read, and mode register write can be performed via commands through the APB. After completing the control configuration state, the system enters the normal access mode state via `ctrl_start`. In normal access mode, data read / write access from the AXI bus is performed. When the bus idle timeout occurs, the system can choose to enter powerdown mode based on the timeout setting and enable configuration.

[0052] During configuration mode, the configuration mode state machine is divided into several states: Idle; Reset (allowing hardware reset and global reset operations); Mode Register Write (allowing mode register write operations); Mode Register Read (allowing mode register read operations); Data Write (fixedly writing 4 bytes of data); Data Read (fixedly reading 4 bytes of data). In Idle mode, if there is a write request to the mode status register, the machine enters the mode register write state and exits back to Idle mode upon completion. Similarly, in Idle mode, if there is a read request to the mode status register, the machine enters the mode register read state and exits back to Idle mode upon completion. In Idle mode, if there is a reset request to the status register, the machine enters the reset state and exits back to Idle mode upon completion. In Idle mode, if there is a data write request to the status register, the machine enters the data write state and exits back to Idle mode upon completion. Finally, in Idle mode, if there is a data read request to the status register, the machine enters the data read state and exits back to Idle mode upon completion.

[0053] The protocol conversion unit includes a clock generation unit, an interface conversion control unit, and a phase delay control unit. The clock generation unit is used to generate a double-frequency clock and an OPI interface gate enable clock. The interface conversion control unit is used to convert dual-edge single-width data into single-edge double-width data. The phase delay control unit is used to perform timing phase delay for the input and output ports.

[0054] The protocol conversion unit receives a double-frequency clock and generates a single-frequency clock. Simultaneously, it converts the timing of the single-edge clock at double frequency, which meets the OPI protocol, into the timing of the double-edge clock at double frequency for the OPI interface. This solves problems such as the combinational logic of the port's double-edge transmission, ensuring that the timing meets the transmission requirements. It also performs functions such as port delay control.

[0055] like Figure 3The diagram shows the generation and output clock control of a double-frequency clock. A double-frequency clock `ddr_clk` is used to generate a double-frequency clock `phy_clk`, and the OPI interface gating enable clock is generated using the enable control signal `dfi_clk_disable` for low-power control. `dfi_clk_disable` is the clock invalidation signal in the double-frequency domain; a high value indicates an invalid clock. `dfi_clk_disable_d1` is a one-beat delay of `dfi_clk_disable` in the double-frequency domain. `dfi_clk_disable_gated` is a one-beat delay of `dfi_clk_disable_d1` in the double-frequency domain. Based on `dfi_clk_disable_gated`, a double-gated clock `opi_clk_out` is generated in the double-frequency domain. This method ensures both output clock gating control and that the clock is output from the timing logic register, reducing glitches.

[0056] like Figure 4 The diagram shows the timing diagram for protocol conversion write. A signal with a single edge and double bit width under a clock cycle of i_phy_clk is converted to a signal with a single edge and single bit width under a clock cycle of i_ddr_clk. Here, i_ofi_ce_n represents the OPI port selection enable signal, active low, a single-bit signal; i_cmd_en represents the command valid enable; i_wrdata_en represents the write data valid signal, active high, both single-bit signals; i_cmd_data is the command or data transmission signal, with a bit width twice that of the OPI interface's data output signal o_dq; i_data_dm is the data mask signal, high indicating masking, with a bit width twice that of the OPI interface's o_dm_dqs; all the signals i_input above represent input signals, operating in the single-rate i_phy_clk clock domain.

[0057] o_dq is the data output signal transmitted to the OPI interface, typically with a bit width of 8 bits; o_dm_dqs is the mask enable signal transmitted to the OPI interface, typically with a bit width of 1 bit; o_opi_ce_n is the interface selection signal transmitted to the OPI, active low; o_clk_out is the clock output signal obtained based on i_ddr_clk. All the above o_ signals represent output signals and operate in the double-rate i_ddr_clk clock domain.

[0058] The main function of this unit is to split the double-width i_cmd_data into a single-width o_dq signal based on i_cmd_en and i_wrdata_en; to split the double-width i_data_dm signal into a single-width o_dm_dqs signal; and to obtain the o_opi_ce_n signal and the clock output signal o_clk_out from the i_ofi_ce_n signal according to the OPI interface protocol.

[0059] It is worth mentioning that since all output signals are output from the timing logic registers in the i_ddr_clk clock domain, glitches caused by combinational logic outputs are avoided, making the port timing more stable and controllable.

[0060] like Figure 5 As shown, the interface read timing sampling diagram is used as an example of 4-byte transmission. It completes the conversion of double-edge single-bit-width data into single-edge double-bit-width data. First, the OPI interface sends the io_opi_dm_dqs signal and the io_opi_dq signal. The two signals are edge-aligned. Here, io_opi_dm_dqs needs to be used as a clock to sample the io_opi_dq signal. First, the io_opi_dm_dqs signal needs to be delayed by 90 degrees using a delay control unit to obtain the dqs_90 clock signal. This aligns the dqs_90 and io_opi_dq signals. The io_opi_dq signal is sampled using the rising and falling edges of the dqs_90 signal, respectively. Then, the data sampled on the rising and falling edges is sampled again using the rising edge of the dqs_90 signal, thus combining them into the comb_dq signal. The corresponding valid signal is comb_dq_valid. When the last two bytes of data are transmitted, read_done is 1 to indicate that the transmission is complete. In the diagram, D0, D1, D2, and D3 represent the first to fourth bytes of data, respectively, and xx indicates that it is not relevant.

[0061] It is worth mentioning that the protocol conversion unit requires a port delay control unit to perform input and output port timing phase delays, including output clock delay, output chip select delay, and input sampling clock delay.

[0062] like Figure 6The diagram shows the phase delay control. This unit is used to adjust the phase relationship between the clock and data, including write timing clock delay adjustment and read timing dqs sampling clock delay adjustment. This unit determines the number of standard units of delay between dly_out and dly_in based on the dly_sel[7:0] signal. When dly_sel[7:0] is 0, it represents 0 delay units; when dly_sel[7:0] is 1, it represents 1 delay unit; when dly_sel[7:0] is 2, it represents 2 delay units, and so on. When dly_sel[7:0] is 255, it represents 255 delay units. The delay value of the standard delay unit is determined by selecting the device from the process library.

[0063] Example 2

[0064] An OPI PSRAM control method based on the AXI bus is provided. The control method is applied to the OPI PSRAM control system of the AXI bus as described in Embodiment 1, and will not be described in detail in this embodiment.

[0065] A computer-readable storage medium storing a computer program, which, when executed by a processor, implements the aforementioned OPI PSRAM control method based on the AXI bus.

[0066] More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wire segments, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0067] In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless segments, wire segments, optical cables, RF, etc., or any suitable combination thereof.

[0068] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules, units, or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units, modules, or components may be combined or integrated into another device, or some features may be ignored or not executed.

[0069] The units may or may not be physically separate. The components shown as units can be one or more physical units, meaning they can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0070] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0071] In particular, according to embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), it performs the functions defined in the methods of this application. It should be noted that the computer-readable medium described above in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof.

[0072] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0073] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions within the technical scope disclosed in the present invention should be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An OPI PSRAM control system based on the AXI bus, characterized in that, It includes an XPI unit, a buffer unit, a protocol conversion control unit, a protocol conversion unit, and an I / O unit; The XPI unit is used to split or combine commands and data from the AXI clock domain, and control the writing of commands and data from the AXI clock domain to a cache module, or to read data from the cache module. Based on the read command requirements, the read data is split and combined, and then transmitted to the bus interface of the AXI clock domain. The XPI unit includes a write address channel unit, which performs the following steps: when both the write address channel valid signal and the write address channel ready signal are valid, write address channel signal data is acquired; based on the write address channel signal data and the OPI boundary constraints, the starting address of the OPI access and the amount of data accessed each time are obtained; the starting address of the OPI access, the amount of data accessed each time, and the write address channel signal data are stored in a buffer unit. The XPI unit also includes a write data channel unit, which performs the following steps: when the write data channel valid signal and the write data channel ready signal are both valid, the write data channel signal data is collected; based on the matching of the identifier signal of the write address channel signal data and the identifier signal of the write data channel signal data, as well as the access requirements of the write data channel signal data and OPI, the write channel data and write channel data mask of the bus are recombined to form new OPI interface data and mask signal, and then stored in the buffer unit; The cache unit is used for conversion between asynchronous clock domains; The protocol conversion control unit is used to read data and commands from the cache module according to the state transition of the state machine, and convert them into timing commands that meet the OPI protocol. The protocol conversion unit is used to convert the timing of a single edge under a first-fold frequency multiplier into the timing of a double-fold frequency multiplier dual edge multiplier for the OPI interface through a second-fold frequency multiplier clock. The I / O unit is used to provide signal input and output ports.

2. The OPI PSRAM control system based on the AXI bus according to claim 1, characterized in that, The XPI unit includes a write response channel unit, which is used to respond to write-back data.

3. The OPI PSRAM control system based on the AXI bus according to claim 1, characterized in that, The XPI unit includes a read address channel unit, and the control of the read address channel unit is the same as that of the write address channel.

4. The OPI PSRAM control system based on the AXI bus according to claim 1, characterized in that, The XPI unit includes the reverse process steps of the read data channel unit performing the write data channel unit.

5. The OPI PSRAM control system based on the AXI bus according to claim 1, characterized in that, The protocol conversion control unit is used to control the state jumps between the system master control state machine, the configuration mode state machine, and the normal mode state machine.

6. The OPI PSRAM control system based on the AXI bus according to claim 1, characterized in that, The protocol conversion unit includes a clock generation unit, an interface conversion control unit, and a phase delay control unit; The clock generation unit is used to generate a frequency-doubled clock and an OPI interface gating enable clock. The interface conversion control unit is used to convert double-edge single-bit-width data into single-edge double-bit-width data. The phase delay control unit is used to perform timing phase delay of the input and output ports.

7. An OPI PSRAM control method based on the AXI bus, characterized in that, The control method is applied to the OPI PSRAM control system of the AXI bus as described in any one of claims 1-6.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the OPI PSRAM control method based on the AXI bus as described in claim 7.

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