Method for locating hardware trojan in machine learning based gate level netlist
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2023-04-13
- Publication Date
- 2026-05-29
AI Technical Summary
Existing methods for detecting and locating hardware Trojans suffer from low accuracy and efficiency, and require an ideal model as a reference.
The integrated circuit is divided into multiple maximally single-output sub-modules. A dataset is constructed and a machine learning model is used to detect and locate hardware Trojans. A classifier is trained through cross-validation and combined with layer-by-layer difference analysis for precise location.
It improves the accuracy and efficiency of hardware Trojan detection, simplifies the operation process, shortens the detection time, and improves the accuracy of location.
Smart Images
Figure CN116401719B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a method for detecting and locating hardware Trojans in a gate-level netlist, which can be used for hardware Trojan protection during the design phase of integrated circuit gate-level netlists. Background Technology
[0002] Hardware Trojans are malicious circuits that can be implanted at any stage of the integrated circuit design and manufacturing process. Their practical applications have already impacted some critical fields, such as mobile communications, healthcare, aerospace, public infrastructure, and even national security. Currently, protective measures against hardware Trojans mainly focus on non-destructive detection. The core idea is to use changes in certain characteristics after a hardware Trojan is implanted to determine whether an integrated circuit has been infected with a hardware Trojan. Non-destructive hardware Trojan detection can be divided into dynamic detection and static detection, depending on the stage at which the selected integrated circuit characteristics are located.
[0003] Dynamic detection determines the presence of hardware malware by observing characteristics during the integrated circuit's operational phase, such as bypass parameters like power consumption and path delay. Under the influence of hardware malware, certain characteristics of the integrated circuit's operational phase change significantly and are easily observed, thus dynamic detection typically achieves high accuracy. However, dynamic detection methods usually require careful selection of the test vector value set, which is difficult and time-consuming when the integrated circuit has many input pins.
[0004] Static detection determines the presence of hardware malware by extracting features from the integrated circuit design phase, such as fan-in and the number of ring structures. Static detection does not require a fully designed integrated circuit, facilitating phased and modular detection of hardware malware. Furthermore, static detection does not require actual operation of the integrated circuit, thus eliminating the need for test vectors. However, most features from the integrated circuit design phase typically require extraction time proportional to the circuit size, and the correlation between these features and hardware malware is difficult to guarantee, resulting in low detection accuracy.
[0005] Patent document CN 110287735A discloses a "Trojan Infection Circuit Identification Method Based on Chip Netlist Features," which includes extracting node SCOAP metrics, detecting suspicious node sets using k-means++ clustering networks, correcting the suspicious node sets by combining the topology of the chip netlist, and reconstructing the Trojan trigger node through node reachability analysis. This method lacks consideration for the mixing of rare and common nodes as Trojan trigger nodes, making it prone to missing Trojans that have accessed a large number of common nodes. Furthermore, this method is time-consuming and has low accuracy.
[0006] Patent document CN 114065308A discloses "A gate-level hardware Trojan location method and system based on deep learning," which includes extracting gate-level netlist information, constructing a feature path set, and using TextCNN for detection and location. This method suffers from low Trojan detection accuracy due to the long construction time for path features and the indistinguishability between these features and ordinary path features.
[0007] Patent document CN 109740348A discloses "A Hardware Trojan Location Method Based on Machine Learning," which includes gate-level netlist feature extraction, hardware Trojan type classification, and detection and location using Ove-class SVM and BPNN respectively. This method faces difficulties in classifying hardware Trojan types during the preprocessing stage and is prone to mis-locating Trojan networks.
[0008] In summary, existing methods for detecting and locating hardware Trojans still suffer from low accuracy and efficiency in locating hardware Trojans, and require an ideal model as a reference. Summary of the Invention
[0009] The purpose of this invention is to address the shortcomings of the prior art by proposing a machine learning-based method for locating hardware Trojans in a gate-level netlist, thereby improving the accuracy and efficiency of hardware Trojan location without the need to refer to an ideal model.
[0010] To achieve the above objectives, the technical solution of the present invention includes the following steps:
[0011] (1) Divide the integrated circuits in the sample into multiple maximum single-output sub-modules;
[0012] (2) The dataset is constructed by extracting features from each maximum single output submodule in the integrated circuit and divided into training set and test set in a ratio of 7:3.
[0013] (3) Use cross-validation to train the machine learning model and obtain a trained classifier;
[0014] (4) Select a gate-level netlist to be tested for Trojan detection and output the detection results;
[0015] (5) Determine whether the output of step (4) contains a hardware Trojan:
[0016] If no hardware Trojan is found, the location is complete;
[0017] Otherwise, proceed to step (6);
[0018] (6) Locate the detected hardware Trojan:
[0019] (6a) Let the current gate-level netlist be C, let the "golden design" version of C without Trojan implantation be C', and divide C and C' into multiple maximal single-output sub-modules, and extract the feature vector of each maximal single-output sub-module;
[0020] (6b) For a maximal single-output submodule a of C detected in step (4) that has been implanted with a Trojan, find the maximal single-output submodule a that is closest to C' based on the Euclidean distance between the feature vectors, and denote it as a'.
[0021] (6c) Perform a Trojan search based on layer-by-layer difference analysis on a and a' to obtain multiple Trojan regions;
[0022] (6d) For all the maximum single-output submodules detected in step (4), execute steps (6b) to (6c) to obtain the Trojan region.
[0023] Compared with the prior art, the present invention has the following advantages:
[0024] First, by dividing the integrated circuit under test into multiple maximally single-output sub-modules, this invention can further divide the overlapping areas of different logic cones in the traditional method of dividing integrated circuits by logic cones, thus simplifying the operation in the hardware Trojan detection and location process and improving the efficiency of hardware Trojan detection and location.
[0025] Secondly, in hardware Trojan detection, since this invention divides the gate-level netlist of the integrated circuit into multiple maximal single-output sub-modules, each of which operates independently during hardware Trojan detection, it facilitates parallel detection of multiple maximal single-output sub-modules, effectively shortening the time required to detect large-scale integrated circuits. Furthermore, because this invention constructs the dataset using maximal single-output sub-modules rather than the entire gate-level netlist, the size of the constructed dataset increases by tens of times, significantly improving the performance of the trained classifier and thus enhancing the accuracy of Trojan detection.
[0026] Third, in terms of hardware Trojan location, since this invention divides the gate-level netlist of the integrated circuit into multiple maximal single-output sub-modules, most of the logic gates and signal lines in each finally located Trojan area belong to hardware Trojans, thus improving the accuracy of Trojan location. Attached Figure Description
[0027] Figure 1 This is a flowchart illustrating the implementation of the present invention;
[0028] Figure 2 This is a schematic diagram of the maximum single-output submodule partitioning in this invention;
[0029] Figure 3 This is a schematic diagram of Trojan horse search based on layer-by-layer difference analysis in this invention. Detailed Implementation
[0030] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0031] Reference Figure 1 The implementation steps for this example are as follows:
[0032] Step 1: Obtain integrated circuit samples and divide the integrated circuits in the samples into multiple maximally single-output sub-modules.
[0033] (1.1) Select gate-level netlists of multiple integrated circuits as samples, which contain multiple "golden designs" without Trojans, and various versions of each "golden design" when different Trojans are implanted;
[0034] (1.2) For each gate-level netlist in the sample, divide it into multiple maximal single-output sub-modules:
[0035] (1.2.1) Taking the logic gates in the gate-level netlist as vertices and the signal line branches as directed edges, that is, the starting point is the input pin of the logic gate and the ending point is the output pin of the logic gate, the gate-level netlist is abstracted into a directed graph. The gate to which each main output pin in the gate-level netlist belongs corresponds to a "merging node" in the directed graph, forming a set of merging nodes T.
[0036] (1.2.2) Perform a breadth-first traversal on the maximal single-output submodule starting from a merging node t in the merging node set. For node i during the traversal, determine whether all output nodes connected to it belong to the maximal single-output submodule:
[0037] If so, add node i to the maximum single output submodule and execute step (1.2.3);
[0038] Otherwise, node i is considered a merge node, and it is added to the merge node set T, and (1.2.3) is executed;
[0039] (1.2.3) Repeat step (1.2.2) for all nodes in the maximal single-output submodule starting from the merging node t until all nodes have been traversed, thus forming a maximal single-output submodule with the logic gate corresponding to the merging node t as the vertex.
[0040] (1.2.4) Repeat steps (1.2.2) to (1.2.3) for all the merge nodes in the merge node set T to divide the gate-level netlist into multiple maximal single-output sub-modules.
[0041] (1.3) Perform step (1.2) on all gate-level netlists in the sample to obtain multiple maximal output submodules of the sample.
[0042] Step 2: Extract features from multiple maximum output sub-modules in the integrated circuit to form a dataset, and divide it into a training set and a test set.
[0043] (2.1) Extract the static structural features of each maximal single-output submodule, construct a feature vector, and add a label to the end of the feature vector according to whether the maximal single-output submodule contains a hardware Trojan, i.e. 1 represents yes and 0 represents no. Merge the feature vectors of all maximal single-output submodules into a matrix.
[0044] (2.2) Perform step (2.1) on the maximum output submodule of all gate-level netlists in the sample to obtain multiple matrices. Merge these matrices by row and remove duplicate rows. The resulting matrix is the dataset.
[0045] (2.3) Divide the dataset into a training part and a testing part in a 7:3 ratio.
[0046] Step 3: Train the machine learning model to obtain a trained classifier.
[0047] K-nearest neighbor, decision tree, and Naive Bayes classifiers are trained using cross-validation. For each classifier, parameters are dynamically adjusted based on the cross-validation scores to achieve optimal results, resulting in a well-trained classifier.
[0048] Step 4: Divide the gate-level netlist of an integrated circuit under test into two maximal single-output sub-modules.
[0049] Reference Figure 2 The implementation of this step is as follows:
[0050] (4.1) With logic gates as vertices and signal line branches as directed edges, the gate-level netlist is abstracted into a directed graph. Then, the logic gate G4 to which the main output pin PO1 belongs and the logic gate G8 to which the main output pin PO2 belongs correspond to two merging nodes t1 and t2 in the directed graph, which together form a merging node set T.
[0051] (4.2) Perform a breadth-first traversal on the maximal single-output submodule starting from the merging node t1. When traversing to logic gate G2, since one of the output nodes G6 of G2 does not belong to the current maximal single-output submodule, logic gate G2 is added to the merging node set T as a merging node t3, and the breadth-first traversal continues. After the traversal is completed, the main input pins PI1~PI3, main output pins PO1, signal lines W1~W2, and logic gates G1, G3, and G4 obtained from the traversal of merging node t1 are assigned to the maximal single-output submodule a.
[0052] (4.3) Perform a breadth-first traversal of the maximal single-output submodule starting from the merging node t2. When the traversal reaches the main input pin PI4, since one of the output nodes G2 of PI4 does not belong to the current maximal single-output submodule, PI4 is added to the merging node set T as a merging node t4 and the traversal continues. After the traversal is completed, the main input pins PI5~PI6, main output pins PO2, signal lines W4~W6 and logic gates G5~G8 obtained by traversing the merging node t2 are assigned to the maximal single-output submodule b.
[0053] (4.4) Perform a breadth-first traversal of the maximal single-output submodule starting from the merging node t3. After the traversal is completed, the main input pin PI3 and logic gate G2 obtained from the traversal of the merging node are assigned to the maximal single-output submodule c.
[0054] (4.5) Perform a breadth-first traversal of the maximal single-output submodule starting from the merging node t4. Since the traversal of PI4 is empty, only the main input pin PI4 is assigned to the maximal single-output submodule d.
[0055] Step 5: Extract the feature vectors of the maximal single-output submodules a, b, c, and d obtained by traversing the four merging nodes, and use these feature vectors to construct a feature matrix.
[0056] (5.1) Traverse the four maximum single-output submodules a, b, c, and d respectively, and calculate the 10 hardware Trojan-related characteristics for each of them: number of main inputs, number of main input branches, number of main outputs, number of main output branches, number of logic gates, number of flip-flops, number of signal lines, total fan-in, total fan-out, and number of loops. The specific interpretation of each hardware Trojan-related characteristic is shown in Table 1:
[0057] Table 1. Detailed Explanation of Hardware Trojan-Related Characteristics
[0058] Feature name describe Main input number The number of main input pins contained in the maximum single output submodule Number of inbound branches The number of logic gate input pins connected to the main input pin in the maximum single-output submodule Main output number The number of main output pins contained in the maximum single output submodule Number of branches The number of logic gate input pins connected to the main output pin in the maximum single-output submodule Number of logic gates The number of basic logic gates contained in the maximum single-output submodule Number of triggers The number of flip-flop logic gates contained in the maximum single-output submodule Number of signal lines The number of internal connections contained in the maximum single-output submodule Total fan-in The sum of the number of input logic gates in all logic gates of the maximum single-output submodule Total fan out The sum of the number of output logic gates of all logic gates in the maximum single-output submodule Number of circuits The number of loops (i.e., simple cycles in a directed graph) contained in a maximally single-output submodule.
[0059] (5.2) Arrange the 10 hardware Trojan-related features of the four maximal single-output submodules a, b, c, and d in order to form the feature vectors of the maximal single-output submodules a, b, c, and d, as shown in Table 2:
[0060] Table 2. Feature vector values of different maximum single-output submodules
[0061]
[0062] (5.3) The eigenvectors of the maximal single-output submodules a, b, c, and d are merged to form a feature matrix, Matrix, as follows:
[0063]
[0064] Step 6: Based on the feature matrix Matrix, the classifier predicts the label vectors corresponding to the four maximal output sub-modules a, b, c, and d obtained by traversing the four merge nodes respectively.
[0065] (6.1) Input the feature matrix Matrix into three classifiers: K nearest neighbor, decision tree, and Naive Bayes classifier. Predict a corresponding four-dimensional label column vector through each classifier to obtain three different four-dimensional label column vectors.
[0066] (6.2) The first dimension of these three different four-dimensional label column vectors forms the label vector v1 corresponding to the maximal single-output submodule a; the second dimension of these three different four-dimensional label column vectors forms the label vector v2 corresponding to the maximal single-output submodule b; the third dimension of these three different four-dimensional label column vectors forms the label vector v3 corresponding to the maximal single-output submodule c; and the fourth dimension of these three different four-dimensional label column vectors forms the label vector v4 corresponding to the maximal single-output submodule d, as shown below:
[0067] v1 = (1 1 0),
[0068] v2 = (0 0 0),
[0069] v3 = (0 0 0),
[0070] v4 = (0 0 0).
[0071] Step 7: Based on the tag vectors corresponding to the four maximum single-output submodules, detect the hardware Trojans in the gate-level netlist to be tested, and output the hardware Trojan set M.
[0072] This step determines whether a hardware Trojan has been implanted in a maximally single-output submodule based on whether at least one of its label vectors is 1, and sets the hardware Trojan set M to empty.
[0073] (7.1) Determine the label vectors of the four maximal single-output submodules obtained from the four merging nodes in the gate-level netlist to be tested:
[0074] If there are two tags of 1 in the tag vector v1 corresponding to the maximum single output submodule a, it is considered that a has been implanted with a hardware Trojan, and a is added to the hardware Trojan set M. The tag vector of b is then judged.
[0075] If all the labels in the label vector v2 corresponding to the maximum single output submodule b are 0, it is considered that no hardware Trojan has been implanted in b, and the label vector of c is judged.
[0076] If all the labels in the label vector v3 corresponding to the maximum single output submodule c are 0, it is considered that no hardware Trojan has been implanted in c, and the label vector of d is judged.
[0077] If all the labels in the label vector v4 corresponding to the maximal single-output submodule d are 0, it is assumed that no hardware Trojan has been implanted in d, and step (7.2) is executed.
[0078] (7.2) Output hardware Trojan set M.
[0079] Step 8: Locate the trojan in the maximum output submodule a of the hardware trojan set M, which has the hardware trojan implanted.
[0080] Reference Figure 3 The implementation of this step is as follows:
[0081] (8.1) Let the current gate-level netlist be C, let the "golden design" version of C without Trojan implantation be C', and divide C' into multiple maximal single-output sub-modules, and extract the feature vector of each maximal single-output sub-module;
[0082] (8.2) Based on the Euclidean distance between the eigenvectors, find the maximal single-output submodule that is closest to a in C', and denote it as a';
[0083] (8.3) Perform a Trojan search based on layer-by-layer difference analysis on a and a' to obtain multiple Trojan regions.
[0084] (8.3.1) Comparing the first level, both a and a' contain only logic gate G5 in the first level, and the two logic gates are of the same type, both being two-input OR gates. Therefore, we continue to traverse and compare the logic gates at the next position to obtain the second level.
[0085] (8.3.2) Comparing the second layer, the logic gates of a in the second layer are G4 and T3, while the logic gates of a' in the second layer are G4 and G3. The logic gate G4 of both a and a' is a two-input OR gate. However, since the logic gate T3 of a is a two-input AND gate and the logic gate G3 of a' is an inverter, the logic gate T3 of a is recorded as a Trojan output gate, and the logic gate T3 of a and the logic gate G3 of a' are excluded. Continue to traverse and compare the logic gates at the next position to obtain the third layer.
[0086] (8.3.3) Comparing the third level, both a and a' contain logic gates G1 and G2 in the third level. Both logic gates G1 are two-input AND gates, and both logic gates G2 are two-input NAND gates. Therefore, we continue to traverse and compare the logic gates at the next position to obtain the fourth level.
[0087] (8.3.4) Comparing the fourth level, the fourth level of both a and a' is empty, so the traversal ends;
[0088] (8.3.5) For the unique Trojan output gate T3, perform a breadth-first traversal with a depth of 8 starting from it to obtain the unique Trojan region D in a, which contains logic gates T3, T2, T1, G3 and main input pins PI5 and PI6.
[0089] The above description is merely a specific example of the present invention and does not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and details without departing from the principles and structure of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.
Claims
1. A method for locating hardware Trojans in a gate-level netlist based on machine learning, characterized in that, Includes the following steps: (1) Divide the integrated circuits in the sample into multiple maximally single-output sub-modules; including the following steps: 1a) Using logic gates as vertices and signal line branches as directed edges, i.e., the starting point is the input pin of the logic gate and the ending point is the output pin of the logic gate, the gate-level netlist is abstracted into a directed graph. In this graph, the gate to which each main output pin belongs in the gate-level netlist corresponds to a "merging node" in the directed graph, forming a set of merging nodes T. 1b) Perform a breadth-first traversal of the maximal single-output submodule starting from a merging node t in the merging node set. For node i during the traversal, determine whether all output nodes connected to it belong to the maximal single-output submodule: If so, add node i to the maximal single-output submodule and execute step 1c). Otherwise, if node i is considered a merging node, it is added to the merging node set T, and 1d is executed. 1c) Repeat step (1b) for all nodes in the maximal single-output submodule starting from the merging node t until all nodes have been traversed, thus forming a maximal single-output submodule with the logic gate corresponding to the merging node t as the vertex. 1d) Repeat steps 1b) to 1c) for all the merge nodes in the merge node set T to divide the gate-level netlist into multiple maximal single-output sub-modules; (2) The dataset is constructed by extracting features from each maximum single output submodule in the integrated circuit and divided into training set and test set in a ratio of 7:3; (3) Use cross-validation to train the machine learning model and obtain the trained classifier; (4) Select a gate-level netlist to be tested for Trojan detection, and output the detection results as follows: 4a) Select a gate-level netlist and let the hardware Trojan set of the gate-level netlist be M. At this time, M is empty. 4b) Divide the gate-level netlist into multiple maximal single-output sub-modules, extract the feature vector of each maximal single-output sub-module, and use the feature vectors of all maximal single-output sub-modules to form a feature matrix; 4c) Input the feature matrix into the K nearest neighbor, decision tree, and Naive Bayes classifier respectively to predict the corresponding label vector; 4d) For each maximal single-output submodule, determine whether the label vector predicted by its classifier has at least one label of 1: If so, it is considered that a hardware Trojan has been implanted and added to the hardware Trojan set M, and the next maximum single output submodule is then judged. Otherwise, continue to check the next maximum single-output submodule; 4e) Repeat step 4d) for all maximal single-output submodules in the gate-level netlist until all maximal single-output submodules have completed the judgment operation, then check whether the hardware Trojan set M of the gate-level netlist is empty: If so, report that it does not contain a hardware Trojan; Otherwise, output its hardware Trojan set M; (5) Determine whether the output of step (4) contains a hardware Trojan: If no hardware Trojan is found, the test is complete. Otherwise, proceed to step (6); (6) Locate the detected hardware Trojan: (6a) Let the current gate-level netlist be C, and let the "golden design" version of C without malware be C'. C and C' are divided into multiple maximal single-output sub-modules, and the feature vector of each maximal single-output sub-module is extracted. (6b) For a maximal single-output submodule a of C detected in step (4) that has been implanted with a Trojan, find the maximal single-output submodule a that is closest to C' based on the Euclidean distance between the feature vectors, and denote it as a'; (6c) Perform a Trojan search based on layer-by-layer difference analysis on a and a' to obtain multiple Trojan regions; (6d) For all the maximum single-output submodules detected in step (4), execute steps (6b) to (6c) to obtain the Trojan region.
2. The method according to claim 1, characterized in that, In step (2), feature extraction is performed on each maximally single-output submodule in the integrated circuit to form a dataset, as follows: 2a) Select gate-level netlists of multiple integrated circuits as samples, which contain multiple "golden designs" without Trojans, and various versions of each "golden design" when different Trojans are implanted; 2b) For each gate-level netlist in the sample, divide it into multiple maximal single-output sub-modules, extract the static structural features of each maximal single-output sub-module, construct a feature vector, and add a label to the end of the feature vector according to whether the maximal single-output sub-module contains a hardware Trojan, i.e. 1 represents yes and 0 represents no. Merge the feature vectors of all maximal single-output sub-modules into a matrix. 2c) Perform step (2b) on all gate-level netlists in the sample to obtain multiple matrices. Merge these matrices by row and remove duplicate rows. The resulting matrix is the dataset.
3. The method according to claim 1, characterized in that, In step (6c), a Trojan horse search based on layer-by-layer difference analysis is performed on a and a', as follows: 6c1) Starting from the corresponding vertex, perform breadth-first traversal (BFS) on the directed graphs corresponding to a and a' in parallel. During the BFS process, compare the logic gate sequences visited by a and a' at the same traversal depth in order, and record the logic gates at the same position in these two logic gate sequences as g and g', respectively. 6c2) Compare whether g and g' have the same type: If g and g' are of different types, first record g as a "Trojan output gate", and in the next depth traversal of a and a', exclude g and g' respectively, and then continue to compare the types of logic gates g and g' at the next position; If g and g' have the same type, then continue to compare the types of the logic gates g and g' at the next position; 6c3) Repeat step (6c2) until all logic gates of a or a' have been traversed, resulting in multiple Trojan output gates; 6c4) Perform a breadth-first traversal on each Trojan output gate, and divide all non-repeating logic gates, signal lines, main input pins, and main output pins visited during the traversal into a "Trojan region"; 6c5) Perform step (6c4) on all obtained Trojan output gates to obtain multiple Trojan regions.
4. The method according to claim 3, characterized in that, In step (2b), the static structural features of each maximum single-output submodule are extracted, including: the number of main inputs, the number of main input branches, the number of main outputs, the number of main output branches, the number of logic gates, the number of flip-flops, the number of signal lines, the total fan-in, the total fan-out, and the number of loops, totaling 10 features.