Single-event multiple-flip (SFM) processing methods, devices, FPGAs, and media for FPGAs

Abstract

This invention discloses a method, apparatus, FPGA, and medium for single-event multi-bit flip (SIF) processing on an FPGA. The method includes: determining the physical address corresponding to the FPGA resources, the FPGA bit stream region, and the resource state; performing a radiation experiment on the FPGA; and extracting m elements M of the set space during the fault time within the data extraction cycle based on the physical address corresponding to the FPGA resources, the FPGA bit stream region, and the resource state; and extracting elements M of the set control during the fault time within the data extraction cycle. i and element M j This method involves determining the offset set, identifying single-event multiple-flip (SFM) events within the FPGA based on the offset set, and then formulating a hardening strategy. This approach enables direct analysis of SFM events occurring within the FPGA during radiation experiments, allowing for the development of hardening strategies to improve the reliability of the FPGA system.

Description

Technical Field

[0001] This invention relates to the field of FPGA technology, and in particular to a method, apparatus, FPGA, and medium for single-event multi-bit flip processing of FPGA. Background Technology

[0002] High-performance field-programmable gate arrays (FPGAs) have high transistor density, which significantly increases charge sharing between adjacent cells, leading to more severe single-event multiple-bit upsets (MBUs). Currently, MBUs have become a major threat to high-reliability FPGA systems in space applications. However, the difficulty in identifying MBUs within FPGAs in related technologies makes it impossible to develop protection strategies against them, thus reducing the reliability of FPGA systems. Summary of the Invention

[0003] This invention aims to at least partially solve one of the technical problems in the related art. Therefore, one object of this invention is to provide a method, apparatus, FPGA, and medium for single-event multiple-bit flip processing of FPGAs that can improve the reliability of FPGA systems.

[0004] A single-event multi-bit flip (SIF) processing method for FPGA includes the following steps:

[0005] Determine the physical address, FPGA bit stream region, and resource status corresponding to the FPGA resources;

[0006] Radiation experiments were conducted on the FPGA, and based on the physical address corresponding to the FPGA resources, the FPGA bit stream region and resource status, m elements M of the set space were extracted during the fault time in the data extraction cycle, where the coordinates of an element M were defined as (x, y).

[0007] The element M of the space is set according to the fault time within the data extraction cycle. i and element M j Determine the offset set; where x i <x j , or, x i =x j And y j <y j The offset set contains the offsets Δx and Δy of the single-particle flip data;

[0008] The single-event multi-bit flip of the FPGA is determined based on the offset set, and a hardening strategy is formulated based on the single-event multi-bit flip of the FPGA.

[0009] In the above scheme, the hardening strategy based on the single-event multiple-bit flip of the FPGA includes:

[0010] Based on the single-event multiple-flip (SEF) of FPGA, determine the characteristics of SEF in FPGA.

[0011] Based on the characteristics of single-event multiple-flip (SEF) in FPGAs, a hardening strategy is developed for each type of SEF.

[0012] In the above scheme, based on the characteristics of single-event multiple-flip (SEF) in FPGAs, a hardening strategy is formulated for each type of SEF, including:

[0013] Based on the characteristics of single-event multiple-flip (SFM) in FPGA, determine the coverage area corresponding to each type of SFM.

[0014] Based on the coverage area corresponding to each type of single-particle multi-flip, determine the critical spacing corresponding to each type of single-particle multi-flip.

[0015] Based on the critical spacing corresponding to each type of single-particle multi-flip, a reinforcement strategy is formulated for each type of single-particle multi-flip.

[0016] In the above scheme, the features of FPGA single-event multiple-flip (SFM) include at least the number of flipped bits in SFM, the graphic feature form corresponding to different numbers of flipped bits, the SFM generation ratio, and the event cross-section corresponding to different SFM types.

[0017] In the above scheme, determining the single-event multi-bit flip of the FPGA based on the offset set includes:

[0018] The first probability is determined based on the offsets in the offset set; the first probability represents the probability of any offset in the offset set; any offset is any combination of offsets in the offset set.

[0019] Based on the first probability, the second probability is determined; the second probability represents the probability that any offset will occur at a set frequency.

[0020] The offset corresponding to the second probability being greater than the set value is determined as the offset corresponding to the single-particle multi-bit flip of the FPGA.

[0021] The above scheme determines the physical address, FPGA bitstream region, and resource status corresponding to the FPGA resources, including:

[0022] Based on the FPGA's bitstream file and resource location file, the physical address, FPGA bitstream region, and resource status corresponding to the FPGA resources are determined; the bitstream file and resource bit file are generated based on the FPGA's configuration and bitstream generation software.

[0023] The above scheme determines the physical address, FPGA bitstream region, and resource status corresponding to the FPGA resources, including:

[0024] The bit stream of the FPGA is parsed based on the development project script to determine the physical address, bit stream region, and resource status of the FPGA resources.

[0025] A single-event multi-bit flip processing device for FPGA, comprising:

[0026] The first determining module is used to determine the physical address, FPGA bit stream region, and resource status corresponding to the FPGA resources;

[0027] The extraction module is used to perform radiation experiments on the FPGA and extract m elements M in the set space during the fault time within the data extraction cycle based on the physical address corresponding to the FPGA resources, the FPGA bit stream region and the resource status. The coordinates of an element M are defined as (x, y).

[0028] The second determining module is used to set the element M of the space based on the fault time within the data extraction cycle. i and element M j Determine the offset set; where x i <x j , or, x i =x j And y j <y j The offset set contains the offsets Δx and Δy of the single-particle flip data;

[0029] The third determination module is used to determine the single-event multi-bit flip of the FPGA based on the offset set, and to formulate a hardening strategy based on the single-event multi-bit flip of the FPGA.

[0030] An FPGA includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above method.

[0031] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0032] The aforementioned method, apparatus, FPGA, and medium for processing single-event multiple-flip (SEV) events in FPGAs determine the physical address, bitstream region, and resource status of the FPGA resources. A radiation experiment is conducted on the FPGA, and SEV data within a defined space is captured during the fault time within the data extraction cycle based on the physical address, bitstream region, and resource status. The SEV data is then processed to obtain its offset. Based on this offset, the SEV events in the FPGA are determined, and a hardening strategy is formulated. This allows for direct analysis of SEV events occurring within the FPGA during the radiation experiment, facilitating further analysis and processing of SEV events in the FPGA. This enables targeted hardening design for SEV events in the FPGA, improving the reliability of the FPGA system.

[0033] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0034] Figure 1 This is a flowchart illustrating a single-event multi-bit flip (SIF) processing method for an FPGA in one embodiment.

[0035] Figure 2 This is a flowchart illustrating the single-event multi-bit flip processing method for FPGA in yet another embodiment.

[0036] Figure 3 This is a flowchart illustrating the single-event multi-bit flip processing method for FPGA in yet another embodiment.

[0037] Figure 4 This is a flowchart illustrating the single-event multi-bit flip processing method for FPGA in yet another embodiment.

[0038] Figure 5 This is a schematic diagram of the process for resolving and protecting against single-event multiple-flip (SFM) flips inside an FPGA in one embodiment.

[0039] Figure 6 This is a block diagram of a single-event multi-bit flip processing device for an FPGA in one embodiment. Detailed Implementation

[0040] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0041] Before providing a detailed description of the embodiments of the present invention, we will first briefly introduce the single-event multiple flip that occurs inside the FPGA.

[0042] In a radiation environment such as space, the logical state of internal resources such as memory, registers, and latches in a circuit system can change due to the influence of a single charged particle, causing errors in the circuit's logical function and resulting in non-destructive information loss. This change in circuit logic function is called a single-event effect, and the non-destructive but data-error phenomenon caused by the single-event effect is called a soft error.

[0043] FPGAs can be rapidly programmed and reconfigured according to load and requirements, making them suitable for complex electronic systems. SRAM-based FPGAs, with their advantages of reconfigurability and high integration, have strongly supported the development of my country's aerospace technology. However, FPGAs primarily control logic states through configuration code streams. Influenced by ground-based and atmospheric neutrons, this can lead to changes in the configuration information of storage units and wiring, causing soft errors (i.e., flips) and threatening the security of the FPGA system. SRAM-based FPGAs are highly sensitive to single-event effects and are easily affected by radiation, resulting in single-event flips and data errors. This is particularly pronounced in FPGA circuits at 28nm and below nodes. On the one hand, the critical charge for device flips decreases, making the devices more sensitive; on the other hand, the smaller device process nodes and increased transistor density lead to severe single-event multiple flips caused by single events, making redundancy and error correction techniques ineffective and causing hardening strategies to fail. Furthermore, the high operating frequency and data transmission rate of high-performance FPGAs also exacerbate problems such as a high proportion of single-event failures, difficulties in testing and characterization, decreased fault location accuracy, and reduced effectiveness of general protection measures, affecting the on-orbit data security of computing chips and leading to an increased spacecraft failure rate.

[0044] Error detection and correction (EDAC), double interlocked storage cells (DICE), and special layout hardening techniques are severely limited by single-event faults (SETs). Furthermore, these hardening methods primarily target all resources, failing to address SETs directly with dedicated hardening techniques to conserve resources. While process hardening enhances resistance to SETs, its high cost hinders widespread adoption. Unlike common SRAM and Flash memory, SETs within FPGA logic resources are more difficult to identify and detect. Data readback methods struggle to accurately extract SET information from configuration RAM (CRAM) and other resources, making it even more difficult to analyze SET characteristics without considering underlying device information. Consequently, SETs negatively impact FPGA system reliability.

[0045] Based on this, the FPGA single-event multiple-flip (SEV) processing method provided in this embodiment of the invention can effectively locate SEVs inside the FPGA and carry out targeted hardening design based on SEVs, thereby improving the system reliability of the FPGA and also saving resources.

[0046] The implementation details of the technical solutions of the embodiments of the present invention are described in detail below.

[0047] In one embodiment, such as Figure 1 As shown, a single-event multiple-factor (SEM) flip-over (SEM) processing method for FPGAs is provided. This SEM flip-over (SEM) processing method for FPGAs may include the following steps:

[0048] Step S101: Determine the physical address, FPGA bit stream region, and resource status corresponding to the FPGA resources.

[0049] The resources mentioned here refer to those used in the FPGA, such as Configurable Logic Blocks (CLBs) and Look-Up Tables (LUTs). CLBs are the main logic resources used to implement sequential and combinational circuits, while LUTs are a type of storage resource in the FPGA used to implement combinational and sequential logic.

[0050] During the operation of an FPGA, each resource used contains two addresses: a physical address and a bit address in the bit stream.

[0051] The physical address of a resource in an FPGA is represented by coordinates (X, Y), where the X-axis represents the resource's horizontal position in the FPGA, and the Y-axis represents its vertical position. The physical address of a resource corresponds to an actual logic gate module on the FPGA.

[0052] The bit address in the bit stream is also the FPGA bit stream region. The FPGA bit stream region contains the resource status, which is represented by binary values. That is, the binary values ​​are the logical status values ​​of the resources, and different binary values ​​correspond to different logical functions of the circuit.

[0053] In this embodiment, two methods are provided to determine the physical address of the resource, the FPGA bit stream region, and the resource status.

[0054] In one embodiment, FPGA configuration and bitstream generation software can be used to design circuits for specific FPGA devices and generate corresponding bitstream files and resource location files. The resource location file specifies the resource types contained in the bitstream and their corresponding physical addresses, while the bitstream file specifies the bit addresses of the resources within the bitstream. Therefore, the physical addresses, FPGA bitstream regions, and resource states corresponding to the resources can be determined from the bitstream file and resource location file.

[0055] In another embodiment, a code stream comparison and parsing tool developed based on a scripting language within electronic design automation (EDA) tools can be used to perform full bit stream parsing on the FPGA while simultaneously implementing test circuit engineering in the FPGA via software. This allows for the determination of the correspondence between the entire bit stream information and resources, as well as the logical state, line by line and bit by bit. Based on this, the test bit stream design for single-event experiments can be automated and directly parsed using the tool to obtain the resource type, resource state, corresponding physical address, and FPGA bit stream region.

[0056] Both methods can be verified by adjusting the memory and flip-flop resource configurations in the project to find the corresponding changes in the bitstream code values.

[0057] Step S102: Perform a radiation experiment on the FPGA, and extract m elements M of the set space during the fault time within the data extraction cycle based on the physical address corresponding to the FPGA resources, the FPGA bit stream region and resource status.

[0058] Here, radiation experiments refer to placing FPGAs in an experimental environment to conduct single-event effect experiments. Radiation experiments involve various types of FPGA testing and require key aspects such as the development and design of single-event effect testing systems, methodologies for single-ion effect testing of high-performance FPGAs, and the selection of test vectors. Basic experimental characterization techniques will not be elaborated here.

[0059] During the radiation experiment, single-event upset (SET) data of the FPGA can be captured. Specifically, the physical address, bit stream region and resource status of the FPGA resources determined in step S101 are used to identify and extract the SET data in real time and accurately. When the resource status changes, an SET occurs, and the corresponding SET data can be extracted.

[0060] In this embodiment, the period for extracting single-event upset (SI) data should conform to the sensitivity law of single-event upsets induced by heavy-ion experiments in the device. For example, the irradiation setpoint for the radiation experiment is set to 100 ions·cm. 2 ·s -1 If the data extraction period is 1 second, then the data extraction period can be 1 second. When the extraction period of single-event upset data conforms to the sensitivity law of single-event upset caused by heavy ion experiments, the influence of multiple particle disturbances can be avoided, and the misjudgment rate of single-event upsets can be eliminated.

[0061] Radiation experiments can statistically confirm the amount of resources and their physical location on the FPGA. By combining the resource types, we can extract the differences to analyze the characteristics of single-event and single-event multiple-event flips.

[0062] Based on a single-event effect testing system and data extraction and analysis technology, the fault time within the data extraction cycle is determined. Elements in a defined space are extracted, enabling the extraction and analysis of single-event multiple-bit flips triggered in radiation experiments during subsequent processing. For example, in an FPGA, logic resources are arranged as frames and bits (i.e., rows and columns), and specific functions can be implemented by configuring a custom bit stream generated by software. The FPGA has 22,546 frames, each with 101 32-bit words. Data from all frames can be extracted, and single-event flip data can be obtained by filtering from them.

[0063] Suppose the defined space is a rectangle with length X and width Y. Extract the elements from this defined space, which contains m elements M. The elements of the defined space can be contained in a dataset Q, where Q = {M1, M2, ..., M}. m}, M i Let M be any one of the elements in the defined space. i Marked as (x i y i), (x i y i ) represents element M i The coordinates.

[0064] In this embodiment, by limiting the data extraction to a space within the fault time during the data extraction period, it is possible to incorporate time and spatial information dimensions to identify single-particle multi-position flips.

[0065] Step S103, set the spatial element M according to the fault time within the data extraction cycle. i and element M j Determine the offset set.

[0066] Here, high-energy heavy ions can induce single-event multiple-flip (SFM) in FPGAs. Since SFM is generated by a single ion, there are certain rules between the perturbations. SFM is affected by the spatial and temporal characteristics of the ions, as well as the sensitivity of the FPGA to SFM.

[0067] In this embodiment, the multi-position flip of a single particle is determined by the offset of the single particle. Elements M within a defined space have a specific relationship, and are sorted in ascending order. Assume that element M... i The coordinates are (x i y i ), element M j The coordinates are (x j ,yj), where A is used i Representative element M i The coordinates, using A j Representative element M j The coordinates, that is, A i =(x i y i A j =(x j y j If x i <x j , or, x i =x j And y i <y j In this case, then A is determined. i Less than A j Therefore, it is possible to base it on x j -x i Obtain the offset Δx based on y j -y i The offset Δy is obtained.

[0068] In practical applications, an offset set U is established based on the offsets Δx and Δy, and the offset set U = {(Aj -A i )|A i <A j A i A j ∈R}, where R refers to a real number.

[0069] Step S104: Determine the single-event multi-bit flip of the FPGA based on the offset set, and formulate a hardening strategy based on the single-event multi-bit flip of the FPGA.

[0070] Here, single-event multiple-flip (SFM) occurs within a certain pattern of perturbations. Based on this, the offset corresponding to the SFM data can be used to determine the offset caused by SFM. Thus, SFM can be identified from the SFM data, enabling direct analysis of SFM occurring inside the FPGA device from radiation experiments.

[0071] After identifying single-event multiple-flip (SFM) errors in an FPGA, targeted hardening designs can be implemented to address these SFM errors by locating them within the FPGA. Different hardening strategies can be proposed to enhance the reliability of the FPGA system. Since the hardening strategies are designed specifically for SFM errors in the FPGA, rather than hardening all resources in the FPGA, they can save resources and reduce the impact of SFM errors on the reliability of the FPGA system.

[0072] In one embodiment, such as Figure 2 As shown, the single-event multi-bit flip of the FPGA is determined based on the offsets in the offset set, including:

[0073] Step S201: Determine the first probability based on the offset in the offset set.

[0074] In the offset set U established based on offsets Δx and Δy, the Δx of each offset in the offset set U must be equal to or greater than 0. For example, the internal logic of the FPGA is arranged by frame and bit in the bit stream. Assume that the Nth bit x n The value is 21539, and the Nth y is... n Since the value is 3120, we can deduce that the range of the offset Δx is 0 to 21538, and the range of the offset Δy is -3120 to 3120, both of which are integers. Therefore, the N-bit offset is any combination of all Δx and Δy within the above ranges. When Δx = 0, these offsets must completely satisfy the increasing order rule. Based on this, the total L with repetition... N =N(N-1) / 2 offsets, then the probability (i.e., the first probability) of any offset in the offset set U can be expressed as:

[0075] p(β)=f(X~B(Nu ,p))

[0076] Here, arbitrary offset refers to an offset Δx ranging from 0 to 21538, and an offset Δy ranging from -3120 to 3120.

[0077] Step S202: Determine the second probability based on the first probability.

[0078] After each radiation test, n anomalies (n << N) can be observed. The offsets in the offset set U have a total of N repetitions. u = n(n-1) / 2. Assuming these flips are independent of each other, the probability of any offset occurring β times (i.e., the second probability) follows a classical binomial distribution:

[0079] p(β)=f(X~B(N u ,p))

[0080] Step S203: The offset corresponding to the second probability being greater than the set value is determined as the offset corresponding to the single-particle multi-bit flip of the FPGA.

[0081] By setting a confidence interval, the offset that occurs β times with a probability greater than the set value is extracted as the offset caused by single-event multi-position flip. Since this offset violates the independence between perturbations, single-event multi-position flip can be extracted from single-event flip data based on the offset.

[0082] In one embodiment, such as Figure 3 As shown, the hardening strategy based on the single-event multi-bit flip of the FPGA includes:

[0083] Step S301: Determine the characteristics of single-event multiple-flip (SEF) of the FPGA based on the SEF.

[0084] Here, by processing single-event multi-flip (SFM) data, we can obtain a SFM feature dataset (i.e., a SFM failure set) caused by radiation. This SFM feature dataset can provide technical preparation for the implementation of hardening strategies, ensuring that the hardening strategies are designed specifically for SFM rather than for all resources.

[0085] In one embodiment, the single-event multi-bit flip (SFP) feature dataset includes the types of SFPs, the graphical feature forms corresponding to different numbers of flipped bits, the generation rate of SFPs, and the event interfaces corresponding to different SFP types. As shown in Table 1, Table 1 records the features of SFPs.

[0086] Table 1

[0087]

[0088]

[0089] In Table 1, K represents the number of flipped bits in a single-event multi-bit flip. The types of single-event multi-bit flips are classified based on the number of flipped bits; that is, each number of flipped bits corresponds to a type of single-event multi-bit flip. For example, the types of single-event multi-bit flips include 1-bit, 2-bit...10-bit and above flips. i in Table 1 represents the different graphical features that appear in the case of K-bit flips.

[0090] Flip cross sections of various types of single-particle multi-position flips Where K = 1, 2, 3…; i = 1, 2, 3…, σ K_i Let K be the flipping cross section of the i-th type of single-particle multi-flipping, where K is the particle flux per unit area.

[0091] Step S302: Based on the characteristics of single-event multiple-flip (SEF) in FPGA, formulate a hardening strategy for each type of SEF.

[0092] Here, based on the characteristics of single-event multiple-flip (SEF) in FPGAs, it is possible to determine the ability of a single particle to cause charge-sharing effects in the FPGA, thereby determining the distribution pattern of transistor-sensitive actives, and further, based on this pattern, to formulate a hardening strategy for each type of SEF.

[0093] In one embodiment, such as Figure 4 As shown, based on the characteristics of single-event multiple-flip (SEF) in FPGAs, hardening strategies are formulated for each type of SEF, including:

[0094] Step S401: Based on the characteristics of single-event multiple-flip (SEF) in FPGA, determine the coverage area corresponding to each type of SEF.

[0095] Here, electronic design automation tools can be used to determine the coverage area of ​​various types of single-event multiple-flip (SFM) in the FPGA, and the coverage area of ​​SFM is helpful in determining the hardening strategy.

[0096] Based on single-event multiple-flip (SEV) analysis, we analyze two causes of SEV: 1) SEV of storage resources and 2) SEV caused by peripheral circuits. This allows us to determine the area distribution of SEV caused by a single particle and the area distribution of SEV caused by peripheral circuits.

[0097] Step S402: Determine the critical spacing corresponding to each type of single-particle multi-position flip based on the coverage area corresponding to each type of single-particle multi-position flip.

[0098] Here, after determining the coverage area corresponding to each type of single-event multi-flip (SFM), the corresponding critical spacing can be determined. The critical spacing refers to the minimum spacing that is not affected by SFM. In practical applications, determining the critical spacing includes determining the critical spacing between adjacent memory cells, the critical spacing between adjacent bits, the critical spacing between identical slices, the critical spacing between identical repeating tiles, the critical spacing between adjacent tiles, and the critical spacing between non-adjacent tiles in an FPGA. Here, a slice is the basic logic unit of a 7-series FPGA, and repeating tiles are used to compose an FPGA.

[0099] Step S403: Based on the critical spacing corresponding to each type of single-particle multi-flip, formulate a reinforcement strategy corresponding to each type of single-particle multi-flip.

[0100] Here, determining the reinforcement strategy according to the critical spacing can be understood as the spacing between the multiple set bit flows needing to be greater than the critical spacing, which can ensure that the set bit flows are not within the coverage area corresponding to single-particle multi-bit flip, thereby making the bit flows unaffected by single-particle multi-bit flip.

[0101] In practical applications, the time probability and problem source of single-event multi-flips (SEVs) caused by external clocks, resets, and other resources are determined. The time constraints and spatial resource locations required for resource reuse or redundancy in these cases are calculated. Based on the area relationships corresponding to each type of SEV, reliability tolerance and the corresponding flip cross-section distribution are established, as shown in Table 2. Table 2 illustrates the fault-tolerant effects of hardening strategies for different types of SEVs.

[0102] Table 2

[0103]

[0104] Among them, σ in Table 2 t Let σlimit be the total flipping cross section, and σlimit be the limit flipping cross section under the realized conditions. Determine the percentage improvement in fault tolerance T when the corresponding critical spacing D is achieved through position constraints. K_i %.

[0105] In this embodiment, by providing protection schemes and corresponding fault tolerance improvement percentages for different needs, different task requirements can be met.

[0106] Step S404: Based on the critical spacing corresponding to each type of single-particle multi-flip, formulate a reinforcement strategy corresponding to each type of single-particle multi-flip.

[0107] Here, the critical spacing is defined as the critical spacing outside the coverage area of ​​single-event multi-bit flip. The spacing between corresponding bits in the set hardened bit stream is set to be greater than the critical spacing, which ensures that the corresponding bits in the set hardened bit stream are not affected by the single-event multi-bit flip effect at the same time, avoids hardening failure caused by multi-bit flip, and thus achieves the hardening effect.

[0108] In practical applications, there are two reasons that cause single-event multiple flips (SIF). We can set protection levels for these two reasons and use algorithm design to design isolation techniques to reinforce SIF.

[0109] The single-particle multi-flip caused by storage resources mainly revolves around its occurrence probability distribution and the area size of shots corresponding to different single-particle multi-flip types, determining whether D is satisfied. K_i The placement rules, based on Error Checking and Correction Code (ECC) technology, place redundant bits outside the influence range of single-event multi-flip (SFM) flips. In FPGA programming tools, using the hardware description language Verilog, ECC can still implement the parity bit design via Hamming code. The modules requiring hardening for SFM flips caused by this reason include data storage, parity bits, ECC encoding modules, and ECC decoding modules. Furthermore, the data bit spacing and parity bit area are designed to be consistent with T... K_i % corresponding to D K_i The correlation makes the spacing between the data points greater than D. K_i The placement of data bit spacing and parity bit areas is determined by physical spacing rules mapped through the FPGA and established to satisfy D. K_i The Slice information corresponding to the conditions is implemented in the EDA tool using the Verilog language through a user-defined constraint xdc file.

[0110] Single-event multiple-flip (SEF) caused by the peripheral circuit system is mainly mitigated through triple-mode redundancy (TMR) technology, and the TMR failure set is calculated in software. Based on the hardware description language Verilog, constraint files are designed using FPGA programming tools to limit the path spacing to be greater than the corresponding D. K_i That is, the minimum spacing L on the redundant path. min Greater than D K_i This mitigates the single-particle charge-sharing effect while also impacting multi-path systems. In the hardening of peripheral circuit systems, determining the critical spacing R between adjacent sites is crucial. bit-bit Critical spacing R of the same slice Slice-i Critical spacing R of the same tile Tile-i Critical spacing R between adjacent tiles Tile-Tile Critical spacing R between non-adjacent tiles CLBBy limiting the spacing between adjacent bits, identical slices, identical tiles, adjacent tiles, and non-adjacent tiles, single-event multi-bit flip hardening is achieved. During the hardening process, the reliability and performance requirements of the task can be evaluated and calculated, and finally, the hardened bit flow for single-event multi-bit flip is generated by software.

[0111] In one embodiment, such as Figure 5 so, Figure 5 A schematic diagram of the process for resolving and protecting against single-event multi-bit flips inside an FPGA is shown.

[0112] Step 1: Determine the test resource and its corresponding bitstream region and values. This essentially involves determining the physical address, FPGA bitstream region, and resource status of the test resource.

[0113] Step 2 involves conducting an irradiation experiment on the FPGA. The irradiation experiment essentially places the FPGA in an experimental environment to perform single-event effect experiments. In the irradiation experiment, by testing the physical address corresponding to the resource, the FPGA bitstream region, and the resource status, flip information can be identified and extracted in real time and accurately, thereby extracting multiple single-event flip data.

[0114] Step 2.1: Determine the single-particle multi-bit flip type and its corresponding FPGA bitstream characteristics.

[0115] Step 2.2: Determine the event probabilities of various single-particle multi-position flip types.

[0116] Step 2.3: Establish a feature set of single-particle multi-position flip data.

[0117] Step 3: Analyze the coverage area and influence patterns of different single-event multiple-flip (SFM) events. Here, by determining the coverage area of ​​SFM events, we can determine the distribution pattern of the transistor's sensitive active region. This allows us to identify the characteristic patterns of SFM events in memory resources caused by single-event events and those caused by peripheral circuits, thus facilitating subsequent hardening strategies.

[0118] Step 4, Hardening Strategy for Single-Effect Multiple-Flush (SEF). Based on the two causes of SEF, protection levels are set, and isolation techniques are designed using algorithms to harden SEF.

[0119] In the above embodiments, by determining the physical address, bit stream region, and resource status of the FPGA resources, a radiation experiment is performed on the FPGA. Based on the physical address, bit stream region, and resource status of the FPGA resources, m elements of the set space are extracted during the fault time within the data extraction period, and the offset of the single-event upset (SEI) data is determined. Then, the SEI multi-event upset is determined from it. This allows for the effective extraction and analysis of the SEI within the corresponding FPGA period, serving as an important basis for analyzing the radiation sensitivity of the FPGA device itself. Effective isolation and protection strategies can be proposed for SEI, thereby improving the reliability of the FPGA system.

[0120] This application also provides a single-event multi-bit flip processing device for FPGA, referenced. Figure 6 As shown, the single-particle multi-bit flip processing device 600 of the FPGA may include a first determining module 601, an extraction module 602, a second determining module 603, and a third determining module 604.

[0121] The first determining module 601 is used to determine the physical address, bit stream region, and resource status of the FPGA resources; the extraction module 602 is used to perform a radiation experiment on the FPGA and extract m elements M of the set space during the fault time in the data extraction cycle based on the physical address, bit stream region, and resource status of the FPGA resources; wherein, the coordinate position (x, y) of an element M is defined; the second determining module 603 is used to determine the m elements M of the set space during the fault time in the data extraction cycle. i and element M j Determine the offset set; where x i <x j , or, x i =x j And y j <y j The offset set contains the offsets Δx and Δy of the single-event flip data; the third determination module 604 is used to determine the single-event multi-bit flip of the FPGA based on the offset set, and to formulate a hardening strategy based on the single-event multi-bit flip of the FPGA.

[0122] Furthermore, the third determining module 604 is specifically used to determine the characteristics of the FPGA's single-event multi-flip based on the FPGA's single-event multi-flip; and to formulate a hardening strategy for each type of single-event multi-flip based on the characteristics of the FPGA's single-event multi-flip.

[0123] Furthermore, the third determining module 604 is specifically used to determine the coverage area corresponding to each type of single-event multi-flip based on the characteristics of the FPGA; determine the critical spacing corresponding to each type of single-event multi-flip based on the coverage area corresponding to each type of single-event multi-flip; and formulate a hardening strategy corresponding to each type of single-event multi-flip based on the critical spacing corresponding to each type of single-event multi-flip.

[0124] In one embodiment, the features of a single-event multiple-flip (SFM) FPGA include at least the number of flipped bits in the SFM, the graphical feature forms corresponding to different numbers of flipped bits, the SFM generation rate, and the event cross-sections corresponding to different SFM types.

[0125] Furthermore, the third determining module 604 is specifically used to: determine a first probability based on the offsets in the offset set; the first probability represents the probability of any offset in the offset set; any offset is any combination of offsets in the offset set; determine a second probability based on the first probability; the second probability represents the probability of any offset occurring at a set frequency; and determine the offset corresponding to the second probability being greater than a set value as a single-particle multi-bit flip of the FPGA.

[0126] Furthermore, the first determining module 601 is specifically used to determine the physical address, FPGA bit stream region, and resource status corresponding to the FPGA resources based on the FPGA bit stream file and resource location file; wherein, the bit stream file and resource location file are generated based on the FPGA configuration and bit stream generation software.

[0127] Furthermore, the first determining module 601 is specifically used to parse the bit stream of the FPGA based on the development project script, and determine the physical address, FPGA bit stream region and resource status corresponding to the FPGA resources.

[0128] Specific limitations regarding the FPGA-based single-event multiple-factor (SEM) processing device can be found in the above description of the FPGA SEM method. They will not be repeated here. Each module in the aforementioned FPGA SEM processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in a computer device, or stored in software within the computer device's memory, allowing the processor to call and execute the corresponding operations of each module.

[0129] In one embodiment, an FPGA is provided, including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement a single-event multi-bit flip processing method for the FPGA.

[0130] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements a single-event multi-bit flip processing method for an FPGA.

[0131] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0132] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0133] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0134] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0135] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A single-event multi-bit flip processing method for FPGA, characterized in that, include: Determine the physical address, FPGA bit stream region, and resource status corresponding to the FPGA resources; Radiation experiments were performed on the FPGA, and based on the physical address corresponding to the FPGA resources, the FPGA bit stream region and resource status, m elements M of the set space were extracted during the fault time in the data extraction period, where the coordinates of an element M were defined as (x, y). The element M of the space is set according to the fault time within the data extraction period. i and element M j Determine the offset set; where x i <x j , or, x i =x j And y i <y j The offset set includes the offsets Δx and Δy of single-particle flip data; The single-event multiple-flip (SFM) faults of the FPGA are determined based on the offset set, and a hardening strategy is formulated based on the SFM faults of the FPGA. The hardening strategy formulation based on the SFM faults of the FPGA includes: determining the characteristics of the SFM faults of the FPGA based on the SFM faults of the FPGA; and formulating a hardening strategy for each type of SFM fault based on the characteristics of the SFM faults of the FPGA, including: Based on the characteristics of single-event multi-flip in the FPGA, determine the coverage area corresponding to each type of single-event multi-flip. Based on the coverage area corresponding to each type of single-particle multi-flip, determine the critical spacing corresponding to each type of single-particle multi-flip. Based on the critical spacing corresponding to each type of single-particle multi-flip, a reinforcement strategy is formulated for each type of single-particle multi-flip.

2. The FPGA single-event multi-bit flip processing method according to claim 1, characterized in that, The features of the FPGA for single-event multiple-flip (SFM) include at least the number of flipped bits in the SFM, the graphical feature forms corresponding to different numbers of flipped bits, the SFM generation ratio, and the event cross-sections corresponding to different SFM types.

3. The FPGA single-event multi-bit flip processing method according to claim 1, characterized in that, Determining the single-event multi-bit flip of the FPGA based on the offset set includes: A first probability is determined based on the offsets in the offset set; the first probability represents the probability of any offset in the offset set; the arbitrary offset is any combination of offsets in the offset set. Based on the first probability, a second probability is determined; the second probability represents the probability that the arbitrary offset occurs at a set frequency. The offset corresponding to the second probability being greater than the set value is determined as the offset corresponding to the single-particle multi-bit flip of the FPGA.

4. The FPGA single-event multi-bit flip processing method according to claim 1, characterized in that, The process of determining the physical address, FPGA bit stream region, and resource status corresponding to the FPGA resources includes: Based on the bitstream file and resource location file of the FPGA, the physical address, FPGA bitstream region, and resource status corresponding to the resources of the FPGA are determined; wherein, the bitstream file and the resource location file are generated based on the configuration and bitstream generation software of the FPGA.

5. The FPGA single-event multi-bit flip processing method according to claim 1, characterized in that, The process of determining the physical address, FPGA bit stream region, and resource status corresponding to the FPGA resources includes: The bit stream of the FPGA is parsed based on the development project script to determine the physical address, FPGA bit stream region, and resource status corresponding to the FPGA resources.

6. A single-event multi-bit flip processing device for an FPGA, characterized in that, include: The first determining module is used to determine the physical address, FPGA bit stream region, and resource status corresponding to the FPGA resources; The extraction module is used to perform radiation experiments on the FPGA and extract m elements M in the fault time within the data extraction period based on the physical address corresponding to the FPGA resources, the FPGA bit stream region and the resource status. The coordinates of an element M are defined as (x, y). The second determining module is used to set an element M of the space based on the fault time within the data extraction period. i and element M j Determine the offset set; where x i <x j , or, x i =x j And y j <y j The offset set includes the offsets Δx and Δy of single-particle flip data; The third determining module is used to determine the single-event multiple-flip (SFM) of the FPGA based on the offset set, and to formulate a hardening strategy based on the SFM of the FPGA. The formulation of the hardening strategy based on the SFM of the FPGA includes: determining the characteristics of the SFM of the FPGA based on the SFM of the FPGA; and formulating a hardening strategy for each type of SFM based on the characteristics of the SFM of the FPGA, including: Based on the characteristics of single-event multi-flip in the FPGA, determine the coverage area corresponding to each type of single-event multi-flip. Based on the coverage area corresponding to each type of single-particle multi-flip, determine the critical spacing corresponding to each type of single-particle multi-flip. Based on the critical spacing corresponding to each type of single-particle multi-flip, a reinforcement strategy is formulated for each type of single-particle multi-flip.

7. An FPGA comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

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