Display device

Abstract

The present disclosure discloses a display device. The display device includes a display panel having a plurality of sub-pixels, the sub-pixels connected to a plurality of scan lines and a plurality of data lines; and a gate driver for supplying a high-level scan signal to the plurality of scan lines. The gate driver can include a first gate driver for outputting a low-level carry signal, a second gate driver for outputting a high-level scan signal based on the carry signal, a first clock signal line connected to the first gate driver and the second gate driver, and a second clock signal line connected to the first gate driver and the second gate driver. Accordingly, the gate driver can generate a high-level scan signal based on a low-level carry signal from the first gate driver.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0188205, filed on December 27, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety as if fully set forth herein. Technical Field

[0003] This disclosure relates to display devices, and more specifically, to display devices including gate drivers capable of controlling n-type transistors. Background Technology

[0004] Display devices used in computer monitors, televisions, mobile phones, etc., include self-emissive organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs) that require a separate light source.

[0005] Such display devices are finding increasing applications, including computer monitors and televisions, as well as personal portable devices. Therefore, research is underway to develop display devices with larger display areas and reduced size and weight.

[0006] Display devices can drive multiple sub-pixels using a gate driver that supplies scan signals and a data driver that supplies data voltages. The gate driver can be configured as an in-board gate (GIP), meaning the gate driver IC can be integrated into the display panel. Unfortunately, depending on the display device's driving scheme or the internal compensation method of the sub-pixels, the sub-pixel circuitry can become complex. Therefore, the components and area used for the gate driver to drive the sub-pixels increase, making it difficult to reduce the bezel area. Summary of the Invention

[0007] One object of this disclosure is to provide a display device including a gate driver capable of controlling an n-type transistor.

[0008] Another object of this disclosure is to provide a display device capable of outputting a high-level scan signal by using the previously used drive timing as is.

[0009] Another object of this disclosure is to provide a display device that can easily change the scan signal even if the type of transistor in the sub-pixel is changed.

[0010] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0011] According to one aspect of this disclosure, a display device is provided, comprising: a display panel defining a plurality of sub-pixels connected to a plurality of scan lines and a plurality of data lines; and a gate driver for supplying a high-level scan signal to the plurality of scan lines. The gate driver may include: a first gate driver for outputting a low-level carry signal; a second gate driver for outputting a high-level scan signal based on the carry signal; a first clock signal line connected to the first gate driver and the second gate driver; and a second clock signal line connected to the first gate driver and the second gate driver. Therefore, the gate driver according to an exemplary embodiment of this disclosure is capable of generating a high-level scan signal based on a low-level carry signal from the first gate driver.

[0012] Further details of the exemplary implementation are included in the detailed implementation and the accompanying drawings.

[0013] According to an exemplary embodiment of this disclosure, a gate driver capable of controlling an n-type transistor can be formed by adding circuitry to a gate driver suitable for controlling a p-type transistor.

[0014] According to an exemplary embodiment of this disclosure, a high-level scan signal can be easily generated using a gate driver and a drive timing sequence that has been verified to be reliable.

[0015] According to an exemplary embodiment of this disclosure, a high-level scan signal can be output by using the same driving timing for outputting a low-level scan signal as is.

[0016] The effects of this disclosure are not limited to those exemplified above, and this specification includes a variety of other effects. Attached Figure Description

[0017] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated into and constituting a part of this application, illustrate embodiments of the disclosure and, together with the specific embodiments, serve to explain various principles. In the drawings:

[0018] Figure 1 This is a schematic block diagram of a display device according to an exemplary embodiment of the present disclosure.

[0019] Figure 2 This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0020] Figure 3 This is a block diagram of a gate driver for a display device according to an exemplary embodiment.

[0021] Figure 4AThis is a circuit diagram of the first stage of a display device according to an exemplary embodiment of the present disclosure.

[0022] Figure 4B This is a circuit diagram of the second stage of a display device according to an exemplary embodiment of the present disclosure.

[0023] Figure 5 This is a timing diagram of the first and second stages of a display device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0024] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0025] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Any singular reference may include the plural unless expressly stated otherwise.

[0026] The component is interpreted to include the normal tolerance range, even if not explicitly specified.

[0027] When using terms such as “on top of,” “above,” “below,” and “beside” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately adjacent” or “directly.”

[0028] When an element or layer is placed "on" another element or layer, the other layer or element may be placed directly on or between the other elements.

[0029] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of this disclosure, the first component referred to below can be the second component.

[0030] Throughout the specification, the same reference numerals generally denote the same elements.

[0031] For ease of description, the dimensions and thickness of each component shown in the accompanying drawings are illustrated, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0032] Features of the various embodiments of this disclosure may be partially or completely adhered to or combined with each other, and may be interlocked and operated in various technical ways, and these embodiments may be performed independently or in association with each other.

[0033] Reference will now be made in detail to embodiments of this disclosure, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals may be used throughout the drawings to refer to the same or similar parts.

[0034] In the following, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 This is a schematic block diagram of a display device according to an exemplary embodiment of the present disclosure. For ease of explanation, Figure 1 Only the display panel 110, gate driver 120, data driver 130 and timing controller 140 of the various components of the display device 100 are shown.

[0036] Reference Figure 1 The display device 100 includes: a display panel 110 including a plurality of sub-pixels SP; a gate driver 120 and a data driver 130 supplying various signals to the display panel 110; and a timing controller 140 controlling the gate driver 120 and the data driver 130.

[0037] Gate driver 120 supplies scan signals to multiple scan lines SL according to multiple gate control signals GCS provided from timing controller 140. Although in Figure 1 In the example shown, a gate driver 120 is disposed on one side of the display panel 110 and spaced apart from the display panel 110, but the number and position of gate drivers are not limited thereto.

[0038] In response to a data control signal DCS from a timing controller 140, the data driver 130 converts the image data RGB input from the timing controller 140 into a data voltage Vdata using a gamma voltage. The data driver 130 can receive gamma voltages from the gamma unit, select gamma voltages corresponding to the gray levels of the image data RGB from the gamma voltages to generate the data voltage Vdata, and apply the generated data voltage Vdata to multiple data lines DL.

[0039] Timing controller 140 aligns the RGB image data input from an external source and supplies it to data driver 130. Timing controller 140 can use synchronization signals input from external sources, such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal, to generate a gate control signal GCS and a data control signal DCS. Furthermore, timing controller 140 supplies the generated gate control signal GCS and data control signal DCS to gate driver 120 and data driver 130, respectively, to control gate driver 120 and data driver 130.

[0040] Display panel 110 is an element that displays images to a user and includes multiple subpixels SP. In display panel 110, multiple scan lines SL and multiple data lines DL intersect each other, and subpixels SP are connected to scan lines SL and data lines DL.

[0041] Each of the subpixels SP is the smallest unit forming the screen, and several subpixels SP can be aggregated to form a single pixel. Each of the multiple subpixels SP includes a light-emitting element and pixel circuitry for driving the light-emitting element. Depending on the type of display panel 110, the number of light-emitting elements may vary. For example, if the display panel 110 is an organic light-emitting display panel, the light-emitting elements may be organic light-emitting elements, each of which includes an anode, an organic light-emitting layer, and a cathode. Alternatively, light-emitting diodes (LEDs) or quantum dot light-emitting diodes (QLEDs) including quantum dots (QDs) may be used as light-emitting elements.

[0042] In the following text, reference will be made to Figure 2 The sub-pixels SP of a display device 100 according to an exemplary embodiment of the present disclosure are described in detail.

[0043] Figure 2 This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0044] Reference Figure 2 The sub-pixel SP includes a first pixel transistor PT1, a second pixel transistor PT2, a third pixel transistor PT3, a fourth pixel transistor PT4, a fifth pixel transistor PT5, a sixth pixel transistor PT6, a seventh pixel transistor PT7, a driving transistor DT, and a storage capacitor Cst. The sub-pixel SP is connected to the data line DL, multiple scan lines SL, the transmit control signal line, the first initialization line, the second initialization line, the anode reset line, the high-potential power voltage line, and the low-potential power voltage line.

[0045] In the following description, it is assumed that the subpixel SP is set in the nth row.

[0046] Subpixel SP comprises multiple transistors. These transistors can be implemented as different types of transistors. One of the transistors can be a transistor that uses oxide semiconductor or low-temperature polycrystalline oxide (LTPO) as its active layer. Due to the low turn-off current of oxide semiconductor materials, it is suitable for switching transistors with short on-time and long off-time. For example, in the multiple transistors, the first pixel transistor PT1 and the second pixel transistor PT2 can be transistors that use oxide semiconductor or low-temperature polycrystalline oxide as their active layer.

[0047] Specifically, in order to drive the display device 100 at a low speed, some of the transistors in the sub-pixel SP can be implemented as oxide semiconductor transistors. Since the length of a frame in low-speed driving is longer than the length of a frame in high-speed driving, it is important to maintain a constant voltage at each node of the sub-pixel SP. Oxide semiconductor transistors have very low turn-off current, which is beneficial for maintaining the voltage at each node until the next frame. Therefore, switching transistors such as the first pixel transistor PT1 and the second pixel transistor PT2 can be implemented as oxide semiconductor transistors to easily maintain the voltage at each node of the sub-pixel SP.

[0048] Another of the multiple transistors can be a transistor that uses low-temperature polycrystalline silicon (LTP) as the active layer. Due to the high mobility, low power consumption, and excellent reliability of polycrystalline silicon, it is suitable for driving transistors such as DT.

[0049] Incidentally, multiple transistors can be either n-type or p-type transistors. In an n-type transistor, electrons are the charge carriers, so electrons can flow from the source electrode to the drain electrode, and current can flow from the drain electrode to the source electrode. In a p-type transistor, holes are the charge carriers, so holes can flow from the source electrode to the drain electrode, and current can flow from the source electrode to the drain electrode. One of the multiple transistors can be an n-type transistor, and another of the multiple transistors can be a p-type transistor.

[0050] For example, the first pixel transistor PT1 and the second pixel transistor PT2 can be n-type transistors and transistors using oxide semiconductor as the active layer. The fifth pixel transistor PT5 can be an n-type transistor and a transistor including cryogenic polysilicon as the active layer. Furthermore, the driving transistor DT, the third pixel transistor PT3, the fourth pixel transistor PT4, the sixth pixel transistor PT6, and the seventh pixel transistor PT7 can be p-type transistors and can be transistors including cryogenic polysilicon as the active layer. However, the materials of the active layers forming the multiple transistors and the types of multiple transistors are illustrative only and not limiting.

[0051] The first pixel transistor PT1 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first pixel transistor PT1 is connected to the first scan line SL1(n) of the nth row, and the source electrode and drain electrode are connected between the first node N1 and the third node N3. The first pixel transistor PT1 can connect the first node N1 and the third node N3 based on the first scan signal SCAN1(n) of the first scan line SL1(n) in the nth row.

[0052] The second pixel transistor PT2 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the second pixel transistor PT2 is connected to the second scan line SL2(n) of the nth row, and the source and drain electrodes are connected between the second node N2 and the data line DL. The second pixel transistor PT2 can transmit the data voltage Vdata from the data line DL to the second node N2 based on the second scan signal SCAN2(n) of the second scan line SL2(n) in the nth row.

[0053] The third pixel transistor PT3 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the third pixel transistor PT3 is connected to the emitter control signal line in the nth row, and the source and drain electrodes are connected between the high-potential power line and the second node N2. The third pixel transistor PT3 can transmit the high-potential power voltage VDD to the second node N2 based on the emitter control voltage EM(n) from the emitter control signal line in the nth row.

[0054] The fourth pixel transistor PT4 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fourth pixel transistor PT4 is connected to the emitter control signal line in the nth row, and the source and drain electrodes are connected between the third node N3 and the fourth node N4. The fourth pixel transistor PT4 can transfer drive current from the driving transistor DT to the light-emitting element EL based on the emitter control signal EM(n) from the emitter control signal line in the nth row.

[0055] The fifth pixel transistor PT5 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fifth pixel transistor PT5 is connected to the first scan line SL1(n-2) in the (n-2)th row, and the source and drain electrodes are connected between the first initialization line and the storage capacitor Cst, and between the first initialization line and the first node N1. The fifth pixel transistor PT5 can transmit the first initialization voltage Vini1 of the first initialization line to the storage capacitor Cst and the first node N1 based on the first scan signal SCAN1(n-2) of the first scan line SL1 in the (n-2)th row.

[0056] The sixth pixel transistor PT6 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of PT6 is connected to the third scan line SL3(n) of the nth row, and the source and drain electrodes are connected between the anode reset line and the fourth node N4. PT6 can transmit the anode reset voltage VAR of the anode reset line to the fourth node N4 based on the third scan signal SCAN3(n) of the third scan line SL3(n) in the nth row. Therefore, when PT6 is turned on, the anode of the light-emitting element EL and the fourth node N4 can be initialized to the anode reset voltage VAR.

[0057] The seventh pixel transistor PT7 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the seventh pixel transistor PT7 is connected to the third scan line SL3(n) of the nth row, and the source and drain electrodes are connected between the second node N2 and the second initialization line. The seventh pixel transistor PT7 can transmit the second initialization voltage Vini2 of the second initialization line to the second node N2 based on the third scan signal SCAN3(n) of the third scan line SL3(n) in the nth row. At this time, the second initialization voltage Vini2 can be a conduction bias stress voltage used to apply conduction bias stress.

[0058] By applying conduction bias stress, transistor hysteresis can be mitigated. Transistors may exhibit hysteresis where their characteristics change in the current frame depending on the operating state in the previous frame. For example, even when the same data voltage Vdata is supplied to the driving transistor DT, different levels of drive current may be generated depending on the operating state in the previous frame. Therefore, by applying conduction bias stress to multiple transistors, the transistor characteristics, i.e., threshold voltages, can be initialized to a specific state. For example, the same conduction bias stress can be applied to each of multiple sub-pixels SP, such that certain transistors in each sub-pixel SP can be initialized to the same state. Therefore, all sub-pixels SP can emit light of the same brightness in subsequent frames.

[0059] The driving transistor DT includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the driving transistor DT is connected to the first node N1, and the source and drain electrodes are connected between the second node N2 and the third node N3. When the driving transistor DT is turned on, a driving current is supplied to the light-emitting element EL, enabling the light-emitting element EL to emit light.

[0060] The storage capacitor Cst comprises multiple capacitor electrodes. Some of the capacitor electrodes are connected to a high-potential power line, while the other capacitor electrodes are connected to a first node N1. The storage capacitor Cst stores the voltage between the high-potential power voltage VDD and the voltage at the gate electrode of the driving transistor DT, thereby maintaining the drive current from the driving transistor DT when the light-emitting element EL emits light.

[0061] The light-emitting element EL includes an anode and a cathode. The anode of the light-emitting element EL is connected to the fourth node N4, and its cathode is connected to the low-potential power line from which a low-potential power voltage VSS is applied. The light-emitting element EL can emit light proportionally to the drive current from the driving transistor DT.

[0062] Incidentally, when switching transistors such as the first pixel transistor PT1 and the second pixel transistor PT2 are turned off, the voltage at nearby nodes may be distorted, causing backlash, meaning the brightness cannot reach the target value. For example, when the second pixel transistor PT2, connected between the source electrode of the driving transistor DT and the data line DL, is implemented as a p-type transistor, the data voltage Vdata may decrease due to backlash, making it difficult to output the target brightness. Furthermore, when driving the display device 100 in high-temperature or low-temperature environments, the distortion of the data voltage Vdata due to backlash may become worse, potentially preventing the proper display of low-grayscale images.

[0063] In view of the above, in the display device 100 according to an exemplary embodiment of the present disclosure, the second pixel transistor PT2 connected between the source electrode of the driving transistor DT and the data line DL is implemented as an n-type transistor, so that the data voltage Vdata can increase when a backlash occurs. The data voltage Vdata has a positive value, and brightness fluctuations may worsen when the data voltage Vdata decreases rather than increases. When the second pixel transistor PT2 is changed to an n-type transistor, the data voltage Vdata does not decrease even when a backlash occurs, resulting in greater improvement in brightness fluctuations compared to using a p-type transistor.

[0064] However, when the second pixel transistor PT2 is changed to an n-type transistor, the second scan signal SCAN2 supplied from the second scan line SL2 must be changed from a low level to a high level. In view of the above, in the display device 100 according to an exemplary embodiment of this disclosure, a second gate driver GD2 is added to the gate driver 120, such that a high-level second scan signal SCAN2 can be generated without changing the existing driving timing of the first gate driver GD1 that generates the low-level second scan signal SCAN2.

[0065] In the following text, reference will be made to Figures 3 to 5 Describe gate driver 120.

[0066] Figure 3 This is a block diagram of a gate driver for a display device according to an exemplary embodiment. Figure 4A This is a circuit diagram of the first stage of a display device according to an exemplary embodiment of the present disclosure. Figure 4B This is a circuit diagram of the second stage of a display device according to an exemplary embodiment of the present disclosure.

[0067] Figure 5 This is a timing diagram of the first and second stages of a display device according to an exemplary embodiment of the present disclosure.

[0068] Reference Figure 3 The gate driver 120 includes a first gate driver GD1 and a second gate driver GD2.

[0069] The first gate driver GD1 is a circuit that outputs a low-level second scan signal to control the second pixel transistor in a conventional display device, wherein the second pixel transistor is implemented as a p-type transistor. Previously, a low-level carry signal Carry output from the first gate driver GD1 was output to the second scan line SL2. In contrast, in the display device 100 according to an exemplary embodiment of the present disclosure, the low-level carry signal Carry output from the first gate driver GD1 can be provided to a newly added second gate driver GD2 to generate a high-level second scan signal SCAN2.

[0070] The first gate driver GD1 may include a plurality of first-stage ST1s connected to each other, and may output a carry signal Carry to a plurality of second-stage ST2s of the second gate driver GD2. Each of the plurality of first-stage ST1s may output a carry signal Carry based on the carry signal Carry output from the previous first-stage ST1, a first clock signal CLK1, and a second clock signal CLK2.

[0071] The second gate driver GD2 is a component that outputs a high-level second scan signal SCAN2 to a plurality of second scan lines SL2. The second gate driver GD2 may include a plurality of second stages ST2 connected to each other, and sequentially outputs the second scan signal SCAN2 to the plurality of second scan lines SL2. Each of the plurality of second stages ST2 may output a high-level second scan signal SCAN2 based on the carry signal Carry, the first clock signal CLK1, and the second clock signal CLK2 output from the first stage ST1 of the previous row.

[0072] For example, the first level ST1(n) in the nth row can output the carry signal Carry(n-1) to the second level ST2(n+1) in the (n+1)th row based on the carry signal Carry(n-1) output from the first level ST1(n-1) in the (n-1)th row, the first clock signal CLK1, and the second clock signal CLK2.

[0073] For example, the second stage ST2(n) in the nth row can output a high-level second scan signal SCAN2(n) to the second scan line SL2(n) in the nth row based on the carry signal Carry(n-1), the first clock signal CLK1, and the second clock signal CLK2 output from the first stage ST1(n-1) in the (n-1)th row. In summary, the first stage ST1(n) in the nth row can output the carry signal Carry(n) to each of the first stage ST1(n+1) in the (n+1)th row and the second stage ST2(n+1) in the (n+1)th row.

[0074] Since the first stage ST1 (1) and the second stage ST2 (1) do not have a previous first stage ST1, they receive a separate start signal from the start signal line VST to generate the carry signal Carry (1) and the second scan signal SCAN2 (1).

[0075] The following text will describe the first-level ST1(n) and the second-level ST2(n) in the nth row of the multiple first-level ST1 and multiple second-level ST2.

[0076] Reference Figure 4A The first stage ST1(n) includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first auxiliary transistor Ta1, a first capacitor CQ, and a second capacitor CQB. In the following description, it is assumed that the first transistor T1 to the seventh transistor T7 and the first auxiliary transistor Ta1 are p-type transistors. However, it should be understood that this disclosure is not limited thereto.

[0077] The first transistor T1 includes a gate electrode, a source electrode, and a drain electrode. The gate of the first transistor T1 is connected to the Q node, and the source electrode and the drain electrode are respectively connected between a first clock signal line from which a first clock signal CLK1 is provided and a first output terminal from which a carry signal Carry(n) is output.

[0078] The second transistor T2 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the second transistor T2 is connected to the QB node, and the source electrode and the drain electrode are respectively connected between the gate high line from which the gate high voltage VGH is supplied and the first output terminal from which the carry signal Carry(n) is output.

[0079] The third transistor T3 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the third transistor T3 is connected to the second clock signal line from which the second clock signal CLK2 is provided, and the source electrode and the drain electrode are connected between the first output terminal of the first stage ST1(n-1) in the (n-1)th row, from which the carry signal Carry(n-1) of the previous first stage is output, and the Q2 node.

[0080] The fourth transistor T4 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fourth transistor T4 is connected to a first clock signal line from which a first clock signal CLK1 is provided, and the source and drain electrodes are connected between the fifth transistor T5 and the Q2 node.

[0081] The fifth transistor T5 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fifth transistor T5 is connected to the QB node, and the source and drain electrodes are connected between the gate high line from which the gate high voltage VGH is supplied and the fourth transistor T4.

[0082] The sixth transistor T6 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the sixth transistor T6 is connected to the second clock signal line, and its source and drain electrodes are connected between the second gate low line from which the second gate low voltage VGL2 is provided and the QB node.

[0083] The seventh transistor T7 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the seventh transistor T7 is connected to the Q2 node, and its source and drain electrodes are connected between the second clock signal line and the QB node.

[0084] The first auxiliary transistor Ta1 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first auxiliary transistor Ta1 is connected to a second gate low line, and its source and drain electrodes are connected between node Q2 and node Q. The first auxiliary transistor Ta1 may have a gate electrode connected to the second gate low line and remain always on. The first auxiliary transistor Ta1 may have a source electrode connected to node Q2 and a drain electrode connected to node Q, such that the voltage at node Q2 and node Q can be substantially maintained. At this time, a second gate low voltage VGL2, which is lower than the first gate low voltage VGL1, is input to the gate electrode of the first auxiliary transistor Ta1 to prevent voltage leakage from node Q to node Q2.

[0085] The first capacitor CQ is connected between the Q node and the first output terminal of the carry signal Carry(n) from which it is output. The first capacitor CQ can store the voltage at the Q node.

[0086] The second capacitor CQB is connected between the QB node and the gate high line. The second capacitor CQB can store the voltage at the QB node.

[0087] Reference Figure 4B The second stage ST2 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a second auxiliary transistor Ta2, and a third capacitor CQN. In the following description, it is assumed that the eighth transistor T8 through the thirteenth transistor T13 and the second auxiliary transistor Ta2 are p-type transistors, while the fourteenth transistor T14 is an n-type oxide semiconductor transistor. However, it should be understood that this disclosure is not limited thereto.

[0088] The eighth transistor T8 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the eighth transistor T8 is connected to the QBN node, and the source and drain electrodes are connected between the second clock signal line and the second output terminal from which the second scan signal SCAN2(n) is output.

[0089] The ninth transistor T9 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the ninth transistor T9 is connected to the QN node, and its source and drain electrodes are connected between a first gate low line from which a first gate low voltage VGL1 is provided and a second output terminal from which a second scan signal SCAN2(n) is output.

[0090] The tenth transistor T10 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the tenth transistor T10 is connected to the second clock signal line, and the source electrode and drain electrode are connected between the first output terminal of the first stage ST1(n-1) in the (n-1)th row, which outputs the carry signal Carry(n-1) from the previous first stage, and the QBN node.

[0091] The eleventh transistor T11 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the eleventh transistor T11 is connected to the first clock signal line, and the source and drain electrodes are connected between the gate high line and the QBN node.

[0092] The twelfth transistor T12 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the twelfth transistor T12 is connected to the QBN node, and the source and drain electrodes are connected between the gate high line and the QN2 node.

[0093] The thirteenth transistor T13 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the thirteenth transistor T13 is connected to the first clock signal line, and the source electrode and drain electrode are connected between the second gate low line and the QN2 node.

[0094] The fourteenth transistor T14 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the fourteenth transistor T14 is connected to one end of the third capacitor CQN and the QN node, and the source electrode and drain electrode are connected between the second gate low line and the QBN node.

[0095] The second auxiliary transistor Ta2 includes a gate electrode, a source electrode, and a drain electrode. The gate electrode of the second auxiliary transistor Ta2 is connected to a first gate low line, and the source and drain electrodes are connected between the QN2 node and the QN node. The second auxiliary transistor Ta2 may have a gate electrode connected to the first gate low line and remain always on. The second auxiliary transistor Ta2 may have a source electrode connected to the QN2 node and a drain electrode connected to the QN node, thereby substantially maintaining the voltage at the QN2 node and the QN node. When driving the second stage ST2, the second auxiliary transistor Ta2 can prevent voltage leakage from the QN node towards the QN2 node.

[0096] Incidentally, when the nth row containing the first stage ST1 and the second stage ST2 is the first row, the third transistor T3 of the first stage ST1 and the tenth transistor T10 of the second stage ST2 can be connected to the start signal line VST.

[0097] Reference Figure 4A and Figure 5 At the first time t1, a carry signal Carry(n-1) is output from the first output terminal of the first stage ST1(n-1) in the (n-1)th row, and a low-level second clock signal CLK2 is provided from the second clock signal line.

[0098] In this scenario, in the first stage ST1, the third transistor T3 is turned on by the second clock signal CLK2, allowing the carry signal Carry(n-1) to be transmitted from the previous first stage ST1 to nodes Q2 and Q. Since the first auxiliary transistor Ta1 between nodes Q2 and Q is always on, the carry signal Carry(n-1) transmitted to node Q2 can be transmitted to node Q through the first auxiliary transistor Ta1.

[0099] Then, in the first stage ST1, the sixth transistor T6 is turned on by the second clock signal CLK2, causing the second gate low voltage VGL2 of the second gate low line to be transmitted to the QB node. The second transistor T2 and the fifth transistor T5 are turned on by the second gate low voltage VGL2 at the QB node. Therefore, the high-level first clock signal CLK1 and the gate high voltage VGH can be output to the first output terminal through the turned-on second transistor T2 and the turned-on first transistor T1.

[0100] Subsequently, at the second time t2, when the second clock signal CLK2 is high, the Q node of the first stage ST1 floats. Then, at the third time t3, the low-level first clock signal CLK1 is transmitted from the source electrode to the drain electrode of the first transistor T1, and the voltage at the Q node can be changed by the first capacitor CQ, which acts as a bootstrap capacitor, to a voltage lower than the second clock signal CLK2 and the second gate low voltage VGL2. Therefore, the voltage at the Q node decreases, the first transistor T1 can be stably kept on, and the first clock signal CLK1 can be output to the first output terminal through the first transistor T1. Thus, the low-level first clock signal CLK1 can be output as a carry signal Carry(n) through the first transistor T1, which is kept on by the voltage at the Q node. At this time, a high-level voltage is applied to the QB node to keep the second transistor T2 off, so that the gate high voltage VGH is not transmitted to the first output terminal.

[0101] Reference Figure 4B and Figure 5 At the first time t1, a carry signal Carry(n-1) is provided from the first output terminal of the first stage ST1(n-1) in the (n-1)th row to the second stage ST2(n), and a low-level second clock signal CLK2 is provided from the second clock signal line.

[0102] The tenth transistor T10 of the second stage ST2 can be turned on by the low-level second clock signal CLK2, and the low-level carry signal Carry(n-1) is transmitted to the gate electrode of the twelfth transistor T12 through the turned-on tenth transistor T10. The gate high voltage VGH can be transmitted to the QN2 node and the QN node through the turned-on twelfth transistor T12. The gate high voltage VGH can be stored in the third capacitor CQN, and the ninth transistor T9 can remain off for a predetermined period of time.

[0103] Then, the fourteenth transistor T14 is turned on by the gate high voltage VGH transmitted to the QN node, and the second gate low voltage VGL2 can be transmitted through the turned-on fourteenth transistor T14 to the gate electrode of the eighth transistor T8 and the QBN node. The second gate low voltage VGL2 is provided to the QBN node to which the gate electrode of the eighth transistor T8 is connected, the eighth transistor T8 can be turned on, and the low-level second clock signal CLK2 can be output to the second output terminal through the turned-on eighth transistor T8.

[0104] Subsequently, at the second time t2, the second clock signal CLK2 can be at a high level, and the high-level second clock signal CLK2 can be output to the second output terminal. Therefore, a high-level second scan signal SCAN2(n) can be generated based on the carry signal Carry(n-1) output from the previous first stage ST1(n-1), the first clock signal CLK1, and the second clock signal CLK2.

[0105] Subsequently, at the third time t3, the first clock signal CLK1 can be at a low level, the eleventh transistor T11 can be turned on, and the gate high voltage VGH can be transmitted to the QBN node through the turned-on eleventh transistor T11. Therefore, the QBN node can become a gate high voltage VGH, and the eighth transistor T8 can be turned off.

[0106] Additionally, at the third time t3, the thirteenth transistor T13 is turned on by the first clock signal CLK1, and the second gate low voltage VGL2 can be transmitted to the QN node through the turned-on thirteenth transistor T13. At this time, the voltage at the QN node connected to the third capacitor CQN can become lower than the second gate low voltage VGL2 through bootstrapping. Therefore, the ninth transistor T9 is turned on, and the first gate low voltage VGL1 can be output to the second output terminal.

[0107] In this way, in the display device 100 according to an exemplary embodiment of the present disclosure, a second gate driver GD2 for outputting a high-level second scan signal SCAN2 is added to the first gate driver GD1 that outputs a low-level carry signal Carry, so that the previously used drive timing of the signal can be used as is. First, by changing the second pixel transistor PT2 connected between the data line DL and the drive transistor DT to an n-type transistor, the drop in data voltage Vdata due to backlash can be improved. However, when the second pixel transistor PT2 is changed from a p-type transistor to an n-type transistor, a high-level second scan signal SCAN2 needs to be output to the second scan line SL2 instead of a low-level second scan signal SCAN2. Instead of modifying the existing first gate driver GD1 that outputs a low-level signal to the second scan line SL2 or changing the timing of the drive signal, by adding the new second gate driver GD2, the high-level second scan signal SCAN2 can be generated using the existing drive signal timing. The second gate driver GD2 can receive a low-level carry signal Carry output from the first gate driver GD1 to output a high-level second scan signal SCAN2 to the second scan line SL2. In this case, the reliability of the output of the second scan signal SCAN2 of the second scan line SL2 can be increased by utilizing the first gate driver GD1 and the drive signal timing, which has been verified to be reliable. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the second gate driver GD2 is added to the first gate driver GD1 suitable for the p-type transistor, so that the high-level second scan signal SCAN2 can be easily output to a plurality of second scan lines SL2 without changing the drive signal timing.

[0108] Exemplary embodiments of this disclosure can also be described as follows:

[0109] According to an aspect of this disclosure, a display device is provided. The display device includes: a display panel defining a plurality of sub-pixels connected to a plurality of scan lines and a plurality of data lines; and a gate driver for supplying a high-level scan signal to the plurality of scan lines. The gate driver includes: a first gate driver for outputting a low-level carry signal; a second gate driver for outputting a high-level scan signal based on the carry signal; a first clock signal line connected to the first gate driver and the second gate driver; and a second clock signal line connected to the first gate driver and the second gate driver.

[0110] The first gate driver may include a plurality of cascaded first stages, and the display device may include a start signal line connected to the first of the plurality of first stages, each of the plurality of first stages except the first one being connected to a first output terminal of the preceding first stage of the plurality of first stages.

[0111] The second gate driver may include a plurality of second stages, each second stage including a second output terminal connected to a corresponding scan line among the plurality of scan lines. The first of the plurality of second stages may be connected to a start signal line, and each of the plurality of second stages other than the first second stage may be connected to a first output terminal of the preceding first stage among the plurality of first stages.

[0112] The carry signal output from the first stage in the nth row of multiple first stages can be transmitted to the first stage in the (n+1)th row of multiple first stages and the second stage in the (n+1)th row of multiple second stages.

[0113] Each of the plurality of first stages may include: a first transistor having a gate electrode connected to a Q node, and a source electrode and a drain electrode connected between a first clock signal line and a first output terminal; a second transistor having a gate electrode connected to a QB node, and a drain electrode connected to the first output terminal; a third transistor having a gate electrode connected to a second clock signal line, and a source electrode and a drain electrode connected between the first output terminal of the preceding first stage and a Q2 node; a fourth transistor having a source electrode or a drain electrode connected to a Q2 node; a fifth transistor having a gate electrode connected to a QB node; a sixth transistor having a gate electrode connected to a second clock signal line and a drain electrode connected to a QB node; and a seventh transistor having a gate electrode connected to both the Q2 node and the Q node.

[0114] When a carry signal is output from the previous first stage and a low-level clock signal is provided from the second clock signal line, the third transistor can be turned on to transmit the carry signal to the Q node, and the first transistor can be turned on by the voltage at the Q node to output the clock signal from the first clock signal line to the first output terminal.

[0115] Each of the plurality of second stages may include: an eighth transistor having a gate electrode connected to a QBN node, and a source electrode and a drain electrode connected between a second clock signal line and a second output terminal; a ninth transistor having a gate electrode connected to a QN node, and a drain electrode connected to the second output terminal; a tenth transistor having a gate electrode connected to a second clock signal line, and a source electrode and a drain electrode connected between a first output terminal of the preceding first stage and a QBN node; an eleventh transistor having a source electrode and a drain electrode connected between a QBN node and a gate high line from which a gate high voltage is supplied; a twelfth transistor having a gate electrode connected to a QBN node, and a source electrode and a drain electrode connected between the gate high line and a QN2 node; a thirteenth transistor having a drain electrode connected to a QN2 node; and a fourteenth transistor having a gate electrode connected to a QN node, and a source electrode and a drain electrode connected between a QBN node and a gate low line from which a gate low voltage is supplied.

[0116] When a carry signal is output from the previous first stage and a low-level clock signal is provided from the second clock signal line, the tenth transistor can transmit the carry signal to the QBN node, and the twelfth transistor can be turned on by the carry signal to transmit a high gate voltage to the QN node.

[0117] When a high gate voltage is transmitted to the QN node, the fourteenth transistor can be turned on to transmit a low gate voltage to the QBN node, and the eighth transistor can be turned on by the voltage at the QBN node to output the clock signal from the second clock signal line to the second output terminal.

[0118] Each of the plurality of first stages may further include: a first capacitor connected between the Q node and the first output terminal, and a second capacitor connected to the QB node. Each of the plurality of second stages may include a third capacitor connected between the QN node and the second output terminal. When a carry signal is output, the first transistor may remain on through the first capacitor, and when a scan signal is output, the ninth transistor may remain off through the third capacitor.

[0119] Each of the plurality of sub-pixels may include: a driving transistor having a gate electrode connected to a first node, a source electrode connected to a second node, and a drain electrode connected to a third node; a first pixel transistor having a source electrode and a drain electrode connected between the first node and the third node; and a second pixel transistor having a gate electrode connected to a plurality of scan lines, and a source electrode and a drain electrode connected between the second node and a plurality of data lines. The second pixel transistor may be an n-type oxide semiconductor transistor that is turned on by a high-level scan signal supplied from the plurality of scan lines.

[0120] Although exemplary embodiments of this disclosure have been described in detail with reference to the accompanying drawings, this disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of this disclosure. Therefore, the exemplary embodiments of this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of this disclosure. The scope of the technical concept of this disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit this disclosure. The scope of protection of this disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of this disclosure.

Claims

1. A display device, comprising: A display panel having a plurality of sub-pixels connected to a plurality of scan lines and a plurality of data lines; as well as A gate driver for supplying a high-level scan signal to the plurality of scan lines. The gate driver includes: A first gate driver for outputting a low-level carry signal, the first gate driver comprising a plurality of cascaded first stages; A second gate driver for outputting a high-level scan signal based on the carry signal, the second gate driver comprising a plurality of second stages, each second stage comprising a second output terminal connected to a corresponding scan line among the plurality of scan lines; A first clock signal line connected to the first gate driver and the second gate driver; and A second clock signal line connected to the first gate driver and the second gate driver; The display device includes a start signal line connected to the first first stage of the plurality of first stages and the first second stage of the plurality of second stages. Each of the plurality of first stages, except for the first first stage, is connected to the first output terminal of the preceding first stage of the plurality of first stages. Each of the plurality of second stages, except for the first second stage, is connected to the first output terminal of the preceding first stage of the plurality of first stages. Each of the plurality of first levels includes: The first transistor has a gate electrode connected to the Q node, and a source electrode and a drain electrode connected between the first clock signal line and the first output terminal; The second transistor has a gate electrode connected to the QB node and a drain electrode connected to the first output terminal. The third transistor has a gate electrode connected to the second clock signal line, and a source electrode and a drain electrode connected between the first output terminal of the previous first stage and the Q2 node; A fourth transistor having a source electrode or a drain electrode connected to the Q2 node; The fifth transistor has a gate electrode connected to the QB node; A sixth transistor having a gate electrode connected to the second clock signal line and a drain electrode connected to the QB node; and The seventh transistor has a gate electrode connected to the Q2 node and the Q node.

2. The display device according to claim 1, wherein The carry signal output from the first stage in the nth row of the plurality of first stages is transmitted to the first stage in the (n+1)th row of the plurality of first stages and the second stage in the (n+1)th row of the plurality of second stages.

3. The display device according to claim 1, wherein When a carry signal is output from the previous first stage and a low-level clock signal is provided from the second clock signal line, the third transistor is turned on to transmit the carry signal to the Q node, and the first transistor is turned on by the voltage at the Q node to output the clock signal from the first clock signal line to the first output terminal.

4. The display device according to claim 1, wherein Each of the plurality of second levels includes: The eighth transistor has a gate electrode connected to the QBN node, and a source electrode and a drain electrode connected between the second clock signal line and the second output terminal; The ninth transistor has a gate electrode connected to the QN node and a drain electrode connected to the second output terminal; The tenth transistor has a gate electrode connected to the second clock signal line, and a source electrode and a drain electrode connected between the first output terminal of the previous first stage and the QBN node; The eleventh transistor has a source electrode and a drain electrode connected between the QBN node and a gate high line from which a gate high voltage is supplied; The twelfth transistor has a gate electrode connected to the QBN node, and a source electrode and a drain electrode connected between the gate high line and the QN2 node; The thirteenth transistor has a drain electrode connected to the QN2 node; and The fourteenth transistor has a gate electrode connected to the QN node, and a source electrode and a drain electrode connected between the QBN node and a gate low line from which a gate low voltage is supplied.

5. The display device of claim 4, wherein, When a carry signal is output from the previous first stage and a low-level clock signal is provided from the second clock signal line, the tenth transistor transmits the carry signal to the QBN node, and the twelfth transistor is turned on by the carry signal to transmit the gate high voltage to the QN node.

6. The display device according to claim 5, wherein, When the gate high voltage is transmitted to the QN node, the fourteenth transistor is turned on to transmit the gate low voltage to the QBN node, and the eighth transistor is turned on by the voltage at the QBN node to output the clock signal from the second clock signal line to the second output terminal.

7. The display device according to claim 4, wherein, Each of the plurality of first levels further includes: The first capacitor connected between the Q node and the first output terminal; and The second capacitor connected to the QB node, Each of the plurality of second levels includes: A third capacitor connected between the QN node and the second output terminal. Specifically, when the carry signal is output, the first transistor remains turned on by the first capacitor, and When the scanning signal is output, the ninth transistor remains off by the third capacitor.

8. The display device according to claim 1, wherein, Each of the plurality of sub-pixels includes: A driving transistor having a gate electrode connected to a first node, a source electrode connected to a second node, and a drain electrode connected to a third node. A first pixel transistor has a source electrode and a drain electrode connected between the first node and the third node; and The second pixel transistor has a gate electrode connected to the plurality of scan lines, and a source electrode and a drain electrode connected between the second node and the plurality of data lines. The second pixel transistor is an n-type oxide semiconductor transistor that is turned on by a high-level scan signal supplied from the plurality of scan lines.

9. A gate driver for controlling the driving timing of an n-type transistor using a control p-type transistor, comprising: A first gate driver for outputting a low-level carry signal, the first gate driver comprising a plurality of cascaded first stages; A second gate driver for outputting a high-level scan signal based on the carry signal, the second gate driver comprising a plurality of second stages, each second stage comprising a second output terminal; A first clock signal line connected to the first gate driver and the second gate driver; as well as A second clock signal line connected to the first gate driver and the second gate driver; Wherein, the first first stage of the plurality of first stages and the first second stage of the plurality of second stages are connected to the start signal line, each first stage of the plurality of first stages except the first first stage is connected to the first output terminal of the preceding first stage of the plurality of first stages, and each second stage of the plurality of second stages except the first second stage is connected to the first output terminal of the preceding first stage of the plurality of first stages; Each of the plurality of first levels includes: The first transistor has a gate electrode connected to the Q node, and a source electrode and a drain electrode connected between the first clock signal line and the first output terminal; The second transistor has a gate electrode connected to the QB node and a drain electrode connected to the first output terminal. The third transistor has a gate electrode connected to the second clock signal line, and a source electrode and a drain electrode connected between the first output terminal of the previous first stage and the Q2 node; A fourth transistor having a source electrode or a drain electrode connected to the Q2 node; The fifth transistor has a gate electrode connected to the QB node; A sixth transistor having a gate electrode connected to the second clock signal line and a drain electrode connected to the QB node; and The seventh transistor has a gate electrode connected to the Q2 node and the Q node.

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