Display devices

Abstract

A display device is disclosed. The display device includes a plurality of pixel circuit rows, a plurality of select lines connected to the pixel circuit rows, and a shift register including linked shift register units. The shift register units output sequential select pulses to the plurality of select lines. Each shift register unit outputs a select pulse to a corresponding select line among the plurality of select lines. Each shift register unit includes a first conductivity type thin-film transistor connected in parallel to a fixed potential wiring for applying a non-selection level select pulse during an on-state, connecting the corresponding select line to the wiring. During each frame period, the plurality of thin-film transistors are turned on / off by clock signals of different phases. During each frame period, the duty cycle of the on-state of each thin-film transistor is 12.5% ​​or less.

Description

Technical Field

[0001] This disclosure relates to a display device. Background Technology

[0002] LCD (Liquid Crystal Display) devices and OLED (Organic Light Emitting Diode) display devices are widely used as display devices. These display devices include shift registers used to drive (select) scan lines to select the pixel rows to which data signals are to be written.

[0003] Furthermore, OLED display devices that measure the characteristics of components in a display device (driving transistor, OLED) and correct data signals based on the measurement results are also known. Such OLED display devices that perform external compensation on data signals include a shift register that outputs a control signal for measurement to a measurement control line.

[0004] With the expansion of applications using display devices, the demand for non-rectangular display devices has increased due to aesthetic considerations. To realize non-rectangular display devices, driver circuitry including such shift registers needs to be formed through thin-film processes performed on an insulating substrate. Furthermore, display devices are used in various environments, making reliability an increasingly important requirement. Summary of the Invention

[0005] The driver circuitry of the display device sequentially selects selection lines, such as scan lines or light-emitting control lines. The driver circuitry connects the selection line to a wiring that applies either a low or high potential during the selection cycle, and to a wiring that applies the other low or high potential during the non-selection cycle. The driver circuitry connects the selection line to the potential supply wiring via a turn-on / turn-off thin-film transistor (TFT), which in turn connects the selection line to the wiring that applies a high or low potential.

[0006] If a TFT remains in the on state for an extended period, its characteristics will fluctuate due to bias stress, leading to a decrease in driving performance. If low or high potentials are applied to the select line, the driving performance of the TFT will degrade, resulting in a decrease in the display quality of the display device.

[0007] One aspect of this disclosure is a display device comprising: a plurality of pixel circuit rows; a plurality of select lines connected to the plurality of pixel circuit rows; and a shift register including a plurality of linked shift register units. The plurality of shift register units output sequential select pulses to the plurality of select lines. Each of the plurality of shift register units outputs a select pulse to a corresponding select line among the plurality of select lines. Each shift register unit includes a plurality of thin-film transistors of a first conductivity type connected in parallel, and during an on-state, it connects the corresponding select line to a fixed-potential wiring to apply a non-select level to the select pulse. During each frame period, the plurality of thin-film transistors are turned on / off by a clock signal of different phases. During each frame period, the duty cycle of the on-cycle of each of the plurality of thin-film transistors is 12.5% ​​or less.

[0008] According to one aspect of this disclosure, characteristic fluctuations of the TFTs in a display device selectively connected to a power supply line can be mitigated.

[0009] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are not intended to limit this disclosure. Attached Figure Description

[0010] Figure 1 An example configuration of a liquid crystal display device is illustrated schematically;

[0011] Figure 2 The cross-sectional structure of a liquid crystal display device is schematically shown.

[0012] Figure 3A and Figure 3B A corresponding example of the pixel circuitry in a liquid crystal display device is shown;

[0013] Figure 4 The circuit configuration of a single-stage shift register is schematically shown.

[0014] Figure 5 It is a timing diagram showing the changes of the input signal, the potential of node N1, the potential of node N2, and the output signal OUT of the shift register unit over time;

[0015] Figure 6A This shows a portion of a shift register that can be installed in a scan driver;

[0016] Figure 6B This shows another part of the shift register that can be installed in the scan driver;

[0017] Figure 7A It shows having Figure 6A and 6B The timing diagram of the signals in the shift register configured as shown;

[0018] Figure 7B It shows having Figure 6A and 6B Another timing diagram of the signals in the shift register configured as shown;

[0019] Figure 8 The diagram illustrates the relationship between the number of clock signals and the duty cycle.

[0020] Figure 9 The measurement results show the relationship between the duty cycle of the gate signal and the characteristic fluctuations of the amorphous silicon N-type TFT.

[0021] Figure 10 An example configuration of shift register units on both sides that output signals to a scan line is shown;

[0022] Figure 11A This shows a portion of a shift register that can be installed in a scan driver;

[0023] Figure 11B This shows another part of the shift register that can be installed in the scan driver;

[0024] Figure 12A This shows a portion of a shift register that can be installed in a scan driver;

[0025] Figure 12B This shows another part of the shift register that can be installed in the scan driver;

[0026] Figure 13 An example configuration of a shift register unit according to one embodiment of this specification is shown;

[0027] Figure 14A This shows a portion of a shift register that can be installed in a scan driver; and

[0028] Figure 14B Another part of the shift register that can be installed in the scan driver is shown. Detailed Implementation

[0029] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. It should be noted that the embodiments are merely examples of implementing the present disclosure and do not limit the technical scope of the present disclosure. Common elements in the drawings are indicated by the same reference numerals.

[0030] <Overview>

[0031] The following describes a circuit configuration that can be used in scanning circuits of LCD (Liquid Crystal Display) devices, OLED (Organic Light Emitting Diode) display devices, etc. A scanning circuit according to one embodiment of this specification includes a shift register that can output scanning signals for the LCD or OLED display device, light emission control signals for the OLED display device, etc. The shift register includes multiple connected shift register units.

[0032] A shift register sequentially selects a select line, such as a scan line or an illumination control line. The shift register is connected to a wiring that applies either a low or high potential during selection and to a wiring that applies the other low or high potential during non-selection. The driver circuit connects the select line to the potential supply wiring via an on / off TFT, which in turn connects the select line to the wiring that applies a high or low potential.

[0033] If a TFT remains in the on state for an extended period, its characteristics will fluctuate due to bias stress, leading to a decrease in driving performance. Applying low or high potentials to the select line will also degrade the driving performance of the TFT, resulting in a decrease in the display quality of the display device.

[0034] According to one embodiment of this specification, the scanning circuit of a display device includes a shift register that outputs sequential selection pulses to selection lines. Each shift register unit includes a plurality of thin-film transistors of a first conductivity type connected in parallel, which output selection pulses to the corresponding selection line and connect the corresponding selection line to a non-selection level wiring to which the selection pulse is applied during the on-state. During each frame period, the plurality of thin-film transistors are turned on / off by clock signals of different phases. As a result, the duty cycle of the on-cycle of the thin-film transistors can be reduced.

[0035] The embodiments will now be described in detail with reference to the accompanying drawings. In the various drawings, the same reference numerals are assigned to common parts. To increase clarity of description, the size, shape, etc., of the depicted objects may sometimes be exaggerated.

[0036] <Example 1>

[0037] [Overall Configuration]

[0038] Figure 1An example configuration of a liquid crystal display device 10 is schematically illustrated. The features of this disclosure can also be applied to other display devices, such as OLED display devices. The liquid crystal display device 10 includes a liquid crystal display panel and a control device. The liquid crystal display panel includes a TFT (thin-film transistor) substrate 100, a counter substrate 200, and a sealing unit 150. Electrodes for applying an electric field to the TFTs and the liquid crystal are formed on the TFT substrate 100. The sealing unit 150 bonds the TFT substrate 100 to the counter substrate 200. Liquid crystal material is sealed between the TFT substrate 100 and the counter substrate 200.

[0039] Scan drivers 131 and 132 and driver IC 134 are disposed outside the display area 125 of the TFT substrate 100. Driver IC 134 is connected to an external device via FPC (flexible printed circuit) 135. Scan drivers 131 and 132 and driver IC 134 are included in a control device and are also referred to as driver circuitry.

[0040] Scan drives 131 and 132 are positioned opposite each other across display area 125. Figure 1 In the example, scan drivers 131 and 132 are positioned on the left and right sides of the display area 125, respectively. Scan drivers 131 and 132 drive different scan lines of the TFT substrate 100 or drive scan lines simultaneously. Any of these steps can be omitted.

[0041] For example, an anisotropic conductive film (ACF) is used to mount the driver IC 134. The driver IC 134 applies power and timing signals (control signals) to the scan drivers 131 and 132, and also applies signals corresponding to the image data to the data lines.

[0042] Figure 2 The cross-sectional structure of the liquid crystal display device 10 is shown schematically. Figure 2 Partial configuration of the liquid crystal display device 10 is shown, and some configurations including a backlight unit are omitted from the description. The liquid crystal display panel includes a TFT substrate 100 and a counter substrate 200 opposite to the TFT substrate 100. A liquid crystal layer 111 is sandwiched between the TFT substrate 110 and the counter substrate 200. The liquid crystal display device 10 further includes a backlight unit (not shown).

[0043] The TFT substrate 100 includes an insulating substrate 102. The insulating substrate 102 is an insulating transparent substrate made of glass or resin. The insulating substrate 102 is, for example, rectangular, and one of its main surfaces faces a main surface of the opposing substrate 200. A polarizer 101 is attached to the main surface of the insulating substrate 102 on the side opposite to the liquid crystal layer 111.

[0044] On the main surface of the insulating substrate 102 facing the liquid crystal layer 111, driving electrodes 103 (also referred to as pixel electrodes) and common electrodes 104 (also referred to as opposing electrodes) for applying an electric field to the liquid crystal layer 111 are arranged. Each pair of driving electrodes 103 and common electrodes 104 applies an electric field to the liquid crystal of one pixel. The amount of transmitted light at the pixel changes according to the applied electric field. A TFT array (not shown) for selecting the pixel to be controlled is formed on the insulating substrate 102.

[0045] Figure 2 The configuration example shown is a lateral electric field liquid crystal display device. Examples of lateral electric field liquid crystal display devices include IPS (in-plane switching) or FFS (edge-field switching) liquid crystal display devices. Figure 2 In the figure, the driving electrode and the common electrode of only one of the multiple pixels are marked with reference numerals 103 and 104, respectively.

[0046] The alignment film 105 is stacked in layers to cover the electrode layer including the driving electrode 103 and the common electrode 104. The alignment film 105 is in contact with the liquid crystal layer 111 and defines the alignment state of the liquid crystal molecules when no electric field is applied.

[0047] exist Figure 2 In the configuration example, the opposing substrate 200 is a CF substrate including a color filter (CF). The opposing substrate 200 may alternatively exclude a color filter. The opposing substrate 200 is an insulating substrate 141 made of glass or resin. For example, the insulating substrate 141 is rectangular. A polarizing plate 142 is attached to the main surface of the insulating substrate 141 on the side opposite to the liquid crystal layer 111.

[0048] A black matrix 124 defining a grid pattern of pixels is deposited in layers on the main surface of the insulating substrate 141 facing the liquid crystal layer 111. For example, the black matrix 124 is a black resin or metal film made of a chromium-type material. A red, green, or blue color filter 123 is formed in each pixel area surrounded by the black matrix 124.

[0049] An insulating protective layer 122 is deposited in layers on the color filter 123. The protective layer 122 can be omitted. An alignment film 121 is deposited in layers on the protective layer 122. The alignment film 121 is in contact with the liquid crystal layer 111 and defines the alignment state of the liquid crystal molecules when no electric field is applied.

[0050] A backlight unit (not shown) is disposed on the rear surface (rear side) of the liquid crystal display panel. Either the TFT substrate 100 or the opposing substrate 200 is on the front side where the user is viewing the image, and the other is on the rear side. That is, the backlight unit is disposed on... Figure 2 On the TFT substrate 100 side or the opposite substrate 200 side of the liquid crystal display panel shown.

[0051] The liquid crystal layer 111 controls the amount of light transmitted from the backlight unit at each pixel based on the electric field between each driving electrode 103 and the common electrode 104. The driver IC 134 controls the potential of the driving electrode 103 and the common electrode 104 of each pixel. The driver IC 134 controls the potential of the driving electrode 103 and the common electrode 104 of each pixel based on image data to control the amount of light transmitted at the pixel.

[0052] [Pixel Circuit Configuration]

[0053] Next, an example of the pixel circuitry of a liquid crystal display device will be described. Figure 3A and Figure 3B A corresponding example of the pixel circuitry of a liquid crystal display device is shown. Figure 3A An example pixel circuit includes an N-type switching TFT 202, a storage capacitor CST, and a liquid crystal LC between a common electrode and a pixel electrode. A common potential Vcom is applied to the common electrode. For example, the N-type switching TFT 202 can be an amorphous silicon TFT, an oxide semiconductor TFT, or a low-temperature polycrystalline silicon TFT.

[0054] Scan drivers 131 and / or 132 output a selection pulse to scan line 206, switching the N-type switching thin-film transistor 202 to the ON state. The selection level (pulse level) of the selection pulse is high, and the non-selection level (reference level) is low.

[0055] Scan line 206 is connected to one or both of scan drivers 131 and 132. Data line 205 applies a data signal to the pixel electrode and storage capacitor CST via an N-type switch TFT 202 that is in the ON state. The data signal is applied to data line 205 from driver IC 134.

[0056] Figure 3B An example pixel circuit includes a P-type switching TFT 212, a storage capacitor CST, and a liquid crystal LC between a common electrode and a pixel electrode. A common potential Vcom is applied to the common electrode. For example, the P-type switching TFT 212 may be a low-temperature polycrystalline silicon TFT.

[0057] Scan drivers 131 and / or 132 output a selection pulse to scan line 206, switching the P-type switch TFT 212 to the ON state. The selection level (pulse level) of the selection pulse is low, while the non-selection level (reference level) is high.

[0058] Scan line 206 is connected to one or both of scan drivers 131 and 132, and data line 205 applies a data signal to the pixel electrode and storage capacitor CST via a P-type switch TFT 212 that is in the ON state. The data signal is applied to data line 205 from driver IC 134.

[0059] [Scan driver circuit]

[0060] The control will be described below, including Figure 3A The diagram shows an example of the scan driver circuit configuration for the pixel circuit of an N-type switching TFT. The scan line follows... Figure 1 The scan lines extend along the X-axis and are arranged along the Y-axis. The scan driver sequentially outputs gate signals (selection signals) to the scan lines arranged along the Y-axis.

[0061] Figure 4 The circuit configuration of a single-stage shift register 310 (also referred to as a flip-flop or shift register unit) is schematically shown. Scan drivers 131 and 132 each include a shift register, which comprises multiple shift register units 310 linked in a multi-stage manner. The shift register units of scan drivers 131 and 132 may have… Figure 4 The configuration shown.

[0062] Figure 4 The output signal OUT of the shift register unit 310 shown is Figure 3A The gate signal of the N-type TFT 202 in the pixel circuit is shown. A high-level output signal pulse is applied to the gate of the N-type TFT 202 by the shift register unit. As a result, the N-type TFT 202 is turned on. In the circuit described below, the N-type TFT 202 of the pixel circuit and the N-type TFT of the shift register unit can be amorphous silicon TFTs. Furthermore, the transistors of the shift register unit are switching TFTs that are turned on or off.

[0063] The signals input to shift register unit 310 include signals IN1, IN2, DIR1, DIR2, and CLK1 to CLK8. Signals DIR1 and DIR2 are control signals used to select the scan direction (shift direction) of the shift register. CLK1 to CLK8 are clock signals. Signal IN1 is an input signal from one previous stage shift register unit, and signal IN2 is an input signal from another previous stage shift register unit. Only one input signal generates a pulse according to the scan direction of the shift register, while the other input signal is held at VGL. The input signal of the first shift register unit in the shift register is the start signal.

[0064] In addition, a constant low power supply potential VGL is applied to shift register unit 310. The signals IN1, IN2, DIR1, DIR2 and CLK1 to CLK8 input to the shift register unit vary between a constant high power supply potential VGH (high level) and a low power supply potential VGL (low level).

[0065] The shift register unit 310 applies the output signal OUT from the output line OT to the scan line 206. The shift register unit 310 includes 13 transistors T0 to T12 and two capacitors C1 and C2.

[0066] Either the source or drain of transistor T0 is provided with a control signal DIR1 to control the scan direction of the shift register, and the other is connected to node N1. The gate of transistor T0 is provided with an input signal IN1. Either the source or drain of transistor T1 is provided with a control signal DIR2 to control the scan direction of the shift register, and the other is connected to node N1. The gate of transistor T1 is provided with an input signal IN2.

[0067] Either the source or drain of transistor T2 is supplied with a low power supply potential VGL, and the other is connected to node N1. The gate of transistor T2 is connected to node N2. The gate of transistor T2 is supplied with a clock signal CLK1 via capacitor C2, or with a low power supply potential VGL via transistor T3. Transistor T2 is a pull-down TFT that lowers the potential of node N1 to the low power supply potential VGL. Transistor T2 is an example of a third thin-film transistor.

[0068] Either the source or drain of transistor T3 is provided with a low power supply potential VGL, and the other is connected to node N2. The gate of transistor T3 is connected to node N1. The gate of transistor T3 is provided with a control signal DIR1 or DIR2 via transistor T0 or T1, or with a low power supply potential VGL via transistor T2.

[0069] Either the source or drain of transistor T4 is supplied with a clock signal CLK1, and the other is connected to the output line OT. The gate of transistor T4 is connected to node N1. The potential of the gate of transistor T4 is the same as the potential of the gate of transistor T3. Transistor T4 is an example of a second thin-film transistor that provides a select level (high level) for a select pulse during the on-state.

[0070] Transistors T5 through T12 are pull-down N-type TFTs that lower the potential of the output line OT to a low supply potential VGL. Transistors T5 through T12 are connected in parallel between the output line OT and the power supply line providing the low supply potential VGL. Specifically, either the source or drain of each of transistors T5 through T12 is connected to the output line OT, and the other is connected to the wiring providing the low supply potential VGL.

[0071] The gate of transistor T5 is connected to node N2. The gate potential of transistor T5 is the same as that of transistor T2. The gates of transistors T6 through T12 are supplied with clock signals CLK2 through CLK8, respectively. As described later, transistors T6 through T12 and T5 are sequentially turned on, and a low supply potential VGL is provided to the output line OT. Figure 4 In the configuration example, all transistors performing pull-down on the output line are controlled by clock signals of different phases. For example, transistors T5 through T12 have the same channel width and the same pull-down performance. Transistors T5 through T12 can have the same structure.

[0072] Capacitor C1 has its first terminal connected to node N1 and its second terminal connected to output line OT. Capacitor C2 has its first terminal connected to node N2 and its second terminal supplied with clock signal CLK1. Capacitor C1 is a bootstrap capacitor that applies a bootstrap effect to the potential of node N1. Capacitor C2 can appropriately apply clock signal CLK1 and low supply potential VGL to node N2.

[0073] Figure 5 This is a timing diagram showing the changes in the input signal, the potential of node N1, the potential of node N2, and the output signal OUT of shift register unit 310 over time. Time TM1 is the start time of control of shift register unit 310 corresponding to one frame (image frame) of image data.

[0074] exist Figure 5 In the example, control signal DIR1 is always high (VGH), and control signal DIR2 is always low (VGL). This indicates that the scan direction of the shift register remains in the direction indicated by control signal DIR1.

[0075] At time TM1, the input signal IN1 switches from VGL to VGH. Other signals are at VGL. Since the input signal IN1 reaches VGH, transistor T0 turns on. Control signal DIR1 is applied to node N1. Control signal DIR1 is at VGH, and the potential of node N1 rises from VGL to V1. The potential V1 of node N1 is essentially VGH, and more precisely, VGH - Vt, where the threshold voltage of transistor T0 is Vt.

[0076] As the potential of node N1 rises, transistor T3 turns on. Node N2 and the low power supply line are connected to each other via transistor T3. The potential of node N2 is VGL. Furthermore, as the potential of node N1 rises, transistor T4 turns on. The clock signal CLK1 is at VGL, and the output signal OUT is also at VGL.

[0077] Next, at time TM2, the input signal IN1 reaches VGL, and transistor T0 enters the off state. Furthermore, the clock signal CLK1 switches from VGL to VGH. Transistor T4 is turned on, and the output signal OUT rises to a high level. The potential of the output signal OUT is essentially VGH, more precisely VGH-Vt, where the threshold voltage of transistor T0 is Vt.

[0078] At this point, node N1 is in a floating state. Therefore, due to the bootstrap effect, the potential of node N1 rises from V1 to V2 via capacitor C1. Potential V2 is 2VGH - VGL - Vt, and is the maximum potential of node N1. Due to the rise in the potential of node N1, transistor T4 remains in the on state.

[0079] Next, at time TM3, clock signal CLK1 switches to VGL. As a result, the potential of node N1 reaches VGL, and transistors T3 and T4 enter the off state. Node N2 is in a floating state, and its potential remains at VGL. Therefore, transistor T5 is in the off state.

[0080] Furthermore, clock signal CLK2 switches to VGH. As a result, transistor T6 turns on. Output line OT and the low power supply line are connected to each other via transistor T6, and output signal OUT switches to low (VGL). Input signal IN2 switches to VGH according to the output of the shift register unit in the next stage, but signal DIR2 remains at VGL, and the potential of node N1 does not change.

[0081] Clock signals CLK2 to CLK8 generate high-level pulses (turn-on pulses) sequentially from time TM3 to TM4 in the aforementioned order. As a result, transistors T6 to T12 sequentially enter the turn-on state. Figure 5 In the example, the rise and fall of consecutive on-pulses occur simultaneously. There may be some time between the fall of the preceding on-pulse and the rise of the subsequent on-pulse. Alternatively, a configuration may be adopted in which a portion of the consecutive on-pulses overlaps, or in other words, the fall of the preceding on-pulse occurs after the rise of the subsequent on-pulse.

[0082] At time TM4, clock signal CLK1 switches to VGH, and therefore, the potential of node N2 rises to V3 via capacitor C2. Potential V3 is VGH-α, where a coefficient α is used to account for the gate capacitances of transistors T2 and T5 and the drain capacitance of transistor T3. Transistors T2 and T5 switch to the on state, and the output signal OUT remains at VGL. Transistor T2 turns on / off in a manner similar to that of transistor T5.

[0083] After time TM4, the turn-on pulses are generated repeatedly in the order of clock signals CLK1 to CLK8. As a result, transistors T5 to T12 cyclically and sequentially enter the turn-on state. Figure 5 In the example shown, clock signals CLK1 to CLK8 periodically generate turn-on pulses. All clock signals CLK1 to CLK8 are synchronized, and... Figure 5 In the example, the clock frequency and clock width (conduction pulse width) are the same. Furthermore, the phases of all clock signals CLK1 to CLK8 are different from each other. The clock period of clock signals CLK1 to CLK8 is eight times the pulse width.

[0084] exist Figure 5 In the example shown, consecutive clock signals arrive at VGH or VGL simultaneously. One configuration can be adopted where, starting at time TM3, any of transistors T5 through T12 is on until the input signal IN1 rises to write data during the next frame period (until time TM1 of the next frame period), and the output line OT is always connected to the low power supply line. From the time the last pull-down TFT switches from on to off until time TM1 of the next frame period, the output line can be floating.

[0085] Figure 6A A portion of a shift register that can be installed in scan driver 131 or 132 is shown. Specifically, Figure 6A The highest-level shift register unit 311 and the lower-level shift register units 312 (next or previous stage) preceding it are shown. Shift register units 311 and 312 may each have a reference. Figure 4 and Figure 5 The circuit configuration and operation are described. In this example, the shift register consists of 8N linked shift register cells (N is a positive integer).

[0086] Each shift register unit includes multiple signal terminals. One signal terminal is the output signal terminal for the output signal OUT. The other signal terminals are for signals IN1, IN2, DIR1, DIR2, and CLK1 to CLK8, as well as the reference. Figure 4 and Figure 5 The input signal terminal is described as having a low power supply potential VGL.

[0087] The input signal terminals include externally input signals and a low power supply potential VGL. Specifically, control signals DIR1 and DIR2 are input to their respective signal terminals. The start signal ST1 is input to the signal terminal IN1 for the highest-level shift register unit 311. The output signal OUT1 of the previous-level shift register unit 311 is input to the signal terminal IN1 for the next-level shift register unit 312.

[0088] The output signal OUT from the next (previous) stage shift register unit (not shown) is input to the signal terminal IN2 of shift register unit 312. The output signal OUT2 of the next (previous) stage shift register unit 312 is input to the signal terminal IN2 of shift register unit 311.

[0089] Clock signals CA to CH have been input to the signal terminals for clock signals CLK1 to CLK8. In shift register unit 311, clock signals CA to CH are respectively input to the signal terminals for clock signals CLK1 to CLK8. In shift register unit 312, clock signals CB to CH and CA have been input to the signal terminals for clock signals CLK1 to CLK8.

[0090] Figure 6B Another portion of the shift register, which can be installed in scan driver 131 or 132, is shown. Specifically, Figure 6B The diagram shows the lowest-level shift register unit 316 and the preceding shift register 315 (the next or previous level). Shift register units 315 and 316 are the 8N-1 and 8Nth shift register units from the highest level, respectively. Shift register units 315 and 316 may each have a reference... Figure 4 and Figure 5 The circuit configuration and operation are described.

[0091] This section will primarily describe the differences from shift register units 311 and 312. The output signal OUT of the previous stage shift register unit (not shown) is input to the signal terminal IN1 of shift register unit 315. The output signal OUT8N-1 of the previous stage shift register unit 315 is input to the signal terminal IN1 of shift register unit 316.

[0092] The start signal ST2 is input to the signal terminal IN2 of shift register unit 316. The output signal OUT8N of the next (previous) stage shift register unit 316 is input to the signal terminal IN2 of shift register unit 315.

[0093] In shift register unit 315, clock signals CG, CH, and CA to CF have been input to the signal terminals for clock signals CLK1 to CLK8. In shift register unit 316, clock signals CH and CA to CG are respectively input to the signal terminals for clock signals CLK1 to CLK8.

[0094] The shift register units are divided into eight groups, and the same clock signal is input to the clock signal terminal of the shift register unit in the same group. The clock signals input to the clock signal terminal are different between different groups. Specifically, in the 8k-7th shift register units from the highest level, clock signals CA to CH are input to the signal terminals for clock signals CLK1 to CLK8, respectively. k is an integer of 1 or greater.

[0095] In shift register unit 8k-6, clock signals CB to CH and CA have been input to the signal terminals for clock signals CLK1 to CLK8. In shift register unit 8k-5, clock signals CC to CH, CA, and CB have been input to the signal terminals for clock signals CLK1 to CLK8. In shift register unit 8k-4, clock signals CD to CH and CA to CC have been input to the signal terminals for clock signals CLK1 to CLK8.

[0096] In shift register unit 8k-3, clock signals CE to CH and CA to CD have been input to the signal terminals for clock signals CLK1 to CLK8. In shift register unit 8k-2, clock signals CF to CH and CA to CE have been input to the signal terminals for clock signals CLK1 to CLK8. In shift register unit 8k-1, clock signals CG, CH, and CA to CF have been input to the signal terminals for clock signals CLK1 to CLK8. In shift register unit 8k, clock signals CH and CA to CG have been input to the signal terminals for clock signals CLK1 to CLK8.

[0097] Figure 7A It shows having Figure 6A and 6B The timing diagram of the signals in the shift register configured as shown. Figure 7A In the control shown, the scanning direction is from the highest-level shift register unit 311 to the lowest-level shift register unit 316. Time TM10 is the start time of each frame period. During each frame period, control signal DIR1 is at a high level (VGH), and control signal DIR2 is at a low level (VGL). At time TM10, a pulse of start signal ST1 is generated. Then, start signal ST1 remains at a low level (VGL) until the next frame period.

[0098] As the pulse of the start signal ST1 ends, the pulse of the clock signal CA is generated. The end time of the pulse of the start signal ST1 essentially coincides with the start time of the pulse of the clock signal CA. As the pulse of the start signal ST2 ends, the pulses of the clock signals CA to CH are generated sequentially and repeatedly. Regarding the clock signals CA to CH, subsequent pulses are generated as the previous pulse ends. Figure 7A In the example, the end and start times of the continuous pulses roughly coincide. However, these times do not necessarily have to coincide.

[0099] The shift register unit outputs sequential turn-on pulses from the highest-level shift register unit 311 to the lowest-level shift register unit 316. Figure 7A In the process, a pulse is generated in the output signal OUT1 of the first shift register unit 311, and then a pulse is generated in the output signal OUT2 of the next-level shift register unit 312. Then, subsequent shift register units output sequential pulses, and finally, a turn-on pulse is generated in the output signal OUT8N of the lowest-level shift register unit 316.

[0100] Figure 7B It shows having Figure 6A and 6B Another timing diagram of the signals in the shift register configuration shown. Figure 7B In the control shown, the scanning direction is from the lowest-level shift register unit 316 to the highest-level shift register unit 311. Time TM10 is the start time of each frame period. During each frame period, control signal DIR1 is at a low level (VGL), and control signal DIR2 is at a high level (VGH). At time TM10, a pulse of start signal ST2 is generated. Then, start signal ST2 remains at a low level (VGL) until the next frame period.

[0101] As the pulse of the start signal ST2 ends, the pulse of the clock signal CH is generated. The end time of the pulse of the start signal ST2 essentially coincides with the start time of the pulse of the clock signal CH. As the pulse of the start signal ST2 ends, the pulses of the clock signals CH to CA are generated sequentially and repeatedly. Regarding the clock signals CH to CA, the next pulse is generated as the previous pulse ends. Figure 7B In the example, the end and start times of the continuous pulses roughly coincide. However, these times do not necessarily coincide.

[0102] The shift register unit outputs sequential turn-on pulses from the lowest-level shift register unit 316 to the highest-level shift register unit 311. Figure 7BIn the process, a pulse is generated in the output signal OUT8N of the first shift register unit 361, and then a pulse is generated in the output signal OUT8N-1 of the next-level shift register unit 315. Then, subsequent shift register units output sequential pulses, and finally, a turn-on pulse is generated in the output signal OUT1 of the highest-level shift register 311.

[0103] The pull-down N-type TFT in a shift register cell experiences fluctuations in its Id-Vg characteristics (Vth fluctuations) due to the positive bias stress during the on-state. For example, in an N-type TFT, the Vth voltage fluctuates towards the higher voltage side. As a result, the driving performance of the pull-down TFT is reduced, and the TFT cannot be precisely controlled. This is thought to be due to the sequential formation of charge injection into the gate insulating film and the semiconductor film. In the case of amorphous silicon, the characteristic fluctuations are particularly high, and can also occur in other semiconductors, such as oxide semiconductors and low-temperature polycrystalline silicon semiconductors, as well as pull-up P-type TFTs. A pull-up TFT is a TFT used to raise a given node to a high supply potential VGH. Either the source or drain of the pull-up TFT is connected to the given node, and the other is connected to a power supply line at the high supply potential.

[0104] As described above, according to one embodiment of this specification, a plurality of pull-down transistors (TFTs) T5 to T12 are connected in parallel to the output line OT of the shift register unit and are controlled to be turned on / off by different clock signals CLK1 to CLK8. The parallel-connected pull-down TFTs are cyclically and sequentially turned on / off.

[0105] As a result, each pull-down TFT is driven with a low duty cycle. Consequently, the proportion of the on-state period decreases, and therefore, the characteristic fluctuations of the pull-down TFT are mitigated. Furthermore, the proportion of the off-state period increases, and therefore, characteristic fluctuations opposite to those of the on-state period are promoted. As a result, the degradation of the pull-down TFT's driving performance is effectively mitigated. Furthermore, as referenced... Figure 4 and Figure 5 As described above, transistor T2 is a pull-down TFT of node N1, and its on-state ratio is similarly small to that of transistor T5. Therefore, the decrease in the driving capability of transistor T2 can be effectively mitigated.

[0106] The duty cycle of the pull-down transistor connected to the output line depends on the number of clock signals controlling the transistor. The duty cycle of the pull-down transistor is matched to the duty cycle of the high level of the clock signal. Figure 8 The relationship between the number of clock signals and the duty cycle is illustrated schematically. With clock signals of 2, 4, 8, 10, 16, and 20, the duty cycles are 50%, 25%, 12.5%, 10%, 6.25%, and 5% or less, respectively.

[0107] Figure 9 The measurement results showing the relationship between the duty cycle of the gate signal and the characteristic fluctuations of the amorphous silicon N-type TFT are presented. The measurements were performed by continuously applying gate signals with different duty cycles to the gate of the amorphous silicon N-type TFT for 500 hours. Figure 9 The measurement results show that the characteristic fluctuation amount does not change substantially from a duty cycle of 100% to 25%. However, as the duty cycle decreases from 25% to 12.5%, the characteristic fluctuation amount decreases significantly. Therefore, the duty cycle of the gate signal is important for effectively mitigating the characteristic fluctuation of pull-down TFTs, and the characteristic fluctuation can be greatly reduced by setting the duty cycle to 12.5% ​​or less.

[0108] As mentioned above, the characteristic fluctuations of TFTs are most pronounced for amorphous silicon. Therefore, by setting the duty cycle to 12.5% ​​or less, the characteristic fluctuations of pull-down or pull-up TFTs made of oxide semiconductors or low-temperature polycrystalline silicon can be effectively mitigated.

[0109] Reference Figure 4 and Figure 5 In the described configuration example, eight pull-down transistors T5 to T12 are controlled by separate clock signals CLK1 to CLK8. By applying non-overlapping (separate) conduction cycles to transistors T5 to T12, the duty cycle of each pull-down transistor can be reduced to 12.5% ​​or less.

[0110] The number of pull-down transistors connected to the output line is determined by the design and can be greater than or less than eight. The duty cycle of each pull-down transistor can be reduced to 12.5% ​​or less by adjusting the clock signal controlling the pull-down transistors. One clock signal can control multiple pull-down transistors simultaneously.

[0111] <Example 2>

[0112] Next, a configuration example will be described in which each scan line 206 is driven by shift register units located on both sides of the display area 125. By making the left and right frame widths of the liquid crystal display device closer together, the display characteristics of the liquid crystal display device can be improved. By arranging shift register units on both sides of the display area 125, display characteristics can be improved while reducing the size of the frame area.

[0113] Figure 10 This diagram illustrates a configuration example where shift register units 320A and 320B output signals to both sides of a scan line 206. Shift register units 320A and 320B simultaneously output selection pulses of the same width to scan line 206. The description here will primarily focus on... Figure 4 The differences between the configuration examples shown. Assigned and Figure 4 Elements with the same reference numerals Figure 4 The components in are the same. The signals input to the shift register unit 320A include signals IN1, IN2, DIR1, DIR2, CLK1, CLK2, CLK4, CLK6, and CLK8. Different from Figure 4 the configuration example of, the clock signals CLK3, CLK5, and CLK7 are omitted.

[0114] The shift register unit 320A includes transistors T0A to T6A, T8A, T10A, and T12, and two capacitors C1A and C2A. These respectively correspond to Figure 4 the transistors T0 to T6, T8, T10, and T12 and the capacitors C1 and C2 of the shift register unit 310 of, and have a similar configuration and similar operations. Node N1A corresponds to node N1, and its potential change is the same. Node N2A corresponds to node N2, and its potential change is the same.

[0115] The shift register unit 320B includes transistors T0B to T5B, T7B, T9B, and T11B, and two capacitors C1B and C2B. These respectively correspond to Figure 4 the transistors T0 to T5, T7, T9, and T11 and the capacitors C1 and C2 of the shift register unit 310 of, and have a similar configuration and similar operations. Transistors T7B, T9B, and T11B are examples of the fourth thin film transistors. Alternatively, transistors T6A, T8A, T10A, and T12A are examples of the fourth thin film transistors. Node N1B corresponds to node N1, and its potential change is the same. Node N2B corresponds to node N2, and its potential change is the same.

[0116] Figure 11A Shows a part of the shift register that can be installed in the scan driver 131. Specifically, Figure 11A shows the top-level shift register unit 331A and the lower-level shift register 332A (the next level or the previous level) starting from it. The shift register units 331A and 332A can each have the circuit configuration of the shift register unit 320A described in reference to Figure 10 . In this example, the shift register is composed of 8N linked shift register units (N is a positive integer). [[ID={22}]]

[0117] Here, the differences from the Figure 6A shown configuration example will be mainly described. Each shift register unit includes a plurality of signal terminals. One signal terminal is an output signal terminal for outputting the signal OUT. The other signal terminals are input signal terminals for signals IN1, IN2, DIR1, DIR2, CLK1, CLK2, CLK4, CLK6, CLK8, and the low power supply potential VGL. Different from Figure 6A Compared to shift register units 311 and 312, the input terminals for clock signals CLK3, CLK5 and CLK7 are omitted.

[0118] The start signal ST1 is input to the signal terminal IN1 of the highest-level shift register unit 331A. The output signal OUT1 of the previous-level shift register unit 331A is input to the signal terminal IN1 of the next-level shift register unit 322A.

[0119] The output signal OUT from the next (previous) stage shift register unit (not shown) is input to the signal terminal IN2 of shift register unit 332A. The output signal OUT2 of the next (previous) stage shift register unit 332A is input to the signal terminal IN2 of shift register unit 331A.

[0120] In shift register unit 331A, clock signals CA, CB, CD, CF, and CH have been input to the signal terminals for clock signals CLK1, CLK2, CLK4, CLK6, and CLK8. In shift register unit 332A, clock signals CB, CC, CE, CG, and CA have been input to the signal terminals for clock signals CLK1, CLK2, CLK4, CLK6, and CLK8.

[0121] Figure 11B Another portion of the shift register that can be installed in scan driver 131 is shown. Specifically, Figure 11B The diagram shows the lowest-level shift register unit 336A and the preceding shift register unit 335A (the next or previous level). Shift register units 335A and 336A are the 8N-1 and 8Nth shift register units respectively, starting from the highest level. Shift register units 335A and 336A may each have a reference... Figure 10 The circuit configuration of the shift register unit 320A is described.

[0122] This section will primarily describe the differences from shift register units 331A and 332A. The output signal OUT of the previous stage (not shown) shift register unit is input to the signal terminal IN1 of shift register unit 335A. The output signal OUT8N-1 of the previous stage (previous stage) shift register unit 335A is input to the signal terminal IN1 of shift register unit 336A.

[0123] The start signal ST2 is input to the signal terminal IN2 for shift register unit 336A. The output signal OUT8N of the next (previous) stage shift register unit 336A is input to the signal terminal IN2 for shift register unit 335A.

[0124] In shift register unit 335A, clock signals CG, CH, CB, CD, and CF have been input to the signal terminals for clock signals CLK1, CLK2, CLK4, CLK6, and CLK8. In shift register unit 336A, clock signals CH, CA, CC, CE, and CG have been input to the signal terminals for clock signals CLK1, CLK2, CLK4, CLK6, and CLK8.

[0125] Already to Figure 11A and 11B The shift register shown has each clock signal terminal input to the shift register cell of each stage, which is connected to the clock signal input. Figure 6A and 6B The clock signal is the same for the corresponding clock signal terminal of the corresponding shift register unit in the configuration example shown.

[0126] Figure 12A A portion of a shift register that can be installed in scan driver 132 is shown. Specifically, Figure 12A The diagram shows the highest-level shift register unit 331B and the next-level or previous-level shift register 332B. Shift register units 331B and 332B may each have a reference... Figure 10 The circuit configuration of shift register unit 320B is described. In this example, the shift register consists of 8N linked shift register units (N is a positive integer).

[0127] This section will mainly describe and Figure 6A The differences in the configuration example shown are as follows: Each shift register unit includes multiple signal terminals. One signal terminal is the output signal terminal for the output signal OUT. The other signal terminals are the input signal terminals for signals IN1, IN2, DIR1, DIR2, CLK1, CLK3, CLK5, and CLK7, as well as the low power supply potential VGL. (The last sentence appears to be incomplete and possibly refers to a different configuration.) Figure 6A Compared to shift register units 311 and 312, the input terminals for clock signals CLK2, CLK4, CLK6 and CLK8 are omitted.

[0128] The start signal ST1 is input to the signal terminal IN1 of the highest-level shift register unit 331B. The output signal OUT1 of the previous-level shift register unit 331B is input to the signal terminal IN1 of the next-level shift register unit 322B.

[0129] The output signal OUT from the next (previous) stage shift register unit (not shown) is input to the signal terminal IN2 of shift register unit 332B. The output signal OUT2 of the next (previous) stage shift register unit 332B is input to the signal terminal IN2 of shift register unit 331B.

[0130] In shift register unit 331B, clock signals CA, CC, CE, and CG have been input to the signal terminals for clock signals CLK1, CLK3, CLK5, and CLK7. In shift register unit 332B, clock signals CB, CD, CF, and CH have been input to the signal terminals for clock signals CLK1, CLK3, CLK5, and CLK7.

[0131] Figure 12B Another portion of the shift register that can be installed in scan driver 132 is shown. Specifically, Figure 12B The lowest-level shift register unit 336B and the preceding shift register 335B (the next or previous level) are shown. Shift register units 335B and 336B are the 8N-1 and 8Nth shift register units from the highest level, respectively. Shift register units 335B and 336B may each have a reference... Figure 10 The circuit configuration of the shift register unit 320B is described.

[0132] This section will primarily describe the differences from shift register units 331B and 332B. The output signal OUT of the previous stage shift register unit (not shown) is input to the signal terminal IN1 of shift register unit 335B. The output signal OUT8N-1 of the previous stage shift register unit 335B is input to the signal terminal IN1 of shift register unit 336B.

[0133] The start signal ST2 is input to the signal terminal IN2 of shift register unit 336B. The output signal OUT8N of the next (previous) stage shift register unit 336B is input to the signal terminal IN2 of shift register unit 335B.

[0134] In shift register unit 335B, clock signals CG, CA, CC, and CE have been input to the signal terminals used for clock signals CLK1, CLK3, CLK5, and CLK7. In shift register unit 336B, clock signals CH, CB, CD, and CF have been input to the signal terminals used for clock signals CLK1, CLK3, CLK5, and CLK7.

[0135] Already to Figure 12A and 12B The shift register shown has each clock signal terminal input to the shift register cell of each stage, which is connected to the clock signal input. Figure 6A and 6B The clock signal is the same for the corresponding clock signal terminal of the corresponding stage shift register unit in the configuration example shown. (Reference) Figures 10 to 12B The description covers the time-varying input and output signals of two shift registers, as well as the operation and reference of the shift registers. Figure 7A and 7B The description is the same.

[0136] In the example above, the rising and falling of the selection pulses output by the shift register units on both sides of each scan line 206 occur simultaneously. The number of pull-down TFTs for scan line 206 in shift register unit 320A is 5, and the number of pull-down TFTs in shift register unit 320B is 4. Therefore, since the difference in the number of pull-down TFTs on both sides of the scan line is one or less, the size of the frame region can be effectively reduced.

[0137] Transistors T5A and T5B are simultaneously turned on / off. The other pull-down TFTs of scan line 206 are alternately turned on between the left shift register unit 320A and the right shift register unit 320B. That is, transistors 6A, 7B, 8A, 9B, 10A, 11B, and 12A are turned on in the aforementioned order. Therefore, by alternately selecting the transistors to be turned on in the shift register units on both sides, the impact of the configuration of using two shift register units to control the potential of the scan line on display quality can be reduced.

[0138] <Example 3>

[0139] In the embodiments described below in this specification, the pull-down TFTs of the output lines (scan lines) of the shift register unit are intermittently turned on. After the output line is connected to a low power supply line via the pull-down TFT, the pull-down TFT is turned off, and the output line is in a floating state until the next pull-down TFT is turned on. The potential of the output line in the floating state remains at VGL. The number of pull-down TFTs can be reduced by inserting floating cycles in which all pull-down TFTs are off between one or more pull-down cycles in which pull-down TFTs are turned on.

[0140] Figure 13 An example configuration of a shift register unit 350 according to one embodiment of this specification is shown. Figure 4Compared to the shift register unit 310 shown, transistors T7, T9, and T11 are omitted. Other constituent elements are the same as those in shift register unit 310. Furthermore, the clock signals CLK3, CLK5, and CLK7, which control transistors T7, T9, and T11 respectively, are omitted from the input signals to shift register unit 310. Other signals are the same as those to be input to shift register unit 310.

[0141] Clock signals CLK3, CLK5, and CLK7 are omitted, and therefore, the output lines are pulled down for each clock signal. There is a floating period between the turn-on pulses of each clock signal CLK2, CLK4, CLK6, and CLK8.

[0142] Figure 14A A portion of a shift register that can be installed in scan driver 131 or 132 is shown. Specifically, Figure 14A The highest-level shift register unit 351 and the lower-level shift register 352 (next or previous stage) are shown. Shift register units 351 and 352 may each have a reference... Figure 13 The circuit configuration and operation are described. In this example, the shift register consists of 8N linked shift register cells (N is a positive integer).

[0143] and Figure 6A Compared to the configuration example, the input terminals for clock signals CLK3, CLK5, and CLK7 are omitted from shift register units 351 and 352. Other parts are the same as... Figure 6A The configuration example shown is the same.

[0144] Figure 14B Another portion of the shift register, which can be installed in scan driver 131 or 132, is shown. Specifically, Figure 14B The lowest-level shift register unit 356 and the preceding (next or previous) shift register unit 355 are shown. Shift register units 355 and 356 are the 8N-1 and 8Nth shift register units from the highest level, respectively. Shift register units 355 and 356 may each have a reference... Figure 13 The circuit configuration and operation are described.

[0145] The output signal OUT of the previous stage shift register unit (not shown) is input to the signal terminal IN1 of shift register unit 355. The output signal OUT8N-1 of the previous stage shift register unit 355 is input to the signal terminal IN1 of shift register unit 356.

[0146] The start signal ST2 is input to the signal terminal IN2 of the shift register unit 316, and the output signal OUT8N of the next (previous) shift register unit 356 is input to the signal terminal IN2 of the shift register unit 355.

[0147] In shift register unit 355, clock signals CG, CH, CB, CD, and CF have been input to the signal terminals for clock signals CLK1, CLK2, CLK4, CLK6, and CLK8. In shift register unit 356, clock signals CH, CA, CC, CE, and CG have been input to the signal terminals for clock signals CLK1, CLK2, CLK4, CLK6, and CLK8.

[0148] The changes in the input and output signals of the shift register over time are shown in the reference. Figure 7A and 7B The shift register in this embodiment, except that the clock signal is not input to the shift register unit, has the same characteristics as the reference. Figure 4 and Figure 7B The configuration described is similar to the configuration.

[0149] In the example above, the floating period has the same length as each on-cycle of the pull-down TFT. Alternatively, the floating period can be longer than the on-cycle. For example, Figure 13 The configuration example shown can also omit transistors T8 and T12.

[0150] As described above, embodiments of the present disclosure have been presented; however, the present disclosure is not limited to the foregoing embodiments. Those skilled in the art can readily modify, add to, or transform each element in the foregoing embodiments within the scope of this disclosure. A portion of the configuration of one embodiment may be replaced by the configuration of another embodiment, or the configuration of one embodiment may be incorporated into the configuration of another embodiment.

Claims

1. A display device, comprising: Multiple pixel circuit rows; Multiple selection lines are connected to the multiple pixel circuit rows; as well as A shift register consists of multiple linked shift register cells. The multiple linked shift register units output sequential selection pulses to the multiple selection lines. Each of the plurality of linked shift register units outputs the selection pulse to the corresponding selection line among the plurality of selection lines. Each shift register unit in the shift register unit includes a plurality of thin-film transistors of a first conductivity type connected in parallel, which connect the corresponding select line to a fixed potential wiring for applying the non-selection level of the select pulse during the on state. During each frame period, the plurality of thin-film transistors are turned on / off by clock signals of different phases, and During each frame period, the duty cycle of each of the plurality of thin-film transistors is 12.5% ​​or less. The shift register is the first shift register. The display device further includes a second shift register, which is positioned opposite to the first shift register across the plurality of select lines. The second shift register includes multiple linked second shift register units that, together with the first shift register, sequentially output the selection pulses to the multiple selection lines. Each of the plurality of linked second shift register units includes a plurality of fourth thin-film transistors of the first conductivity type connected in parallel to the fixed potential wiring that connects the corresponding select line to the non-selection level of the applied select pulse during the on state. During each frame period, the plurality of fourth thin-film transistors are turned on / off by clock signals of different phases from each other. Wherein, the clock signal of the first shift register has a different phase than the clock signal controlling the plurality of fourth thin-film transistors, and During each frame period, the duty cycle of the conduction period of each of the plurality of fourth thin-film transistors is 12.5% ​​or less, wherein the difference between the number of thin-film transistors connecting each select line of the first shift register to the wiring applying the non-select level and the number of thin-film transistors connecting each select line of the second shift register to the fixed potential wiring applying the non-select level is 1 or less. In this configuration, a thin-film transistor selected from the plurality of thin-film transistors in the first shift register and a fourth thin-film transistor selected from the plurality of fourth thin-film transistors are alternately turned on.

2. The display device according to claim 1, in, Each of the plurality of thin-film transistors is an N-type amorphous silicon thin-film transistor, and The non-selection level is a low level.

3. The display device according to claim 1, in, Each shift register unit also includes: A second thin-film transistor of the first conductivity type, in its on-state, applies the selection level of the selection pulse to the corresponding selection line; and The third thin-film transistor of the first conductivity type, in its on-state, connects the fixed-potential wiring to the gate of the second thin-film transistor, and The third thin-film transistor is controlled by the same clock signal as one of the plurality of thin-film transistors.

4. The display device according to claim 1, in, All the thin-film transistors, each of which is connected to the fixed-potential wiring, are controlled by clock signals of different phases.

5. A display device, comprising: Multiple pixel circuit rows; Multiple selection lines are connected to the multiple pixel circuit rows; as well as A shift register consists of multiple linked shift register cells. The multiple linked shift register units output sequential selection pulses to the multiple selection lines. Each of the plurality of linked shift register units outputs the selection pulse to the corresponding selection line among the plurality of selection lines. Each shift register unit in the shift register unit includes a plurality of thin-film transistors of a first conductivity type connected in parallel, which connect the corresponding select line to a fixed potential wiring for applying the non-selection level of the select pulse during the on state. During each frame period, the plurality of thin-film transistors are turned on / off by clock signals of different phases, and During each frame period, the duty cycle of each of the plurality of thin-film transistors is 12.5% ​​or less. During each frame period, the plurality of thin-film transistors are cyclically and sequentially turned on and off. Among these, a floating period exists between the consecutive on-cycles of the plurality of thin-film transistors, during which all of the plurality of thin-film transistors are off, and During the floating period, the corresponding selection line is in a floating state. Wherein, the length of the continuous conduction period is less than or equal to the length of the floating period.

6. The display device according to claim 5, in, Each of the plurality of thin-film transistors is an N-type amorphous silicon thin-film transistor, and The non-selection level is a low level.

7. The display device according to claim 5, in, Each shift register unit also includes: A second thin-film transistor of the first conductivity type, in its on-state, applies the selection level of the selection pulse to the corresponding selection line; and The third thin-film transistor of the first conductivity type, in its on-state, connects the fixed-potential wiring to the gate of the second thin-film transistor, and The third thin-film transistor is controlled by the same clock signal as one of the plurality of thin-film transistors.

8. The display device according to claim 5, in, All the thin-film transistors, each of which is connected to the fixed-potential wiring, are controlled by clock signals of different phases.

9. A display device, comprising: Multiple pixel circuit rows; Multiple selection lines are connected to the multiple pixel circuit rows; as well as A shift register consists of multiple linked shift register cells. The multiple linked shift register units output sequential selection pulses to the multiple selection lines. Each of the plurality of linked shift register units outputs the selection pulse to the corresponding selection line among the plurality of selection lines. Each shift register unit in the shift register unit includes a plurality of thin-film transistors of a first conductivity type connected in parallel, which connect the corresponding select line to a fixed potential wiring for applying the non-selection level of the select pulse during the on state. During each frame period, the plurality of thin-film transistors are turned on / off by clock signals of different phases, and During each frame period, the duty cycle of each of the plurality of thin-film transistors is 12.5% ​​or less. During each frame period, the plurality of thin-film transistors are cyclically and sequentially turned on / off, and The end and start of the continuous conduction cycles of the plurality of thin-film transistors are basically matched.

10. The display device according to claim 9, in, Each of the plurality of thin-film transistors is an N-type amorphous silicon thin-film transistor, and The non-selection level is a low level.

11. The display device according to claim 9, in, Each shift register unit also includes: A second thin-film transistor of the first conductivity type, in its on-state, applies the selection level of the selection pulse to the corresponding selection line; and The third thin-film transistor of the first conductivity type, in its on-state, connects the fixed-potential wiring to the gate of the second thin-film transistor, and The third thin-film transistor is controlled by the same clock signal as one of the plurality of thin-film transistors.

12. The display device according to claim 9, in, All the thin-film transistors, each of which is connected to the fixed-potential wiring, are controlled by clock signals of different phases.

Images