A readout circuit for MTM antifuse PROM

Abstract

The application discloses a readout circuit suitable for MTM anti-fuse PROM and belongs to the field of semiconductor integrated circuits, and comprises an isolation tube N1, a pre-charge tube P0, a pull-down tube N0, a voltage-limiting protection resistor R0, a recognition inverter INV1, a conventional inverter INV2, a programming control signal Prog_VC and a readout enable signal SA_EN. The added voltage-limiting protection resistor R0 is greater than the resistance of the MTM anti-fuse after programming, but is far smaller than the resistance of the MTM anti-fuse before programming. When the storage unit stores data 0, the MTM anti-fuse is not programmed, and the resistance is extremely high. When the readout operation is performed, the voltage difference between the two ends of the MTM anti-fuse can be effectively reduced by the voltage-limiting protection resistor, so that the unprogrammed MTM anti-fuse is protected, and the reliability of the MTM anti-fuse PROM memory is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a readout circuit suitable for MTM antifuse PROM. Background Technology

[0002] MTM antifuses are one-time programmable devices. After programming, the physical state of the MTM antifuse changes to achieve different storage states. MTM antifuses inherently possess excellent radiation resistance, and programming is unrecoverable, offering advantages such as non-volatility, small size, high speed, and high reliability. MTM antifuse-based PROM memories are small in size, low in manufacturing cost, and highly reliable, capable of stably and reliably storing data. They have unparalleled advantages in the harsh environments of outer space, characterized by high radiation, large temperature differences between day and night, and severe electromagnetic interference. MTM antifuse PROMs offer advantages such as fast read speed, low power consumption, strong radiation resistance, high reliability, and good security, and are widely used in aerospace environments. These advantages are becoming increasingly prominent.

[0003] MTM antifuse units consist of two conductive electrode layers with an antifuse dielectric layer between them. Before programming, the antifuse unit exhibits insulating properties with a resistance on the order of 250 GΩ. Programming the antifuse unit involves applying a programming voltage between the two electrode layers, forming a conductive wire between the two conductive electrode layers, thus exhibiting conductive properties and exhibiting low resistance, below 200 ohms after programming. The MTM antifuse PROM stores data 1 for programmed antifuse units and data 0 for unprogrammed antifuse units.

[0004] Antifuses are classified into different types based on the electrode and dielectric materials, resulting in different MTM antifuse processes. Depending on the MTM antifuse process, as well as differences in programming voltage, programming current, and programming pulse, the resistance of the antifuse unit after programming will vary. Even under the same process, the post-programming resistance of the antifuse units on different fabrication batches, different wafers within the same batch, and different MTM antifuse PROM chips on the same wafer will differ. The post-programming resistance of the antifuse unit has a significant impact on the data readout of the antifuse PROM.

[0005] To improve the storage density, capacity, cost reduction, and manufacturing yield of MTM antifuse PROM memory, MTM antifuse PROM memory uses single-ended storage cells. This means each storage cell has only one storage node, storing only the corresponding data 0 or 1. Unlike SRAM storage cells, which differentially store both 0 and 1 simultaneously, a single storage cell does not. The structure of the storage cell is as follows... Figure 1 As shown.

[0006] To ensure reliable readout, traditional MTM antifuse PROMs, after programming, pre-charge the readout bit line BL and its parasitic capacitance to VDD level before reading data. Then, the amplifier is enabled, allowing the memory cell to discharge the readout bit line BL. For programmed antifuse memory cells, the antifuse resistance is below 200 ohms after programming, allowing for rapid discharge of the BL voltage from VDD down to a lower level. However, for unprogrammed memory cells, the antifuse resistance is in the 250 GΩ range, preventing discharge of the BL voltage, which remains close to VDD. This results in a prolonged period of near-VDD voltage across the unprogrammed antifuse terminals. During extended operation, the near-VDD voltage applied during readout can cause weak breakdown programming in the unprogrammed antifuse memory, affecting the overall reliability of the antifuse PROM. Summary of the Invention

[0007] The purpose of this invention is to provide a readout circuit suitable for MTM antifuse PROM to solve the problems in the background art.

[0008] To solve the above technical problems, the present invention provides a readout circuit suitable for MTM antifuse PROM, including isolation transistor N1, precharge transistor P0, pull-down transistor N0, voltage limiting protection resistor R0, identification inverter INV1, conventional inverter INV2, programming control signal Prog_VC and readout enable signal SA_EN;

[0009] The drain of the isolation transistor N1 is connected to the bit line BL, the gate is connected to the programming control signal Prog_VC, and the source is connected to the critical node D0. The first end of the voltage limiting protection resistor R0 is connected to the critical node D0, and the second end is grounded. The source of the pull-down transistor N0 is grounded, the gate is connected to the readout enable signal SA_EN, and the drain is connected to the critical node D0. The drain of the precharge transistor P0 is connected to the power supply VDD, the gate is connected to the readout enable signal SA_EN, and the source is connected to the critical node D0. The critical node D0 is connected to the input of the identification inverter INV1. Adjusting the flip level of the identification inverter INV1 accurately identifies the level of the critical node D0 in the programmed and unprogrammed states. The output of the identification inverter INV1 is connected to the input of the conventional inverter INV2. The conventional inverter INV2 inverts the output of the identification inverter INV1 and uses it as the output result of the readout circuit, i.e., the data stored in the memory cell.

[0010] In one implementation, when the readout circuit for the MTM antifuse PROM is being programmed, the programming control signal PROG_VC is low for isolation protection; when the readout circuit for the MTM antifuse PROM is being read, PROG_VC is high to connect the bit line BL to the readout circuit.

[0011] In one implementation, when no read operation is performed, the read enable signal SA_EN is high, the pull-down transistor N0 is turned on, and the precharge transistor P0 is turned off, keeping the critical node D0 at a low level. When a read operation is performed, the read enable signal SA_EN jumps to a low level, the pull-down transistor N0 is turned off, and the precharge transistor P0 is turned on, charging the critical node D0 and the bit line BL.

[0012] In one implementation, when the MTM antifuse in the memory cell is programmed and its resistance is low (less than 200 ohms), the critical node D0 and bit line BL will be pulled down to a low level by the resistance of the MTM antifuse during a read operation. When the MTM antifuse in the memory cell is not programmed and its resistance is high (greater than 250 G ohms), the critical node D0 and bit line BL cannot be pulled down by the resistance of the MTM antifuse during a read operation.

[0013] In one implementation, during a read operation, the precharge transistor P0 charges the critical node D0 and the bit line BL, and the voltage limiting protection resistor R0 pulls down the voltage of the critical node D0 and the bit line BL, thereby limiting the voltage of the critical node D0 and the bit line BL to a safe range, thus protecting the unprogrammed MTM antifuse in the memory cell.

[0014] In one embodiment, the resistance value of the voltage limiting protection resistor R0 is 5 to 20 times the maximum resistance value after the MTM antifuse is programmed.

[0015] This invention provides a readout circuit for an MTM antifuse PROM, comprising an isolation transistor, a pre-charge transistor, a pull-down transistor, a voltage-limiting protection resistor, an identification inverter, and a conventional inverter. The added voltage-limiting protection resistor is much larger than the programmed resistance of the MTM antifuse, but much smaller than the unprogrammed resistance. When the memory cell stores data 0, the MTM antifuse is unprogrammed and its resistance is extremely high. During the readout operation, the voltage-limiting protection resistor effectively reduces the voltage difference across the MTM antifuse, thereby protecting the unprogrammed MTM antifuse and improving the reliability of the MTM antifuse PROM memory. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of an MTM antifuse PROM memory cell.

[0017] Figure 2 This is a schematic diagram of a readout circuit structure suitable for MTM antifuse PROM provided by the present invention. Detailed Implementation

[0018] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of a readout circuit suitable for an MTM antifuse PROM. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0019] Current MTM antifuse PROM memory units, such as Figure 1 As shown, it includes a precharge protection transistor M2, an MTM antifuse F1, a programming current limiting transistor M1, a precharge control signal PRE, and a word line WL. When the memory cell is not accessed, the word line WL is low and the programming current limiting transistor M1 is off; when the memory cell is read, the precharge control signal PRE is low, the word line WL is high, and the programming current limiting transistor M1 is on.

[0020] This invention provides a readout circuit suitable for MTM antifuse PROM, such as... Figure 2 As shown, it includes isolation transistor N1, precharge transistor P0, pull-down transistor N0, voltage limiting protection resistor R0, identification inverter INV1, conventional inverter INV2, programming control signal Prog_VC, and readout enable signal SA_EN. The drain of the isolation transistor N1 is connected to the bit line BL, the gate is connected to the programming control signal Prog_VC, and the source is connected to the critical node D0. The first end of the voltage limiting protection resistor R0 is connected to the critical node D0, and the second end is grounded. The source of the pull-down transistor N0 is grounded, the gate is connected to the readout enable signal SA_EN, and the drain is connected to the critical node D0. The drain of the precharge transistor P0 is connected to the power supply VDD, the gate is connected to the readout enable signal SA_EN, and the source is connected to the critical node D0. The critical node D0 is connected to the input of the identification inverter INV1. The flip level of the identification inverter INV1 is adjusted and designed so that the level of the critical node D0 can be accurately identified in both programmed and unprogrammed states. The output of the identification inverter INV1 is connected to the input of the conventional inverter INV2. The conventional inverter INV2 inverts the output of the identification inverter INV1 and uses it as the output result of the readout circuit, i.e., the data stored in the memory cell.

[0021] The resistance value of the voltage limiting protection resistor R0 can be 5 to 20 times the maximum resistance value after the MTM antifuse is programmed. In the embodiment of the present invention, it is specifically designed to be 10 times.

[0022] When no read operation is performed, the programming control signal Prog_VC is driven to the GND level, the isolation transistor N1 is turned off, and the read enable signal SA_EN is VDD high, the precharge transistor P0 is turned off, and the pull-down transistor N0 is turned on, so that the critical node D0 is pulled down to the GND level.

[0023] During the read operation, the programming control signal Prog_VC is driven to VDD high level, turning on the isolation transistor N1. At the same time, the read enable signal SA_EN is GND low level, the precharge transistor P0 is turned on, and the pull-down transistor N0 is turned off. The critical node D0 and bit line BL are charged through the precharge transistor P0.

[0024] When the memory cell stores data 1, the MTM antifuse F1 in the cell is programmed. The resistance of the MTM antifuse F1 is less than 200 ohms. During readout, the precharge transistor P0 charges the critical node D0 and the bit line BL. The critical node D0 and the bit line BL then discharge through the small resistance of the MTM antifuse in the memory cell and the path of the programming current-limiting transistor M1, and also through the voltage-limiting protection resistor R0. Since the resistance of the voltage-limiting protection resistor R0 is much larger than the resistance of the MTM antifuse F1, the discharge is mainly achieved through the resistance of the MTM antifuse in the memory cell.

[0025] When the memory cell stores data 0, the MTM antifuse F1 in the cell is not programmed, and its resistance is greater than 250 GΩ, so it is in the off state. During readout, the precharge transistor P0 charges the critical node D0 and bit line BL. However, the critical node D0 and bit line BL cannot discharge through the path of the MTM antifuse's large resistance and the programming current-limiting transistor M1 in the memory cell; they can only discharge through the voltage-limiting protection resistor R0.

[0026] Because the resistance of the voltage-limiting protection resistor R0 is much larger than the resistance value of the MTM antifuse after programming, the resistance difference between the discharge path of the critical node D0 and the bit line BL is large in the two states of stored data 1 and stored data 0. After final balancing, the voltages formed on the critical node D0 and the bit line BL in the two states will also have a significant difference, thus enabling [the discharge path to be cleared]. Figure 2 The identification inverter INV1 in the readout circuit shown is used for identification.

[0027] On the other hand, for the storage cell storing data 0, during reading, due to the discharge of the voltage-limiting protection resistor R0, the voltage on the bit line BL will be at a low level after stabilization during the final read. During the read process, the voltage across the unprogrammed MTM antifuse F1 will remain at a low level, thereby protecting the unprogrammed MTM antifuse F1.

[0028] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A readout circuit suitable for MTM antifuse PROM, characterized in that, This includes isolation transistor N1, precharge transistor P0, pull-down transistor N0, voltage limiting protection resistor R0, identification inverter INV1, conventional inverter INV2, programming control signal Prog_VC, and readout enable signal SA_EN; The drain of the isolation transistor N1 is connected to the bit line BL, the gate is connected to the programming control signal Prog_VC, and the source is connected to the critical node D0; the first end of the voltage limiting protection resistor R0 is connected to the critical node D0, and the second end is grounded; the source of the pull-down transistor N0 is grounded, the gate is connected to the read enable signal SA_EN, and the drain is connected to the critical node D0; the drain of the precharge transistor P0 is connected to the power supply VDD, the gate is connected to the read enable signal SA_EN, and the source is connected to the critical node D0. The key node D0 is connected to the input terminal of the identification inverter INV1. By adjusting the flip level of the identification inverter INV1, the level of the key node D0 can be accurately identified in the two states of programming and non-programming. The output of the identification inverter INV1 is connected to the input of the conventional inverter INV2. The conventional inverter INV2 inverts the output of the identification inverter INV1 and uses it as the output of the readout circuit, i.e., the data stored in the memory cell. The resistance value of the voltage limiting protection resistor R0 is 5 to 20 times the maximum resistance value after the MTM antifuse is programmed.

2. The readout circuit for an MTM antifuse PROM as described in claim 1, characterized in that, When the read circuit for the MTM antifuse PROM is being programmed, the programming control signal PROG_VC is low for isolation protection; when the read circuit for the MTM antifuse PROM is being read, PROG_VC is high to connect the bit line BL to the read circuit.

3. The readout circuit for an MTM antifuse PROM as described in claim 1, characterized in that, When no read operation is performed, the read enable signal SA_EN is high, the pull-down transistor N0 is turned on, and the precharge transistor P0 is turned off, keeping the critical node D0 at a low level. When a read operation is performed, the read enable signal SA_EN jumps to a low level, the pull-down transistor N0 is turned off, and the precharge transistor P0 is turned on, charging the critical node D0 and the bit line BL.

4. The readout circuit for an MTM antifuse PROM as described in claim 1, characterized in that, When the MTM antifuse in the memory cell has been programmed, and the resistance of the MTM antifuse is small (less than 200 ohms), the critical node D0 and bit line BL will be pulled down to a low level by the resistance of the MTM antifuse during a read operation. When the MTM antifuse in the memory cell has not been programmed, and the resistance of the MTM antifuse is large (greater than 250 G ohms), the critical node D0 and bit line BL cannot be pulled down by the resistance of the MTM antifuse during a read operation.

5. The readout circuit for an MTM antifuse PROM as described in claim 1, characterized in that, During a read operation, the precharge transistor P0 charges the critical node D0 and bit line BL, while the voltage limiting protection resistor R0 pulls down the voltage of the critical node D0 and bit line BL, thus limiting the voltage of the critical node D0 and bit line BL to a safe range and protecting the unprogrammed MTM antifuse in the memory cell.

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