FCBGA packaging core board, packaging substrate and its preparation method

Abstract

This invention provides an FCBGA packaging core board, a packaging substrate, and a method for preparing the same. The method for preparing the packaging core board includes: providing a glass substrate, wherein the glass substrate is one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass, and quartz glass, with a coefficient of thermal expansion between 1 ppm / ℃ and 10 ppm / ℃ and a thermal conductivity between 1 W / m·K and 5 W / m·K; and performing heat treatment on the glass substrate; forming interconnect holes penetrating the glass substrate; forming a metal seed layer covering opposite sides of the glass substrate and the surface of the interconnect holes; forming a metal interconnect layer covering the metal seed layer, wherein the metal interconnect layer fills the interconnect holes; and patterning the metal interconnect layer and the metal seed layer until they are exposed on the surface of the glass substrate. The FCBGA packaging core board of this invention has the advantages of good dimensional stability, small warpage, good thermal conductivity, high strength, high wiring density, high reliability, short process flow, short production cycle, and low manufacturing cost, and is suitable for high-end chip packaging and heterogeneous integrated packaging.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to an FCBGA package core board, a package substrate, and a method for preparing the same. Background Technology

[0002] Flip Chip Ball Grid Array (FCBGA) is currently the primary packaging method for high-end chips. With the rapid development of the electronics industry, the number of I / O pins on chips has increased dramatically. As the connection mechanism between the chip and the printed circuit board, the packaging substrate requires increasingly precise wiring, and the control of warpage on the packaging substrate has become increasingly stringent. Furthermore, due to the rapid development of heterogeneous integration solutions, multiple chips can be simultaneously mounted on the packaging substrate, especially the FCBGA packaging substrate, or embedded chips can be formed within the packaging substrate, creating 2D, 2.5D, or 3D packages. All of these technological trends require packaging substrates, especially FCBGA packaging substrates, to have high wiring density, low warpage, and low cost.

[0003] In addition, as the integration of packaging substrates becomes higher and higher, the structure of packaging substrates becomes more and more complex. How to simplify the production process and reduce production costs is one of the problems that packaging substrates urgently need to solve today. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an FCBGA package core board, a package substrate and a method for preparing the same, so as to solve at least one of the above-mentioned problems faced by the FCBGA package substrate in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a method for preparing an FCBGA package core board, the method comprising:

[0006] A glass substrate is provided, wherein the glass substrate is one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass and quartz glass, and its coefficient of thermal expansion is between 1ppm / ℃ and 10ppm / ℃, including the endpoint value, and its thermal conductivity is between 1W / m·K and 5W / m·K, including the endpoint value. The glass substrate is heat-treated to relieve stress on the glass substrate.

[0007] Interconnecting holes are formed through the glass substrate;

[0008] A metal seed layer is formed covering the opposite sides of the glass substrate and the surface of the interconnect hole;

[0009] A metal interconnect layer is formed covering the metal seed layer, and the metal interconnect layer fills the interconnect holes;

[0010] The metal interconnect layer and the metal seed layer are patterned until the surface of the glass substrate is exposed to form an FCBGA package core board.

[0011] Optionally, the thickness of the glass substrate is between 0.03 mm and 3 mm, including the endpoint values.

[0012] Optionally, the weight percentage of dopants in the glass substrate is between 8% and 12%, including the endpoint values.

[0013] Alternatively, the interconnecting holes can be formed using a laser-induced etching method.

[0014] Optionally, the metal interconnect layer and the metal seed layer can be patterned using laser etching.

[0015] Furthermore, the laser used for laser etching is a carbon dioxide laser, a green laser, a UV laser, or an excimer laser, and the laser pulse is at the nanosecond, picosecond, or femtosecond level.

[0016] Optionally, the method for forming the metal interconnect layer includes: firstly, forming a first metal sub-interconnect layer covering the metal seed layer using a DC electroplating process; and then forming a second metal sub-interconnect layer covering the first metal sub-interconnect layer using an AC electroplating process, wherein the second metal sub-interconnect layer fills the interconnect via.

[0017] The present invention also provides a method for preparing an FCBGA packaging substrate, the method comprising:

[0018] Provide a packaging core board prepared by any of the preparation methods described above;

[0019] A dielectric layer is formed on both opposite sides of the encapsulation core board using a pressing method;

[0020] The dielectric layer is patterned to form blind vias penetrating the dielectric layer;

[0021] Based on the blind vias, a patterned circuit connection layer is formed that is electrically connected to the encapsulation core board;

[0022] Repeat the steps of the dielectric layer and the circuit connection layer until the required number of stacked layers are completed to form the FCBGA package substrate.

[0023] Optionally, after forming the required number of laminate layers, the process further includes: sequentially preparing a solder resist layer and a surface treatment layer on the surface of the resulting structure, and preparing solder balls in the desired area of ​​the surface treatment layer.

[0024] This invention also provides an FCBGA package core board, which is prepared using the FCBGA package core board preparation method described in any one of the above claims, and includes: a glass substrate, a patterned metal seed layer, and a patterned metal interconnect layer; wherein,

[0025] The glass substrate is one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass, and quartz glass, with a coefficient of thermal expansion between 1ppm / ℃ and 10ppm / ℃, including the endpoint value, and a thermal conductivity between 1W / m·K and 5W / m·K, including the endpoint value. The glass substrate is subjected to heat treatment to relieve stress on the glass substrate.

[0026] The glass substrate is provided with interconnecting holes that penetrate the glass substrate;

[0027] The metal seed layer covers the opposite sides of the glass substrate and the surface of the interconnect hole;

[0028] The metal interconnect layer covers the surface of the metal seed layer and fills the interconnect holes.

[0029] The present invention also provides an FCBGA packaging substrate, the packaging substrate comprising: an FCBGA packaging core board as described above and at least one stacked layer; wherein,

[0030] The stack includes a dielectric layer and a wiring connection layer. A blind via is formed in the dielectric layer, and the wiring connection layer fills the blind via and extends to a portion of the surface of the dielectric layer.

[0031] The circuit connection layer of the stacked board is connected to the metal interconnect layer of the encapsulation core board.

[0032] As described above, the FCBGA packaging core board, packaging substrate, and their preparation method of the present invention, and the FCBGA packaging substrate prepared by the preparation method of the FCBGA packaging core board of the present invention, have the advantages of good dimensional stability, small warpage deformation, good thermal conductivity, high strength, high wiring density, high reliability, short process, short production cycle, and low manufacturing cost, and are suitable for high-end chip packaging and heterogeneous integrated packaging fields. Attached Figure Description

[0033] Figure 1 The diagram shows the structure of the glass substrate in the method for preparing the FCBGA package core board of the present invention.

[0034] Figure 2 The diagram shows the structure after interconnect holes are formed in the preparation method of the FCBGA package core board of the present invention.

[0035] Figure 3The diagram shows the structure after the metal seed layer is formed in the preparation method of the FCBGA package core board of the present invention.

[0036] Figure 4 and Figure 5 The diagram shows the structure after the metal interconnect layer is formed in the preparation method of the FCBGA package core board of the present invention.

[0037] Figure 6 The diagram shown is a structural schematic of the FCBGA package core board after it has been formed in the preparation method of the FCBGA package core board of the present invention.

[0038] Figure 7 The diagram shows the structure after the patterned dielectric layer forms a blind via in the basic fabrication method of the FCBGA package of the present invention.

[0039] Figure 8 The diagram shows the structure after a circuit connection layer is formed in the basic fabrication method of the FCBGA package of the present invention.

[0040] Figure 9 The diagram shows the structure after forming the required number of circuit connection layers in the basic fabrication method of the FCBGA package of the present invention.

[0041] Figure 10 The diagram shows the structure after forming the solder resist layer and the surface treatment layer in the basic preparation method of the FCBGA package of the present invention.

[0042] Component designation explanation

[0043] 100 packaged core board

[0044] 101 glass substrate

[0045] 102 interconnect holes

[0046] 103 Metal Seed Layer

[0047] 104 Metal Interconnect Layer

[0048] 105 First Metal Interconnect Layer

[0049] 106 Second Metal Interconnect Layer

[0050] 107 Line Spacing

[0051] 201 Dielectric Layer

[0052] 202 Blind Hole

[0053] 203 Line Connection Layer

[0054] 204 solder mask

[0055] 205 Surface Treatment Layer Detailed Implementation

[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0058] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for the device in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more layers in between. The phrase “between” as used herein includes both endpoint values.

[0059] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0060] Please see Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0061] This embodiment provides a method for preparing an FCBGA packaged core board, the method comprising:

[0062] S1: Provide a glass substrate, wherein the glass substrate is one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass and quartz glass, and its coefficient of thermal expansion is between 1ppm / ℃ and 10ppm / ℃, including the endpoint value, and its thermal conductivity is between 1W / m·K and 5W / m·K, including the endpoint value, and perform heat treatment on the glass substrate to relieve stress on the glass substrate.

[0063] S2: Form interconnecting holes through the glass substrate;

[0064] S3: Form a metal seed layer covering the opposite sides of the glass substrate and the surface of the interconnect hole;

[0065] S4: Form a metal interconnect layer covering the metal seed layer, and the metal interconnect layer fills the interconnect holes;

[0066] S5: Pattern the metal interconnect layer and the metal seed layer until the surface of the glass substrate is exposed to form an FCBGA package core board.

[0067] The FCBGA packaging substrate prepared using the method described in this embodiment has advantages such as good dimensional stability, small warpage, good thermal conductivity, high strength, high wiring density, high reliability, short process, short production cycle, and low manufacturing cost. It is suitable for high-end chip packaging and heterogeneous integrated packaging. Specifically, this embodiment uses a glass substrate as the core layer of the packaging substrate. Glass is a material with high dimensional stability, exhibiting the following characteristics: 1. A very low coefficient of thermal expansion, especially the glass used in this embodiment with a coefficient of thermal expansion between 1ppm / ℃ and 10ppm / ℃, which is very close to the coefficient of thermal expansion of components (2ppm / ℃ to 4ppm / ℃); 2. A dimensional humidity coefficient of "0", unaffected by humidity; 3. Glass also has a very high glass transition temperature (Tg approximately 800℃), allowing for stable operation over a wide operating range. Therefore, the FCBGA packaging substrate prepared using glass has advantages such as good dimensional stability, small warpage, and high reliability. Secondly, the glass substrate in this embodiment is one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass, and quartz glass, which has good thermal conductivity, with a thermal conductivity coefficient between 1 W / m·K and 5 W / m·K, thereby improving the overall thermal conductivity of the subsequently formed FCBGA packaging substrate. Furthermore, the glass substrate in this embodiment undergoes a heat treatment process before encapsulation lamination. This involves heating the glass to above its glass transition temperature, holding it at that temperature, and then rapidly cooling it to "temper" it. Next, it is held at a constant temperature in a furnace at a much lower temperature than the tempering temperature for a certain period, and finally cooled to achieve stress relief and "homogenization." This stress-relief heat treatment effectively improves the glass's bending strength and impact resistance, ultimately enhancing the impact resistance of the FCBGA packaging substrate and achieving a strength improvement effect. Fourth, traditional FCBGA packaging substrates use copper-clad laminates (CCLs) as the core board. CCLs have a three-layer structure: two sides are copper foil, and the middle layer is a composite of organic materials and glass fibers. The glass fibers are interwoven, resulting in visible interwoven textures on the copper surface when using CCLs as the core board. This high surface roughness limits the fabrication of overlays and circuits on CCLs to relatively large linewidths / spacings. Fabricating finer circuits can lead to large areas of flying wires. In contrast, this embodiment uses a glass substrate as the core board. Because glass has very low roughness, the root of the seed layer (i.e., surface roughness) formed by subsequent processes such as sputtering, evaporation, and chemical plating is relatively small, making subsequent laser ablation easier. Therefore, finer circuits can be fabricated on the core board than with traditional CCLs. Furthermore, because the glass substrate is very flat, overlay structures can also achieve finer circuits and improve yield.Finally, the traditional core board production process for FCBGA packaging substrates involves approximately 14 steps, including core board cutting, mechanical drilling, desmearing, chemical copper plating, electroplating, resin plugging, grinding, desmearing, chemical copper plating, electroplating, film lamination, exposure, development, and etching. In contrast, the core board production process for FCBGA packaging substrates in this embodiment only requires about 5 steps. Compared to the traditional process, the preparation method in this embodiment has a shorter process, shorter production cycle, and lower manufacturing cost.

[0068] The preparation method of the FCBGA package core board of this embodiment will be described in detail below with reference to the accompanying drawings.

[0069] like Figure 1 As shown, step S1 is performed first, providing a glass substrate 101. The glass substrate 101 is one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass, and quartz glass, with a coefficient of thermal expansion between 1ppm / ℃ and 10ppm / ℃ and a thermal conductivity between 1W / m·K and 5W / m·K. The glass substrate 101 is then heat-treated to relieve stress.

[0070] It should be noted that in this embodiment, the data between ... includes endpoint values, for example, between 1ppm / ℃ and 10ppm / ℃, including 1ppm / ℃ and 10ppm / ℃.

[0071] As an example, the coefficient of thermal expansion of the glass substrate 101 is between 1 ppm / ℃ and 10 ppm / ℃, for example, it can be 2 ppm / ℃, 4 ppm / ℃, 6 ppm / ℃, 8 ppm / ℃, etc. The thermal conductivity of the glass substrate 101 is between 1 W / m·K and 5 W / m·K, for example, it can be 2 W / m·K, 3 W / m·K, 4 W / m·K, etc.

[0072] As an example, the advantage of the glass substrate 101 is that its thickness meets the commonly used core board thickness requirements, and can even be thinner, generally between 0.03mm and 3mm, including endpoint values, such as 0.05mm, 0.1mm, 1mm, 2mm, 3mm, etc.

[0073] As a preferred example, the doping amount of the dopant in the glass substrate 101 is between 8% and 12% by weight, including the endpoints. In this embodiment, the preferred weight percentage is 10%.

[0074] As an example, the heat treatment process for the glass substrate 101 is as follows: first, the glass is heated to above the glass transition temperature; after heat preservation, it is "tempered" by rapid cooling; then, it is kept at a constant temperature in a furnace at a temperature much lower than the tempering temperature for a certain period of time; finally, it is cooled to achieve the effect of stress relief and "homogenization".

[0075] like Figure 2 As shown, step S2 is then performed to form an interconnection hole 102 that penetrates the glass substrate 101.

[0076] As an example, the method for forming the interconnect hole 102 is not limited, and can include laser-induced etching, electrochemical etching, laser ablation, plasma etching, focused discharge etching, photosensitive glass etching, sandblasting, etc. In this embodiment, laser-induced etching is preferably used to form the interconnect hole 102, and the cross-sectional shape of the formed interconnect hole 102 is as follows. Figure 2 Type X in the text.

[0077] like Figure 3 As shown, step S3 is then performed to form a metal seed layer 103 covering both opposite sides of the glass substrate 101 and the surface of the interconnect hole 102. That is, the metal seed layer 103 covers the entire surface of the structure.

[0078] As an example, the method for forming the metal seed layer 103 is not limited; for example, it can be sputtering, vapor deposition, or electroless plating. The material of the metal seed layer 103 can be titanium.

[0079] like Figure 5 As shown, step S4 is then performed to form a metal interconnect layer 104 covering the metal seed layer 103, and the metal interconnect layer 104 fills the interconnect hole 102.

[0080] As an example, the method for forming the metal interconnect layer 104 is not limited; for example, it can be sputtering, vapor deposition, electroless plating, or electroplating. In this embodiment, electroplating is preferably used to form the metal interconnect layer 104, specifically as follows: Figure 4 As shown, firstly, a first metal interconnect layer 105 is flash-plated (using a DC electroplating process) onto the surface of the metal seed layer 103; as... Figure 5 As shown, then, using an AC electroplating process, a second metal interconnect layer 106 is formed on the surface of the first metal interconnect layer 105, filling the interconnect holes 102, thereby forming the metal interconnect layer 104.

[0081] As an example, the material of the metal interconnect layer 104 can be copper.

[0082] like Figure 6As shown, step S5 is performed to pattern the metal interconnect layer 104 and the metal seed layer 103 until the surface of the glass substrate 101 is exposed to form the FCBGA package core board 100.

[0083] As a specific example, the method of graphically representing the metal interconnect layer 104 and the metal seed layer 103 includes forming a dry film, exposure, development, forming an etching window, then etching the metal interconnect layer 104 and the metal seed layer 103, and finally removing the dry film to form the package core board 100. The size and layout of the formed etching window are selected according to the specific circuit requirements, and no excessive restrictions are imposed here.

[0084] As a preferred example, laser etching is used to etch the metal interconnect layer 104 and the metal seed layer 103. Since the substrate is made of glass, which has very low roughness, the resulting metal seed layer 103 has a relatively small root. Therefore, laser etching of the metal seed layer is simple to operate and is a dry-mode process, resulting in higher alignment accuracy and the ability to fabricate finer circuits on the core board. In this embodiment, the laser used for laser etching is preferably a carbon dioxide laser, a green laser, a UV laser, or an excimer laser, with laser pulses at the nanosecond, picosecond, or femtosecond level.

[0085] Based on the above-described method for fabricating the FCBGA package core board 100, this embodiment also provides a method for fabricating an FCBGA package substrate. The method for fabricating this FCBGA package substrate will be described below with reference to the accompanying drawings.

[0086] like Figure 6 As shown, step S1 is performed first, providing a package core board 100 prepared by the FCBGA package core board preparation method described above.

[0087] like Figure 7 As shown, step S2 is then performed, using a pressing method to form a dielectric layer 201 on two opposite sides of the encapsulation core board 100, and patterning it to form a blind via 202 penetrating the dielectric layer 201.

[0088] As an example, the dielectric layer 201 may be an insulating dielectric material with photosensitivity and a thermal decomposition temperature of 340 degrees or higher. In this embodiment, the dielectric layer 201 is a photosensitive material with a dielectric loss coefficient of less than 3.5 and a dielectric constant of less than 4.0. However, the type of dielectric layer 201 is not limited to this and can be selected according to specific needs. No excessive restrictions are imposed here.

[0089] As an example, the pressing method can be employed, such as vacuum pressing, to form the dielectric layer 201 with good adhesion on both sides of the encapsulation core board 100. The thickness of the dielectric layer 201 is not excessively limited here.

[0090] like Figure 8 As shown, step S3 is then performed, in which a patterned circuit connection layer 203 electrically connected to the encapsulation core board 100 is formed based on the blind via 202.

[0091] As an example, the circuit connection layer 203 includes a seed layer and a metal layer. The seed layer may include a copper seed layer formed by chemical plating or a titanium / copper seed stack formed by sputtering, whichever is selected as needed. Then, a photosensitive layer is prepared on the seed layer, and the photosensitive layer is exposed and developed. Next, the metal layer is electroplated to form the circuit. Finally, the photosensitive layer and the corresponding seed layer are removed to obtain the final circuit connection layer 203. The photosensitive layer can be a dry film or a wet film. The coating method for the dry film photosensitive layer is lamination or vacuum lamination, and the coating method for the wet film photosensitive layer is spin coating, spray coating, blade coating, or roll-to-roll coating. The thickness of the photosensitive layer is between 1 μm and 100 μm, including the endpoint values.

[0092] like Figure 9 As shown, step S3 is then performed, repeating the steps for dielectric layer 201 and circuit connection layer 203 until the required number of stacked layers is completed to form the FCBGA package substrate. Figure 9 Three circuit connection layers 203 are formed on both sides of the FCBGA package core board 100. This is just an example. In practice, the number of circuit connection layers 203 can be set according to actual needs, and no excessive restrictions are imposed here.

[0093] As an example, such as Figure 10 As shown, after forming the required number of laminated layers, the process further includes: sequentially preparing a solder resist layer 204 and a surface treatment layer 205 on the surface of the resulting structure, and preparing solder balls (not shown in the figure) in the desired area of ​​the surface treatment layer 205. The solder balls can be formed using screen-printed solder paste or micro-hole solder ball placement. The surface treatment layer 205 is fabricated using electroless nickel-palladium alloy (ESP), and its function is to protect the circuit connection layer 203, prevent its oxidation, and maintain the solderability of the circuit connection layer 203.

[0094] Based on the above-described method for fabricating an FCBGA package core board, this embodiment also provides an FCBGA package core board, such as... Figure 6 As shown, the encapsulation core board includes: a glass substrate 101, a patterned metal seed layer 103, and a patterned metal interconnect layer 104.

[0095] The glass substrate 101 is one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass, and quartz glass, with a coefficient of thermal expansion between 1ppm / ℃ and 10ppm / ℃, including the endpoint value, and a thermal conductivity between 1W / m·K and 5W / m·K, including the endpoint value. The glass substrate is subjected to heat treatment to relieve stress on the glass substrate.

[0096] The glass substrate 101 is provided with interconnecting holes 102 that penetrate the glass substrate 101;

[0097] The metal seed layer 103 covers the opposite sides of the glass substrate 101 and the surface of the interconnect hole 102;

[0098] The metal interconnect layer 104 covers the surface of the metal seed layer 103 and fills the interconnect holes 102.

[0099] Based on the above-described method for fabricating an FCBGA package substrate, this embodiment also provides an FCBGA package substrate, such as... Figure 10 As shown, the packaging substrate includes: the packaging core board 100 as described above and at least one stacked layer; wherein,

[0100] The stack includes a dielectric layer 201 and a wiring layer 203. A blind via 202 is formed in the dielectric layer 201, and the wiring layer 203 fills the blind via 202 and extends to a portion of the surface of the dielectric layer 201.

[0101] The circuit connection layer 203 of the stacked board is connected to the metal interconnect layer 104 of the encapsulation core board 100.

[0102] The following is a specific example of fabricating an FCBGA package substrate:

[0103] (1) Provide a glass substrate, which is a high-strength glass with high toughness, low coefficient of thermal expansion and good thermal conductivity. Aluminum oxide (Al2O3) is added to the glass, the thermal conductivity of the glass is 4W / m·K, the thickness of the glass substrate is 0.2mm, and the glass substrate is heat-treated.

[0104] (2) The interconnecting holes of the glass substrate are fabricated on the glass substrate using a UV picosecond laser machine. The holes are fabricated on both sides, and the shape of the holes is similar to an X-shape with a diameter of 75 μm.

[0105] (3) Deposit titanium and copper metal as metal seed layers on the substrate on which the interconnect hole has been fabricated by double-sided evaporation, wherein the thickness of titanium metal is 200 nm and the thickness of copper metal is 600 nm.

[0106] (4) Based on the above-mentioned packaging substrate for making the metal seed layer, the metal layer is thickened by electroplating copper to form a reliable interconnect metal interconnect layer.

[0107] (5) Laser ablation is performed on the reliable interconnected metal interconnect layer and metal seed layer using an excimer laser. The line width of the laser ablation is 10 μm and the spacing between the lines is 10 μm to form the packaging core board.

[0108] (6) After completing the pre-processing of the circuit on the glass encapsulation core board, a dielectric layer is attached. The dielectric layer is an ABF film with a thickness of 40μm. Laser drilling is performed on the ABF with a hole diameter of 50μm. Descaling and chemical copper processes are performed, and a photosensitive layer with a thickness of 25μm is laminated. Electroplating, film removal, and flash etching are performed to form the circuit connection layer. The preparation process of the circuit connection layer is repeated until the required number of layers is reached.

[0109] (7) After the circuit connection layer is completed, the solder mask layer and surface treatment layer are fabricated. Solder balls of 70μm are formed in the required areas by micro-hole placement. At this point, the fabrication process of all FCBGA package substrates is completed.

[0110] In summary, this invention provides an FCBGA packaging core board, a packaging substrate, and a method for preparing the same. The FCBGA packaging substrate prepared using the method of this invention exhibits advantages such as good dimensional stability, low warpage, good thermal conductivity, high strength, high wiring density, high reliability, short process flow, short production cycle, and low manufacturing cost. It is suitable for high-end chip packaging and heterogeneous integrated packaging. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing an FCBGA package core board, characterized in that, The preparation method includes: A glass substrate is provided, wherein the glass substrate is one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass, and quartz glass, and its coefficient of thermal expansion is between 1ppm / ℃ and 10ppm / ℃, including the endpoints, and its thermal conductivity is between 1W / m•K and 5W / m•K, including the endpoints. The glass substrate is subjected to heat treatment to relieve stress. The heat treatment process is as follows: first, the glass substrate is heated to above the glass transition temperature, held at that temperature, and then tempered with rapid cooling air. Next, it is held at a constant temperature furnace below the tempering temperature, and finally cooled to achieve the effect of stress relief and homogenization. Interconnecting holes are formed through the glass substrate; A metal seed layer is formed covering the opposite sides of the glass substrate and the surface of the interconnect hole; A metal interconnect layer is formed covering the metal seed layer, and the metal interconnect layer fills the interconnect holes; The metal interconnect layer and the metal seed layer are patterned until the surface of the glass substrate is exposed to form an FCBGA package core board.

2. The method for preparing the FCBGA package core board according to claim 1, characterized in that: The thickness of the glass substrate is between 0.03 mm and 3 mm, including the endpoint values.

3. The method for preparing the FCBGA package core board according to claim 1, characterized in that: The weight percentage of dopants in the glass substrate is between 8% and 12%, including the endpoint values.

4. The method for preparing the FCBGA package core board according to claim 1, characterized in that: The interconnect holes are formed using a laser-induced etching method.

5. The method for preparing the FCBGA package core board according to claim 1, characterized in that: The metal interconnect layer and the metal seed layer are patterned using laser etching.

6. The method for preparing the FCBGA package core board according to claim 5, characterized in that: The laser used for laser etching is a carbon dioxide laser, a green laser, a UV laser, or an excimer laser, and the laser pulse is at the nanosecond, picosecond, or femtosecond level.

7. The method for preparing the FCBGA package core board according to claim 1, characterized in that, The method for forming the metal interconnect layer includes: firstly, forming a first metal sub-interconnect layer covering the metal seed layer using a DC electroplating process; and then forming a second metal sub-interconnect layer covering the first metal sub-interconnect layer using an AC electroplating process, wherein the second metal sub-interconnect layer fills the interconnect via.

8. A method for fabricating an FCBGA packaging substrate, characterized in that, The preparation method includes: A packaging core board prepared by the preparation method according to any one of claims 1 to 7 is provided; A dielectric layer is formed on both opposite sides of the encapsulation core board using a pressing method; The dielectric layer is patterned to form blind vias penetrating the dielectric layer; Based on the blind vias, a patterned circuit connection layer is formed that is electrically connected to the encapsulation core board; Repeat the steps of the dielectric layer and the circuit connection layer until the required number of stacked layers are completed to form the FCBGA package substrate.

9. The method for preparing the FCBGA packaging substrate according to claim 8, characterized in that, After forming the required number of laminate layers, the process further includes: sequentially preparing a solder resist layer and a surface treatment layer on the surface of the resulting structure, and preparing solder balls in the required area of ​​the surface treatment layer.

10. An FCBGA packaged core board, characterized in that, The encapsulation core board is prepared using the preparation method described in any one of claims 1 to 7, and includes: a glass substrate, a patterned metal seed layer, and a patterned metal interconnect layer; wherein... The glass substrate is one of alkali-free glass, alkaline glass, alumina glass, borosilicate glass, and quartz glass, with a coefficient of thermal expansion between 1 ppm / ℃ and 10 ppm / ℃, including the endpoints, and a thermal conductivity between 1 W / m•K and 5 W / m•K, including the endpoints. The glass substrate is subjected to heat treatment to relieve stress. The heat treatment process is as follows: first, the glass substrate is heated to above the glass transition temperature, held at that temperature, and then tempered with rapid cooling air. Next, it is held at a constant temperature furnace below the tempering temperature, and finally cooled to achieve the effect of stress relief and homogenization. The glass substrate is provided with interconnecting holes that penetrate the glass substrate; The metal seed layer covers the opposite sides of the glass substrate and the surface of the interconnect hole; The metal interconnect layer covers the surface of the metal seed layer and fills the interconnect holes.

11. An FCBGA packaging substrate, characterized in that, The packaging substrate includes: the FCBGA packaging core board as described in claim 10 and at least one stacked layer; wherein... The stack includes a dielectric layer and a wiring connection layer. A blind via is formed in the dielectric layer, and the wiring connection layer fills the blind via and extends to a portion of the surface of the dielectric layer. The circuit connection layer of the stacked board is connected to the metal interconnect layer of the encapsulation core board.

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