Method of forming a bump

Abstract

The application discloses a bump forming method, comprising the following steps: providing a substrate, an upper surface of the substrate is formed with a pad and a passivation layer, the pad is exposed outward from a passivation layer opening on the passivation layer; generating a metal layer on the surface of the passivation layer and the pad; forming a photoresist layer on the surface of the metal layer through photoresist; an exposure and development process, the photoresist layer is formed into a windowed area corresponding to a bump growth area, and the photoresist layer is formed with a photoresist groove corresponding to a non-bump growth area. The non-bump growth area is formed with the photoresist groove, the internal stress of the photoresist is reduced, the possibility of a gap between the photoresist and the metal layer is slowed down, and the plating phenomenon is effectively avoided when the bump is electroplated.

Description

Technical Field

[0001] This invention relates to the field of wafer-level packaging technology, and more particularly to a method for forming bumps. Background Technology

[0002] Advanced IC chip packaging mainly refers to packaging technologies such as flip chip, wafer-level packaging, 2.5D packaging (interposer, RDL, etc.), and 3D packaging (TSV). Bumps, as a key component of advanced packaging, are a prominent example of high-end advanced packaging technology. The extremely fine bump pitch and high pin density requirements place higher demands on the bumps' heat dissipation capabilities, electrical performance, and reliability.

[0003] Currently, photolithography combined with electroplating deposition is the most common method for wafer bump fabrication. However, this type of electroplated bump structure often suffers from underplating abnormalities during manufacturing, affecting its conductivity in subsequent applications. Summary of the Invention

[0004] One of the objectives of this invention is to provide a method for forming bumps to solve the technical problem of abnormal plating in the prior art.

[0005] To achieve one of the above-mentioned objectives, an embodiment of the present invention provides a method for forming bumps, comprising the following steps: providing a substrate, wherein pads and a passivation layer are formed on the upper surface of the substrate, the pads being exposed outward from an opening in the passivation layer; forming a metal layer on the surface of the passivation layer and the pads; forming a photoresist layer on the surface of the metal layer using photoresist; performing an exposure and development process, wherein the photoresist layer forms a windowed area corresponding to the bump growth area, and a plurality of photoresist grooves are formed on the photoresist layer corresponding to the non-bump growth area; forming the bump in the windowed area; and removing the photoresist layer outside the windowed area.

[0006] As a further improvement of one embodiment of the present invention, the exposure and development process includes a first exposure process performed through a first mask, the first mask including an effective pattern and an invalid pattern adjacent to the effective pattern; after the first exposure process, the photoresist layer forms an effective region corresponding to the effective pattern and an invalid region corresponding to the invalid pattern.

[0007] As a further improvement of one embodiment of the present invention, the invalid pattern is an intermittent and / or continuous straight line and / or curve, and the spacing between the valid pattern and the invalid pattern is 2~100um.

[0008] As a further improvement of one embodiment of the present invention, the exposure and development process includes a development process, wherein the effective area of ​​the photoresist layer is developed into a windowed area, and the ineffective area is developed into a photoresist groove.

[0009] As a further improvement of one embodiment of the present invention, the line width of the invalid pattern is thinner than that of the valid pattern, and the line width of the invalid pattern is set to be selected according to the selected photoresist to ensure that the invalid area is not developed in the development process and forms a photoresist groove.

[0010] As a further improvement of one embodiment of the present invention, when using THB-121N photoresist, the linewidth of the invalid pattern is set to less than 5 μm.

[0011] As a further improvement of one embodiment of the present invention, the molding method further includes a second exposure process after the first exposure process and before the development process. The second exposure process is replaced by a second mask. The second mask corresponds to the light-transmitting area of ​​the invalid pattern of the first mask. At the same time, the light energy of the second exposure process is reduced to ensure that the invalid area is not developed in the development process and forms a photoresist groove.

[0012] As a further improvement of one embodiment of the present invention, the invalid pattern does not limit the line width.

[0013] As a further improvement of one embodiment of the present invention, in the first exposure process, the effective pattern and the invalid pattern of the first mask are light-blocking areas; in the second exposure process, the area of ​​the second mask corresponding to the effective pattern of the first mask is still a light-blocking area, ensuring that the effective area can be dissolved and revealed.

[0014] As a further improvement of one embodiment of the present invention, the windowed area exposes the metal layer, the photoresist groove covers the metal layer, and the photoresist groove is located in the photoresist layer outside the windowed area.

[0015] As a further improvement of one embodiment of the present invention, the bump includes a first electroplating layer, a second electroplating layer and a third electroplating layer, wherein the thickness of the first electroplating layer ranges from 3 to 70 μm, the thickness of the second electroplating layer ranges from 1 to 5 μm, and the thickness of the third electroplating layer ranges from 0.5 to 40 μm.

[0016] Compared with the prior art, the present invention provides a method for forming bumps, wherein a window area is formed in the photoresist layer in the bump growth area, and a photoresist groove is formed in the photoresist layer in the non-bump growth area, which reduces the internal stress of the photoresist, reduces the possibility of gaps between the photoresist and the metal layer, and effectively avoids plating penetration during the electroplating of bumps. Attached Figure Description

[0017] Figure 1-8 This is a process diagram of a bump forming method according to an embodiment of the present invention.

[0018] Figure 9-10 This is a process diagram of different exposure and development processes in another embodiment of the present invention. Detailed Implementation

[0019] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0020] The terms used herein, such as “above,” “over,” “below,” and “under,” indicating spatial relative position, are for illustrative purposes to describe the relationship of one unit or feature relative to another unit or feature as shown in the accompanying drawings. These terms may be intended to include different orientations of the device in use or operation other than those shown in the figures. For example, if the device in the figures is flipped, a unit described as being “below” or “under” another unit or feature would be “above” that unit or feature. Therefore, the exemplary term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially related descriptive terms used herein will be interpreted accordingly.

[0021] Please see Figure 1-8 This is a method for forming the protrusion 70 provided in an embodiment of the present invention.

[0022] like Figure 1 As shown, a substrate 10 is provided, and a pad 20 and a passivation layer 30 are formed on the upper surface of the substrate 10. The pad 20 is exposed outward from the passivation layer opening 31 on the passivation layer 30.

[0023] Specifically, the substrate 10 is the wafer body (also known as a chip or silicon wafer). The pad 20 is a metal layer on the surface of the wafer, and the material of the pad 20 includes, but is not limited to, metal alloys such as aluminum, copper, and gold; in a preferred embodiment, the pad 20 is preferably an aluminum pad.

[0024] The passivation layer 30 is a protective layer for the wafer surface, and its material includes, but is not limited to, inorganic thin film materials such as silicon nitride and silicon oxide, or photosensitive organic polymer materials with good dielectric properties such as polyimide. The passivation layer 30 is used to block the electrical conduction between the upper metal layer on the wafer surface and the wafer surface (containing silicon material), and can also be called an insulating layer.

[0025] like Figure 2As shown, optionally, the surface of the passivation layer 30 is covered with a dielectric layer 40, and the pads 20 are exposed through the openings 41 of the dielectric layer 40. In other embodiments, the dielectric layer 40 may be omitted, and only the passivation layer 30 may be retained. In other embodiments, the passivation layer 30 and the dielectric layer 40 may also be considered as two passivation layers 30 or two dielectric layers 40.

[0026] The dielectric layer 40 provides a certain degree of buffering and protection for the passivation layer 30, and together with the passivation layer 30, it isolates the electrical conductivity between the upper metal layer on the wafer surface and the wafer surface (containing silicon). The dielectric layer 40 is made of inorganic thin film materials such as silicon nitride and silicon oxide, or photosensitive organic polymer materials with good dielectric properties such as polyimide. The dielectric layer 40 and the passivation layer 30 can also be referred to as an insulating layer.

[0027] Preferably, a metal layer 50 is formed on the surface of the passivation layer 30 and the pad 20.

[0028] like Figure 3 As shown, specifically, the metal layer 50 is formed by sputtering, including a lower barrier layer and an upper seed layer. That is, the barrier layer covers the surface of the passivation layer 30 and the pad 20. The barrier layer material includes, but is not limited to, titanium, titanium-tungsten, and other titanium metal alloys or compounds. The seed layer material is copper, gold, or other metals, preferably copper. The barrier layer can prevent metal diffusion to the wafer and can improve the adhesion strength of the metal on the wafer surface. The bump 70 is usually formed by electroplating copper. Electroplating requires conductivity, so a copper seed layer is covered on the surface of the barrier layer to conduct electricity. After energizing, copper ions in the electroplating solution combine with electrons to form copper plated on the surface of the seed layer. The copper seed layer can provide copper nuclei. The more nuclei, the more uniform the crystallization, avoiding abnormal grain growth that could lead to bump abnormalities.

[0029] Preferably, a photoresist layer 60 is formed on the surface of the metal layer 50 using photoresist. For example... Figure 4 As shown, a photoresist layer 60 is formed by coating photoresist or applying a film.

[0030] Preferably, in the exposure and development process, the photoresist layer 60 forms a windowed region 61 corresponding to the bump growth area, and the photoresist layer 60 forms multiple photoresist grooves 62 corresponding to the non-bump growth area. For example... Figure 5-6As shown, the bump growth region 601 is the area where bumps 70 will be formed subsequently, while the non-bump growth region 603 is the area where bumps 70 will not be formed. The photoresist groove 62 is formed in the non-bump growth region 603 and does not affect the normal electroplating of bumps 70. The photoresist groove 62 is adjacent to the window region 61, reducing the internal stress of the photoresist and mitigating the possibility of gaps between the photoresist and the metal layer, effectively preventing plating penetration during the electroplating of bumps 70. The photoresist groove 62 also resists thermal expansion during subsequent baking processes, preventing deformation of the photoresist and thus avoiding abnormal shape of the bumps 70.

[0031] Preferably, the protrusion 70 is formed in the window area 61. (See reference...) Figure 7 As shown in the specific embodiment, the bump 70 is formed sequentially by electroplating a first electroplated layer 71, and / or a second electroplated layer 72, and / or a third electroplated layer 73. Typically, the first electroplated layer 71 is the bump itself, mainly serving an electrical conduction function, while the second electroplated layer 72 and the third electroplated layer 73 can be selectively formed.

[0032] The first electroplated layer 71 is generally made of copper, gold, etc., preferably copper, and its thickness is generally 3~70um; the second electroplated layer 72 is a bump metal barrier layer, mainly used to block the interdiffusion behavior between the third electroplated layer 73 and the metal of the first electroplated layer 71, and its material is generally nickel, with a thickness of 1~5um; the third electroplated layer 73 is the surface metal of the bump 70, and its material is generally gold, tin, tin-silver, etc., with a thickness of 0.5~40um. The specific thickness can be determined according to customer needs and is not limited here.

[0033] Preferably, the photoresist layer 60 outside the windowed area 61 is removed. This can be done by dry etching or wet etching.

[0034] Preferably, the seed layer 50 is removed. This can be done by dry or wet etching. (See reference...) Figure 8 As shown, the protrusion 70 has been formed.

[0035] Preferably, the exposure and development process includes a first exposure process performed through a first mask 80, the first mask 80 including an effective pattern 81 and an invalid pattern 82 adjacent to the effective pattern; after the first exposure process, the photoresist layer 60 forms an effective region 601 corresponding to the effective pattern and an invalid region 602 corresponding to the invalid pattern.

[0036] Preferably, the invalid pattern is an intermittent and / or continuous straight line and / or curve, and the spacing between the valid pattern and the invalid pattern is 2~100um.

[0037] Preferably, the exposure and development process includes a development process, wherein the effective area 601 of the photoresist layer is developed into a windowed area 61, and the ineffective area 602 is developed into a photoresist groove 62.

[0038] Specifically, such as Figure 5-6 As shown, the effective area 601 in the exposure process corresponds to the bump growth area and also to the windowed area 61 after development, while the ineffective area 602 is located in the non-bump growth area 603.

[0039] Preferably, the windowed area 61 exposes the metal layer 50, the photoresist groove 62 covers the metal layer 50, and the photoresist groove 62 is located in the photoresist layer outside the windowed area 61.

[0040] Specifically, this application uses negative photoresist. The unexposed portion of the negative photoresist dissolves in the developer to form a window, while the photoexposed portion remains on the substrate surface after development to form a photoresist layer. Therefore, the effective and ineffective patterns in this application are light-shielding areas, blocking light during the exposure process to facilitate subsequent dissolution, while other areas are light-transmitting areas, receiving light to form the photoresist layer 60.

[0041] Specifically, the photoresist groove 62 includes two formation methods. The first formation method:

[0042] Preferably, the line width of the invalid pattern 82 is thinner than that of the valid pattern 81. The line width of the invalid pattern 82 is set according to the selected photoresist to ensure that the invalid area 602 is not developed during the development process and forms a photoresist groove 62.

[0043] Preferably, when using THB-121N photoresist, the linewidth of the invalid pattern is set to less than 5µm.

[0044] It is understandable that when the invalid pattern 82 on the first mask 80 is too fine, it has less light-blocking effect, causing the photoresist in the invalid area to be partially exposed to light. Therefore, during development, the developer dissolves some of the photoresist, which cannot be fully developed, leaving only the development mark, i.e., the photoresist groove 62.

[0045] Different photoresists have different photosensitivity, so the line width of the invalid pattern 82 of the first mask 80 needs to be determined according to the different photoresists. The selected line width can be used to partially dissolve the photoresist to form grooves.

[0046] The second formation method: Preferably, the forming method further includes a second exposure process after the first exposure process and before the developing process. In the second exposure process, the second mask 90 is replaced. The area corresponding to the invalid pattern 82 of the first mask 80 on the second mask 90 is a light-transmitting area. At the same time, the light energy of the second exposure process is reduced to ensure that the invalid area is not developed in the developing process and a photoresist groove is formed.

[0047] Preferably, the line width of the invalid pattern 82 is not limited.

[0048] Preferably, in the first exposure process, the effective pattern 81 and the invalid pattern 82 of the first mask 80 are light-shielding areas; in the second exposure process, the area corresponding to the effective pattern of the first mask on the second mask 90 is still a light-shielding area, ensuring that the effective area can be dissolved and developed.

[0049] It can be understood that if the line width of the invalid pattern 82 is not limited, it will cover the photoresist, making the photoresist not sensitive to light and being dissolved by the developer to form a window, rather than a photoresist groove 62. Therefore, under the condition of not limiting the line width, a second exposure process is added after the first exposure process in this application.

[0050] See Figure 9-10 As shown, specifically, in the first exposure process, except for the areas corresponding to the effective pattern 81 and the invalid pattern 82, the photoresist in other places is exposed to light and will form a photoresist layer after development; while the effective areas 601 and the invalid areas 602 of the photoresist corresponding to the effective pattern 81 and the invalid pattern 82 are not exposed to light.

[0051] In the second exposure process, the first mask 80 is replaced. The light-shielding area corresponding to the original invalid pattern 82 on the second mask 90 is changed to a light-transmitting area, and other places remain unchanged. That is, only the effective pattern 91 is set as the light-shielding area on the second mask 90, and other places are all light-transmitting areas and receive light. It can be understood that if the light energy is the same as that in the first exposure process, the invalid area 602 will be exposed in the same way and will form a photoresist after development. Therefore, this application reduces the energy in the second exposure process, making the photoresist in the invalid area 602 not fully sensitive to light (i.e., partially sensitive). When receiving development again, the developer partially dissolves the photoresist, leaving only a development mark, that is, a photoresist groove 62.

[0052] It can be understood that in other embodiments, the photoresist groove 62 can also be realized by more exposure and development methods.

[0053] It can be formed corresponding to any of the technical solutions provided above, and will not be elaborated here.

[0054] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0055] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for forming a bump, characterized in that, Includes the following steps: A substrate is provided, wherein pads and a passivation layer are formed on the upper surface of the substrate, and the pads are exposed outward from the passivation layer openings on the passivation layer; A metal layer is formed on the surface of the passivation layer and the pads; A photoresist layer is formed on the surface of the metal layer using photoresist; In the exposure and development process, the photoresist layer forms a windowed area corresponding to the bump growth area, and the photoresist layer forms multiple photoresist grooves corresponding to the non-bump growth area. The bump is generated in the window area; Remove the photoresist layer outside the windowed area; The exposure and development process includes a first exposure process through a first mask, the first mask including an effective pattern and an invalid pattern adjacent to the effective pattern; After the first exposure process, the photoresist layer forms an effective area corresponding to the effective pattern and an invalid area corresponding to the invalid pattern; The invalid pattern is an intermittent and / or continuous straight line and / or curve, and the spacing between the valid pattern and the invalid pattern is 2~100um; The exposure and development process includes a development process, wherein the effective area of ​​the photoresist layer is developed into a windowed area, and the ineffective area is developed into a photoresist groove.

2. The molding method according to claim 1, characterized in that, The invalid pattern has a line width that is thinner than the valid pattern. The line width of the invalid pattern is set according to the selected photoresist to ensure that the invalid area is not developed during the development process and forms a photoresist groove.

3. The molding method according to claim 2, characterized in that, When using THB-121N photoresist, the linewidth of invalid patterns should be set to below 5µm.

4. The molding method according to claim 1, characterized in that, The forming method also includes a second exposure process after the first exposure process and before the development process. The second exposure process is replaced by a second mask. The second mask corresponds to the light-transmitting area of ​​the invalid pattern of the first mask. At the same time, the light energy of the second exposure process is reduced to ensure that the invalid area is not developed in the development process and forms a photoresist groove.

5. The molding method according to claim 4, characterized in that, The invalid pattern does not have a line width limitation.

6. The molding method according to claim 5, characterized in that, In the first exposure process, the effective and invalid patterns of the first mask are light-blocking areas; in the second exposure process, the area of ​​the second mask corresponding to the effective pattern of the first mask is still a light-blocking area, ensuring that the effective area can be dissolved and revealed.

7. The molding method according to claim 1, characterized in that, The windowed area exposes the metal layer, the photoresist groove covers the metal layer, and the photoresist groove is located on a photoresist layer outside the windowed area.

8. The molding method according to claim 1, characterized in that, The bump includes a first electroplated layer, a second electroplated layer and a third electroplated layer, wherein the thickness of the first electroplated layer ranges from 3 to 70 μm, the thickness of the second electroplated layer ranges from 1 to 5 μm, and the thickness of the third electroplated layer ranges from 0.5 to 40 μm.

Images