A method of forming a semiconductor device

Abstract

The application provides a semiconductor device forming method, which comprises the following steps: forming a first shallow trench isolation structure in a semiconductor substrate of a first region, forming a second shallow trench isolation structure in a second region, the upper surface of the first shallow trench isolation structure and the upper surface of the second shallow trench isolation structure are flush, and both are located above the surface of the semiconductor substrate, the final height of the second shallow trench isolation structure in the second region can be improved, so that the final height is not lower than that of the ACT region, and the risk of failure of a low-voltage device semiconductor device is avoided; the height of the first shallow trench isolation structure is reduced through a special etching process, so that there is no problem of residual polysilicon around the first shallow trench isolation structure when a gate is formed in the first region in the subsequent process, and the problem of abnormal semiconductor device does not occur, the step does not increase the mask, that is, the process cost is basically not increased, and the final height of the first shallow trench isolation structure in the high-voltage region and the final height of the second shallow trench isolation structure in the low-voltage region are balanced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing processes, and particularly to a method for forming a semiconductor device. Background Technology

[0002] With the current 0.11μm logic process, it is compatible with both low-voltage 1.5V MOS devices and high-voltage 7V / 9V MOS devices. The gate oxide thickness of the 1.5V MOS device is, for example, approximately... The gate oxide thickness of a 7V MOSFET device is, for example, approximately The gate oxide thickness of a 9V MOSFET device is, for example, approximately This means that after forming thick gate oxide in both the high-voltage region (i.e., the region forming the high-voltage MOSFET device) and the low-voltage region (i.e., the region forming the low-voltage MOSFET device), removing the thick gate oxide in the low-voltage region requires prolonged HF pickling. This results in a significant reduction in the height of the STI (Shallow Trench Isolation Structure) 2 in the low-voltage region, and the height of the STI 2 in the low-voltage region is significantly lower than the height of the ACT (Active Region) 1, for example, the height difference is... A severe divot defect exists at the interface between the active region and the shallow trench isolation structure, resulting in poor morphology of the cobalt-silicon compound during subsequent formation. Furthermore, the divot defect causes a reverse narrow width effect, increasing the risk of semiconductor device failure. Additionally, the STI height in the high-voltage region is significantly higher than the ACT height. For example, the height difference is... During the gate formation process in the high-voltage region, polysilicon residue may appear on the periphery of the STI in the high-voltage region, which also poses a risk of semiconductor device failure. Summary of the Invention

[0003] The purpose of this invention is to provide a method for forming a semiconductor device that can reduce the risk of semiconductor device failure caused by excessively high height of the first region STI and excessively low height of the second region STI.

[0004] To address the above problems, the present invention provides a method for forming a semiconductor device, comprising the following steps:

[0005] Step S1: Provide a semiconductor substrate, the semiconductor substrate including a first region and a second region;

[0006] Step S2: A first shallow trench isolation structure is formed in the semiconductor substrate in the first region, and a second shallow trench isolation structure is formed in the second region, wherein the upper surfaces of the first shallow trench isolation structure and the upper surfaces of the second shallow trench isolation structure are flush and both are located above the surface of the semiconductor substrate.

[0007] Step S3: A patterned first photoresist layer is formed on the semiconductor substrate, exposing the semiconductor substrate in the first region. The height of the first shallow trench isolation structure is reduced through an etching process, such that the upper surface of the first shallow trench isolation structure is located between the upper surface of the second shallow trench isolation structure and the surface of the semiconductor substrate; and

[0008] Step S4: Remove the first photoresist layer, and sequentially form a first gate oxide and a patterned second photoresist layer on the semiconductor substrate surface of the first region, and use the patterned second photoresist layer as a mask to etch the first gate oxide of the second region, and remove the second photoresist layer.

[0009] Optionally, in step S1, a sacrificial layer and a silicon nitride layer are sequentially formed on the semiconductor substrate.

[0010] Furthermore, step S2 includes:

[0011] A first shallow trench is formed in the semiconductor substrate of the first region, and a second shallow trench is formed in the semiconductor substrate of the second region, wherein the trench depth of the first shallow trench and the trench depth of the second shallow trench are the same.

[0012] The first shallow trench and the second shallow trench are filled with oxide, which covers the silicon nitride layer in the first region outside the first shallow trench and the silicon nitride layer in the second region outside the second shallow trench.

[0013] The oxides in the first and second shallow trenches are planarized by CMP process, and CMP is stopped on the silicon nitride layer to form a first shallow trench isolation structure and a second shallow trench isolation structure. The upper surfaces of the first and second shallow trench isolation structures are flush and both are located above the surface of the sacrificial layer.

[0014] Remove the silicon nitride layer.

[0015] Furthermore, the height difference between the upper surface of the first shallow trench isolation structure and the surface of the semiconductor substrate is...

[0016] Furthermore, step S3 includes:

[0017] A patterned first photoresist layer is formed on the sacrificial layer, the patterned first photoresist layer having a first opening in the first region, the first opening exposing the sacrificial layer in the first region;

[0018] At the first opening, using the patterned first photoresist layer as a mask, an ion implantation process is performed to form a high-voltage trap in the semiconductor substrate of the first region; and

[0019] At the first opening, using the patterned first photoresist layer as a mask, the sacrificial layer in the first region is removed by wet etching, while simultaneously reducing the height of the first shallow trench isolation structure.

[0020] Furthermore, the wet etching process is carried out at room temperature using a hydrofluoric acid solution, wherein the solubility ratio of HF to H2O in the hydrofluoric acid solution is 1:20, 1:50, or 1:100.

[0021] Furthermore, the etching height of the first shallow trench isolation structure is

[0022] Furthermore, step S4 includes:

[0023] Remove the first photoresist layer and sacrificial layer located in the second region;

[0024] The first gate oxide is formed on the semiconductor substrate by a dry oxide method;

[0025] A patterned second photoresist layer is formed on the first gate oxide, the patterned second photoresist layer having a second opening in the second region, the second opening exposing the first gate oxide and the second shallow trench isolation structure in the second region;

[0026] At the second opening, using the patterned second photoresist layer as a mask, a wet etching process is employed to remove the first gate oxide in the second region and expose the semiconductor substrate. Simultaneously, the etching reduces the height of the second shallow trench isolation structure.

[0027] The second photoresist layer in the first region is removed, and a second gate oxide is formed on the semiconductor substrate in the second region by a dry oxide method.

[0028] Furthermore, the thickness of the first gate oxide is The thickness of the second gate oxide is

[0029] Optionally, the materials of the first gate oxide, the first shallow trench isolation structure, and the second shallow trench isolation structure are all silicon dioxide.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] This invention provides a method for forming a semiconductor device. By forming a first shallow trench isolation structure in a semiconductor substrate in a first region and a second shallow trench isolation structure in a second region, the upper surfaces of the first and second shallow trench isolation structures are flush and both located above the surface of the semiconductor substrate. This method increases the final height of the second shallow trench isolation structure in the low-voltage region (i.e., the second region), ensuring that its final height is not lower than the ACT region, thus avoiding the risk of low-voltage device failure. Furthermore, by using a specialized etching process to reduce the height of the first shallow trench isolation structure, residual polysilicon is avoided around the periphery of the first shallow trench isolation structure when forming the gate in the high-voltage region (first region), preventing semiconductor device malfunctions. This step does not require an additional photomask, thus minimally increasing process costs, and balances the final height of the first shallow trench isolation structure in the high-voltage region and the final height of the second shallow trench isolation structure in the low-voltage region. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the measured STI height in the low-pressure area and the STI height in the ACT in the existing technology;

[0033] Figure 2 This is a schematic flowchart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0034] Figures 3-5 This is a schematic diagram of the structure of each step in a method for forming a semiconductor device according to an embodiment of the present invention.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1-ACT; 2-STI; I-First region; II-Second region; 10-Semiconductor substrate; 11-Sacrificial layer; 12-First shallow trench isolation structure; 13-Second shallow trench isolation structure; 21-First photoresist layer; 22-Second photoresist layer; 30-First gate oxide layer. Detailed Implementation

[0037] The following will provide a more detailed description of a method for forming a semiconductor device according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0038] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0039] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0040] Figure 2 This is a schematic flowchart illustrating a method for forming a semiconductor device according to this embodiment. Figure 2 As shown, this embodiment provides a method for forming a semiconductor device, including the following steps:

[0041] Step S1: Provide a semiconductor substrate, the semiconductor substrate including a first region and a second region;

[0042] Step S2: A first shallow trench isolation structure is formed in the semiconductor substrate in the first region, and a second shallow trench isolation structure is formed in the second region, wherein the upper surfaces of the first shallow trench isolation structure and the upper surfaces of the second shallow trench isolation structure are flush and both are located above the surface of the semiconductor substrate.

[0043] Step S3: A patterned first photoresist layer is formed on the semiconductor substrate, exposing the semiconductor substrate in the first region. The height of the first shallow trench isolation structure is reduced through an etching process, such that the upper surface of the first shallow trench isolation structure is located between the upper surface of the second shallow trench isolation structure and the surface of the semiconductor substrate; and

[0044] Step S4: Remove the first photoresist layer, and sequentially form a first gate oxide and a patterned second photoresist layer on the semiconductor substrate surface of the first region, and use the patterned second photoresist layer as a mask to etch the first gate oxide of the second region, and remove the second photoresist layer.

[0045] The following combination Figures 3-5 A method for forming a semiconductor device provided in this embodiment will be described in detail.

[0046] like Figure 3As shown, step S1 is first performed to provide a semiconductor substrate 10, which includes a first region I and a second region II.

[0047] This step specifically includes:

[0048] First, a semiconductor substrate 10 is provided, comprising adjacent logic regions and ACT (active region) regions (not shown in the figure). The logic regions include an adjacent first region I and a second region II. The first region I is a high-voltage element region for forming a high-voltage MOS device, and the second region II is a low-voltage element region for forming a low-voltage MOS device. The high voltage is, for example, 7V or 9V, and the low voltage is, for example, 1.5V.

[0049] The semiconductor substrate 10 can provide an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components. It can be a bare die or a wafer processed by epitaxial growth process. In this embodiment, the semiconductor substrate 10 is, for example, a silicon substrate.

[0050] Next, a sacrificial layer 11 and a silicon nitride layer (not shown) are sequentially formed on the semiconductor substrate 10. The sacrificial layer 11 is used to protect the semiconductor substrate 10 during subsequent processing. The sacrificial layer 11 is made of silicon oxide, and its thickness is [not specified in the original text]. The silicon nitride layer is used as a stop layer for subsequent CMP processes.

[0051] Next, step S2 is performed, in which a first shallow trench isolation structure 12 is formed in the semiconductor substrate 10 of the first region I, and a second shallow trench isolation structure 13 is formed in the second region II, wherein the upper surface of the first shallow trench isolation structure 12 and the upper surface of the second shallow trench isolation structure 13 are flush and both are located above the surface of the semiconductor substrate 10.

[0052] This step specifically includes:

[0053] First, a first shallow trench is formed in the semiconductor substrate 10 of the first region I, and a second shallow trench is formed in the semiconductor substrate 10 of the second region II, wherein the trench depth of the first shallow trench and the trench depth of the second shallow trench are the same.

[0054] Next, oxides (e.g., silicon dioxide) are filled into the first and second shallow trenches, the oxides covering the silicon nitride layer in the first region I outside the first shallow trench and the silicon nitride layer in the second region II outside the second shallow trench.

[0055] Next, the oxides in the first and second shallow trenches are planarized by CMP process, and CMP is stopped on the silicon nitride layer to form the first shallow trench isolation structure 12 and the second shallow trench isolation structure 13. The upper surfaces of the first shallow trench isolation structure 12 and the second shallow trench isolation structure 13 are flush and both are located above the surface of the sacrificial layer 11.

[0056] Wherein, the height difference between the upper surface of the first shallow trench isolation structure 12 and the surface of the semiconductor substrate 10 is In other words, the height difference between the upper surface of the second shallow trench isolation structure 13 and the surface of the semiconductor substrate 10 is also... Compared to existing technologies, this embodiment increases the height of the first shallow trench isolation structure 12 and the second shallow trench isolation structure 13 after the CMP process (for example, by increasing the height by [missing information]). This increases the height of the second shallow trench isolation structure 13 during the subsequent removal of the first gate oxide in the second region II, and facilitates obtaining the first shallow trench isolation structure 12 and the second shallow trench isolation structure 13 with essentially flush heights after the subsequent removal of the first gate oxide in the second region II, thereby increasing the final height of the second shallow trench isolation structure 13.

[0057] Next, the silicon nitride layer is removed by thermal phosphoric acid, wherein the heights of the first shallow trench isolation structure 12 and the second shallow trench isolation structure 13 both depend on the grinding amount of the CMP process.

[0058] like Figure 4 As shown, step S3 is then performed, in which a patterned first photoresist layer 21 is formed on the semiconductor substrate 10. The patterned first photoresist layer 21 exposes the semiconductor substrate 10 of the first region I, and the height of the first shallow trench isolation structure 12 is reduced by an etching process, such that the upper surface of the first shallow trench isolation structure 12 is located above the upper surface of the second shallow trench isolation structure 13 and the surface of the semiconductor substrate 10.

[0059] This step specifically includes the following steps:

[0060] First, a patterned first photoresist layer 21 is formed on the sacrificial layer 11. The patterned first photoresist layer 21 has a first opening in the first region I, and the first opening exposes the sacrificial layer 11 in the first region I.

[0061] Next, at the first opening, using the patterned first photoresist layer 21 as a mask, an ion implantation process is performed to form a high-voltage trap in the semiconductor substrate 10 of the first region I. When the first region I is used to form an NMOS device, the ion implantation process implants P-type ions; when the first region I is used to form a PMOS device, the ion implantation process implants N-type ions.

[0062] Next, at the first opening, using the patterned first photoresist layer 21 as a mask, a wet etching process is used to remove the sacrificial layer 11 of the first region I. Simultaneously, the height of the first shallow trench isolation structure 12 is reduced to minimize the height difference between the upper surface of the first shallow trench isolation structure 12 and the semiconductor substrate 10. This prevents excessive etching of the second shallow trench isolation structure 13 in the second region II during subsequent etching of the first gate oxide, which could result in a significant height difference between the shallow trench isolation structures in the low-voltage and high-voltage regions. Compared to existing technologies, this embodiment adds a wet etching process to remove the sacrificial layer 11 of the first region I and simultaneously reduces the height of the first shallow trench isolation structure 12. This allows the height of the first shallow trench isolation structure 12 to be reduced earlier, solving the problem of polysilicon residue appearing around the first shallow trench isolation structure 12 during subsequent gate formation in the first region I, thereby preventing semiconductor device malfunctions.

[0063] In this step, the etching height of the first shallow trench isolation structure 12 is Compared with the prior art, this step reduces the height of the first shallow trench isolation structure 12 in advance, which is beneficial to obtaining the first shallow trench isolation structure 12 and the second shallow trench isolation structure 13 with the same height in the subsequent process.

[0064] The wet etching in this step is performed at room temperature (e.g., around 23°C) using a hydrofluoric acid solution, wherein the solubility ratio of HF to H2O in the hydrofluoric acid solution is 1:20, 1:50, or 1:100. Those skilled in the art will know that a higher solubility ratio of HF to H2O in the hydrofluoric acid solution results in a longer wet etching process. Furthermore, because the selectivity between silicon oxide and silicon etching is relatively high in this step, the damage to the semiconductor substrate 10 caused by the wet etching process is minimal and negligible.

[0065] like Figure 5As shown, step S4 is then performed to remove the first photoresist layer 21, and to sequentially form a first gate oxide 30 and a patterned second photoresist layer 22 on the surface of the semiconductor substrate 10 in the first region I. Using the patterned second photoresist layer 22 as a mask, the first gate oxide 30 is etched to balance the heights of the first shallow trench isolation structure 12 and the second shallow trench isolation structure 13, and the second photoresist layer 22 is removed.

[0066] This step specifically includes the following steps:

[0067] First, the first photoresist layer 21 and sacrificial layer 11 located in the second region II are removed.

[0068] Next, a high-quality first gate oxide 30 is formed on the semiconductor substrate 10 using a dry oxygen method (i.e., a direct high-temperature thermal reaction between O2 and Si). The first gate oxide 30 covers only the semiconductor substrate 10 in the second region II and the semiconductor substrate 10 in the first region I. The thickness of the first gate oxide 30 is... The first gate oxide 30 is made of silicon dioxide.

[0069] Next, a patterned second photoresist layer 22 is formed on the first gate oxide 30. The patterned second photoresist layer 22 has a second opening in the second region II, and the second opening exposes the first gate oxide 30 and the second shallow trench isolation structure 13 in the second region II.

[0070] Next, at the second opening, using the patterned second photoresist layer 22 as a mask, the first gate oxide 30 of the second region II is removed by a wet etching process, exposing the semiconductor substrate 10. Since the first gate oxide 30 and the second shallow trench isolation structure 13 are made of the same material, the second shallow trench isolation structure 13 is etched simultaneously with the etching of the first gate oxide 30, thereby reducing the height of the second shallow trench isolation structure 13. This balances the heights of the first shallow trench isolation structure 12 and the second shallow trench isolation structure 13, ultimately resulting in a first shallow trench isolation structure 12 and a second shallow trench isolation structure 13 with consistent heights. There is no phenomenon of the first shallow trench isolation structure 12 being too high or the second shallow trench isolation structure 13 being too low. Since the height of the second shallow trench 13 increases after CMP, the height of the second shallow trench 13 after removing the first gate oxide 30 in this step is increased, ensuring that it is not lower than the ACT region of the semiconductor device, thus avoiding the risk of low-voltage device failure.

[0071] Next, the second photoresist layer 22 in the first region I is removed, and a second gate oxide (not shown in the figure) is formed on the semiconductor substrate 10 in the second region II using a dry oxide method. The thickness of the second gate oxide is...

[0072] In summary, this invention provides a method for forming a semiconductor device. By forming a first shallow trench isolation structure in a semiconductor substrate in a first region and a second shallow trench isolation structure in a second region, the upper surfaces of the first and second shallow trench isolation structures are flush and both located above the surface of the semiconductor substrate. This method can increase the final height of the second shallow trench isolation structure in the low-voltage region (i.e., the second region), ensuring that it is not lower than the ACT region, thus avoiding the risk of low-voltage device failure. By using a specialized etching process to reduce the height of the first shallow trench isolation structure, residual polysilicon will not appear on the periphery of the first shallow trench isolation structure when forming the gate in the high-voltage region (first region), thereby preventing semiconductor device malfunctions. Furthermore, this step does not require an additional photomask, meaning there is virtually no increase in process cost. This method balances the final height of the first shallow trench isolation structure in the high-voltage region and the final height of the second shallow trench isolation structure in the low-voltage region.

[0073] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0074] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that, Includes the following steps: Step S1: Provide a semiconductor substrate, the semiconductor substrate including a first region and a second region; Step S2: A first shallow trench isolation structure is formed in the semiconductor substrate in the first region, and a second shallow trench isolation structure is formed in the second region, wherein the upper surfaces of the first shallow trench isolation structure and the upper surfaces of the second shallow trench isolation structure are flush and both are located above the surface of the semiconductor substrate. Step S3: A patterned first photoresist layer is formed on the semiconductor substrate, exposing the semiconductor substrate in the first region. The height of the first shallow trench isolation structure is reduced through an etching process, such that the upper surface of the first shallow trench isolation structure is located between the upper surface of the second shallow trench isolation structure and the surface of the semiconductor substrate; and Step S4: Remove the first photoresist layer, and sequentially form a first gate oxide and a patterned second photoresist layer on the semiconductor substrate surface of the first region, and use the patterned second photoresist layer as a mask to etch the first gate oxide of the second region, and remove the second photoresist layer.

2. The method for forming a semiconductor device as described in claim 1, characterized in that, In step S1, a sacrificial layer and a silicon nitride layer are sequentially formed on the semiconductor substrate.

3. The method for forming a semiconductor device as described in claim 2, characterized in that, Step S2 includes: A first shallow trench is formed in the semiconductor substrate of the first region, and a second shallow trench is formed in the semiconductor substrate of the second region, wherein the trench depth of the first shallow trench and the trench depth of the second shallow trench are the same. The first shallow trench and the second shallow trench are filled with oxide, which covers the silicon nitride layer in the first region outside the first shallow trench and the silicon nitride layer in the second region outside the second shallow trench. The oxides in the first and second shallow trenches are planarized by CMP process, and CMP is stopped on the silicon nitride layer to form a first shallow trench isolation structure and a second shallow trench isolation structure. The upper surfaces of the first and second shallow trench isolation structures are flush and both are located above the surface of the sacrificial layer. Remove the silicon nitride layer.

4. The method for forming a semiconductor device as described in claim 3, characterized in that, The height difference between the upper surface of the first shallow trench isolation structure and the surface of the semiconductor substrate is 5. The method for forming a semiconductor device as described in claim 2, characterized in that, Step S3 includes: A patterned first photoresist layer is formed on the sacrificial layer, the patterned first photoresist layer having a first opening in the first region, the first opening exposing the sacrificial layer in the first region; At the first opening, using the patterned first photoresist layer as a mask, an ion implantation process is performed to form a high-voltage trap in the semiconductor substrate of the first region; and At the first opening, using the patterned first photoresist layer as a mask, the sacrificial layer in the first region is removed by wet etching, while simultaneously reducing the height of the first shallow trench isolation structure.

6. The method for forming a semiconductor device as described in claim 5, characterized in that, The wet etching process is carried out at room temperature using a hydrofluoric acid solution, wherein the solubility ratio of HF to H2O in the hydrofluoric acid solution is 1:20, 1:50, or 1:

100.

7. The method for forming a semiconductor device as described in claim 5, characterized in that, The etching height of the first shallow trench isolation structure is 8. The method for forming a semiconductor device as described in claim 2, characterized in that, Step S4 includes: Remove the first photoresist layer and sacrificial layer located in the second region; The first gate oxide is formed on the semiconductor substrate by a dry oxide method; A patterned second photoresist layer is formed on the first gate oxide, the patterned second photoresist layer having a second opening in the second region, the second opening exposing the first gate oxide and the second shallow trench isolation structure in the second region; At the second opening, using the patterned second photoresist layer as a mask, a wet etching process is employed to remove the first gate oxide in the second region and expose the semiconductor substrate. Simultaneously, the etching reduces the height of the second shallow trench isolation structure. The second photoresist layer in the first region is removed, and a second gate oxide is formed on the semiconductor substrate in the second region by a dry oxide method.

9. The method for forming a semiconductor device as described in claim 8, characterized in that, The thickness of the first gate oxide is The thickness of the second gate oxide is 10. The method for forming a semiconductor device as claimed in claim 1, characterized in that, The first gate oxide, the first shallow trench isolation structure, and the second shallow trench isolation structure are all made of silicon dioxide.

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