HEMT devices and their fabrication methods

Abstract

This application provides a HEMT device and its fabrication method, relating to the field of circuit technology. The HEMT device includes a substrate layer, a buffer layer, a first channel layer, a second channel layer, a barrier layer, and a semiconductor layer. The second channel layer and the barrier layer form a fin-shaped NMOS semiconductor structure extending along the length direction of the first channel layer. The semiconductor layer includes a first PMOS semiconductor layer and a second PMOS semiconductor layer formed on the surface of the first channel layer. The first and second PMOS semiconductor layers are respectively disposed on both sides of the fin-shaped NMOS semiconductor structure. The technical solution provided in this application can improve the output current of the PMOS device.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a HEMT device and its fabrication method. Background Technology

[0002] High Electron Mobility Transistors (HEMTs) possess excellent properties such as high breakdown voltage, low on-resistance, high switching speed, and high energy conversion efficiency; CMOS offers advantages such as high integration density and low power consumption. Integrating HEMTs and CMOS on the same substrate can significantly improve the overall performance of the device. Therefore, HEMT devices monolithically integrated with CMOS (also known as complementary HEMTs) are increasingly widely used in electric vehicles, power grids, and power electronics.

[0003] Complementary HEMT devices include both P-channel metal-oxide-semiconductor (PMOS) and N-channel metal-oxide-semiconductor (NMOS), with the PMOS and NMOS formed on the same substrate.

[0004] Because PMOS has a high ionization energy for p-type impurities and a low hole concentration, its hole mobility is relatively low, resulting in a lower output current. Summary of the Invention

[0005] In view of this, embodiments of this application provide a HEMT device and its fabrication method, which can increase the two-dimensional hole gas concentration of a PMOS device, thereby increasing the output current of the PMOS.

[0006] To achieve the above objectives, in a first aspect, embodiments of this application provide a HEMT device, comprising: a substrate layer, a buffer layer, a first channel layer, a second channel layer, a barrier layer and a semiconductor layer, a first gate dielectric layer, a first gate electrode, a first source electrode, a first drain electrode, a second gate dielectric layer, a second gate electrode, a second source electrode, a second drain electrode, a third gate dielectric layer, a third gate electrode, a third source electrode and a third drain electrode;

[0007] The substrate layer, the buffer layer, the first channel layer, the second channel layer, and the barrier layer are stacked from bottom to top; wherein, the second channel layer and the barrier layer form a fin-shaped NMOS semiconductor structure extending along the length direction of the first channel layer;

[0008] The semiconductor layer includes: a first PMOS semiconductor layer and a second PMOS semiconductor layer formed on the surface of the first channel layer; the first PMOS semiconductor layer and the second PMOS semiconductor layer are respectively disposed on both sides of the fin-shaped NMOS semiconductor structure;

[0009] The first gate dielectric layer is located in the middle of the Fin strip structure of the fin-shaped NMOS semiconductor structure, and forms a groove structure with the bottom embedded in the barrier layer;

[0010] The first gate electrode is located on the first gate dielectric layer; the first source electrode and the first drain electrode are located between the second channel layer and the barrier layer, and are respectively disposed at both ends of the fin-shaped NMOS semiconductor structure;

[0011] The second gate dielectric layer is located in the middle of the first PMOS semiconductor layer and forms a groove structure with its bottom embedded in the first channel layer; the second gate electrode is located on the second gate dielectric layer; the second source electrode and the second drain electrode are located between the buffer layer and the first channel layer and are respectively disposed at both ends of the first PMOS semiconductor layer;

[0012] The third gate dielectric layer is located in the middle of the second PMOS semiconductor layer and forms a groove structure with its bottom embedded in the first channel layer; the third gate electrode is located on the third gate dielectric layer; the third source electrode and the third drain electrode are located between the buffer layer and the first channel layer and are respectively disposed at both ends of the second PMOS semiconductor layer.

[0013] As an optional implementation of this application, the semiconductor layer is a P-type semiconductor layer.

[0014] As an optional implementation of this application, the P-type semiconductor layer includes a first semiconductor layer and a second semiconductor layer stacked from bottom to top.

[0015] As an optional implementation of this application, the doping concentration of the second semiconductor layer is higher than that of the first semiconductor layer.

[0016] As an optional implementation of this application, both the first channel layer and the second channel layer are unintentionally doped nitride layers.

[0017] As an optional implementation of this application, the barrier layer is generated from an aluminum-containing nitride.

[0018] As an optional implementation of this application, the first drain electrode, the second drain electrode, and the third drain electrode are all located on one side of the first gate electrode, and the first source electrode, the second source electrode, and the third source electrode are all located on the other side of the first gate electrode.

[0019] As an optional implementation of this application, the first gate electrode extends downward to cover the two sidewalls of the fin-type NMOS semiconductor structure and is connected to the second gate electrode and the third gate electrode.

[0020] As an optional implementation of this application, the materials of the first source electrode, the first drain electrode, the first gate electrode, the second source electrode, the second gate electrode, the second drain electrode, the third source electrode, the third gate electrode, and the third drain electrode all include one or more of titanium, aluminum, nickel, gold, and tantalum.

[0021] Secondly, embodiments of this application provide a method for fabricating a HEMT device, used to fabricate the HEMT device as described in the first aspect above, the method comprising:

[0022] A buffer layer, a first channel layer, a second channel layer, and a barrier layer are sequentially grown on the surface of the substrate.

[0023] The barrier layer and part of the second channel layer are etched to form a fin-shaped NMOS semiconductor structure and a first PMOS semiconductor layer and a second PMOS semiconductor layer located on both sides of the fin-shaped NMOS semiconductor structure.

[0024] The middle part of the barrier layer is etched to form a first gate groove structure with the bottom embedded in the barrier layer; the middle parts of the first PMOS semiconductor layer and the second PMOS semiconductor layer are etched to form a second gate groove structure and a third gate groove structure with the bottom embedded in the first channel layer, respectively.

[0025] Ion implantation is performed on the first PMOS semiconductor layer and the second PMOS semiconductor layer to form a semiconductor layer with the target doping concentration;

[0026] An insulating dielectric is deposited on the first gate trench structure, the second gate trench structure and the third gate trench structure to form a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer, respectively.

[0027] A metal layer is deposited to form a first source electrode, a second source electrode, a third source electrode, a first drain electrode, a second drain electrode, a third drain electrode, a first gate electrode, a second gate electrode, and a third gate electrode.

[0028] The technical solution provided in this application involves a fin-shaped NMOS semiconductor structure formed by the second channel layer and barrier layer of a HEMT device extending along the length of the first channel layer. The semiconductor layer includes a first PMOS semiconductor layer and a second PMOS semiconductor layer formed on the surface of the first channel layer. The first and second PMOS semiconductor layers are respectively disposed on both sides of the fin-shaped NMOS semiconductor structure. In this solution, both sides of the fin-shaped NMOS semiconductor structure have PMOS semiconductor structures, thereby increasing the two-dimensional hole concentration of the PMOS device and thus improving the output current of the PMOS device. Furthermore, the first and second PMOS semiconductor layers, through the buffer layer and the first channel layer, can achieve through-conduction of two-dimensional hole gas below the fin-shaped NMOS semiconductor structure, thereby reducing the device size and consequently reducing the on-resistance of the HEMT device. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of a HEMT device provided in an embodiment of this application;

[0030] Figure 2 Examples of this application Figure 1 A cross-sectional view of a HEMT device along the BB direction;

[0031] Figure 3 Examples of this application Figure 1 A cross-sectional view of a HEMT device along the CC direction;

[0032] Figure 4A This application provides a schematic diagram of the structure of a HEMT device during manufacturing.

[0033] Figure 4B This is a schematic cross-sectional view of a HEMT device along the AA direction during the manufacturing of a HEMT device according to an embodiment of this application;

[0034] Figure 5A This application provides a schematic diagram of the structure of a HEMT device during manufacturing.

[0035] Figure 5B This is a schematic cross-sectional view of a HEMT device along the AA direction during the manufacturing of a HEMT device according to an embodiment of this application;

[0036] Figure 6A This application provides a schematic diagram of the structure of a HEMT device during manufacturing.

[0037] Figure 6B This is a schematic cross-sectional view of the HEMT device along the BB direction during the manufacturing of a HEMT device according to an embodiment of this application;

[0038] Figure 6C This is a schematic cross-sectional view of a HEMT device along the CC direction during the manufacturing of a HEMT device according to an embodiment of this application;

[0039] Figure 7A This application provides a schematic diagram of the structure of a HEMT device during manufacturing.

[0040] Figure 7B This is a schematic cross-sectional view of the HEMT device along the BB direction during the manufacturing of a HEMT device according to an embodiment of this application;

[0041] Figure 7C This is a schematic cross-sectional view of a HEMT device along the CC direction during the manufacturing of a HEMT device according to an embodiment of this application;

[0042] Figure 8A This application provides a schematic diagram of the structure of a HEMT device during manufacturing.

[0043] Figure 8B This is a schematic cross-sectional view of the HEMT device along the BB direction during the manufacturing of a HEMT device according to an embodiment of this application;

[0044] Figure 8C This is a schematic cross-sectional view of a HEMT device along the CC direction during the manufacturing of a HEMT device according to an embodiment of this application;

[0045] Figure 9 This application provides a schematic diagram of the structure of a HEMT device during manufacturing.

[0046] Figure 10 This is a schematic diagram of the structure of a HEMT device during the manufacturing process, as provided in an embodiment of this application. Detailed Implementation

[0047] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is for explaining specific embodiments only and is not intended to limit the scope of this application.

[0048] First, the structure of the HEMT device provided in the embodiments of this application will be introduced.

[0049] Figure 1 This is a schematic diagram of the HEMT device provided in the embodiments of this application. Figure 2 yes Figure 1 A cross-sectional view of a HEMT device along the BB direction. Figure 3 yes Figure 1 A schematic cross-sectional view of a HEMT device along the CC direction. (See diagram below.) Figures 1-3As shown, the HEMT device provided in this embodiment may include: a substrate layer 10, a buffer layer 20, a first channel layer 30, a second channel layer 40, a barrier layer 50 and a semiconductor layer 80, a first gate dielectric layer 601, a first gate electrode 701, a first source electrode (not shown), a first drain electrode (not shown), a second gate dielectric layer 602, a second gate electrode 702, a second source electrode (not shown), a second drain electrode (not shown), a third gate dielectric layer 603, a third gate electrode 703, a third source electrode (not shown) and a third drain electrode (not shown).

[0050] The substrate layer 10, buffer layer 20, first channel layer 30, second channel layer 40 and barrier layer 50 are stacked from bottom to top; wherein, the second channel layer 40 and the barrier layer 50 form a fin-shaped NMOS semiconductor structure extending along the length direction of the first channel layer 30.

[0051] The substrate 10 can be formed from materials such as silicon (Si), sapphire, or silicon carbide (SiC); the buffer layer 20 can be formed from aluminum gallium nitride (AlGaN) so that it can easily form a heterojunction with the first channel layer 30; the first channel layer 30 can be formed from undoped GaN to reduce impedance and increase the concentration of two-dimensional hole gas (2DHG).

[0052] In some embodiments, the barrier layer 50 may be formed from an aluminum-containing nitride, such as aluminum gallium nitride (AlGaN) or indium aluminum nitride (InAlN), to better form a heterojunction.

[0053] In some embodiments, aluminum gallium nitride (AlGaN) can be used as the barrier layer 50 to increase the concentration of two-dimensional electron gas (2DEG) generated on the lower surface of the barrier layer 50; the second channel layer 40 can be generated from undoped GaN to reduce impedance and increase the concentration of 2DEG.

[0054] Semiconductor layer 80 can be a p-type semiconductor layer, an n-type semiconductor layer, or an unintentionally doped semiconductor layer; this application does not impose any particular limitation on this. In some embodiments, to improve the migration rates of 2DEG and 2DHG, semiconductor layer 80 is a p-type semiconductor layer.

[0055] Semiconductor layer 80 may include one layer or multiple layers. Figure 1 The example described below uses a semiconductor layer 80, which includes a first semiconductor layer I and a second semiconductor layer II stacked from bottom to top.

[0056] The doping concentration of the second semiconductor layer II may be different from that of the first semiconductor layer I. In some embodiments, the doping concentration of the second semiconductor layer II may be higher than that of the first semiconductor layer I in order to increase the concentration of 2DHG.

[0057] The semiconductor layer 80 includes a first PMOS semiconductor layer 801 and a second PMOS semiconductor layer 802 formed on the surface of the first channel layer 30; the first PMOS semiconductor layer 801 and the second PMOS semiconductor layer 802 are respectively disposed on both sides of the fin-shaped NMOS semiconductor structure.

[0058] Both the first PMOS semiconductor layer 801 and the second PMOS semiconductor layer 802 can be composed of p-type gallium nitride (GaN) / p-type magnesium gallium nitride (MgGaN) / p-type indium gallium nitride (InGaN) / p-type nickel oxide (NiO) / p-type tin oxide (SnO). In order to increase the concentration of 2DEG and 2DHG and make 2DEG and 2DHG have better migration rates, in some embodiments of this application, p-type GaN material is used to form the semiconductor layer 80.

[0059] The first gate dielectric layer 601 is located in the middle of the fin-shaped NMOS semiconductor structure and forms a groove structure embedded in the bottom barrier layer 50.

[0060] The first gate electrode 701 is located on the first gate dielectric layer 601; the first source electrode and the first drain electrode are located between the second channel layer 40 and the barrier layer 50, and are respectively disposed at both ends of the fin-shaped NMOS semiconductor structure.

[0061] The second gate dielectric layer 602 is located in the middle of the first PMOS semiconductor layer 801 and forms a groove structure with its bottom embedded in the first channel layer 30; the second gate electrode 702 is located on the second gate dielectric layer 602; the second source electrode and the second drain electrode are located between the buffer layer 20 and the first channel layer 30 and are respectively disposed at both ends of the first PMOS semiconductor layer 801.

[0062] The third gate dielectric layer 603 is located in the middle of the second PMOS semiconductor layer 802 and forms a groove structure with its bottom embedded in the first channel layer 30; the third gate electrode 703 is located on the third gate dielectric layer 603; the third source electrode and the third drain electrode are located between the buffer layer 20 and the first channel layer 30 and are respectively disposed at both ends of the second PMOS semiconductor layer 802.

[0063] It is understood that the first gate electrode 701, the first source electrode, and the first drain electrode constitute the three electrodes of the fin-type NMOS structure; the second gate electrode 702, the second source electrode, and the second drain electrode constitute the first PMOS structure; and the third gate electrode 703, the third source electrode, and the third drain electrode constitute the second PMOS structure.

[0064] Specifically, the first gate electrode 701 can be spaced apart from the second gate electrode 702 and the third gate electrode 703. In some embodiments, the first gate electrode 701 can also extend downward to cover the two sidewalls of the fin-type NMOS semiconductor structure and connect with the second gate electrode 702 and the third gate electrode 703. This can reduce the connection of metal lines and simplify the manufacturing process.

[0065] In some embodiments, the first drain electrode, the second drain electrode, and the third drain electrode may be distributed on different sides of the first gate electrode 701, and the first source electrode, the second source electrode, and the third source electrode may also be distributed on different sides of the first gate electrode 701.

[0066] In some embodiments, the first drain electrode, the second drain electrode, and the third drain electrode may all be located on one side of the first gate electrode 701; the first source electrode, the second source electrode, and the third source electrode may all be located on the other side of the first gate electrode 701, which facilitates subsequent connection of metal wires and simplifies the manufacturing process.

[0067] The first gate dielectric layer 601, the second gate dielectric layer 602, and the third gate dielectric layer 603 can all be made of insulating materials so that when the HEMT device is working, the voltage at the gate will form an electric field in the channel region, cutting off the current; the first channel layer 30 and the second channel layer 40 can both be unintentionally doped nitride layers; the materials of the first source electrode, the first drain electrode, the first gate electrode 701, the second source electrode, the second drain electrode, the second gate electrode 702, the third source electrode, the third drain electrode, and the third gate electrode 703 can all include one or more of titanium, aluminum, nickel, gold, and tantalum.

[0068] The first source electrode, the first drain electrode, the first gate electrode 701, the second source electrode, the second drain electrode, the second gate electrode 702, the third source electrode, the third drain electrode, and the third gate electrode 703 can be ohmic contacts or Schottky contacts.

[0069] In some embodiments, the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, the third source electrode, and the third drain electrode are all ohmic contacts; the first gate electrode 701, the second gate electrode 702, and the third gate electrode 703 are all Schottky contacts. This approach improves the migration rate of electrons or holes.

[0070] In the aforementioned PMOS and NMOS structures, since there is no P-type semiconductor material below the second gate dielectric layer 602 and the third gate dielectric layer 603, the 2DHG below the second gate dielectric layer 602 and the third gate dielectric layer 603 is almost non-existent. When a negative voltage is applied to the second gate electrode 702 and the third gate electrode 703, due to the field effect, hole conductive channels are formed below the second gate dielectric layer 602 and the third gate dielectric layer 603, and the PMOS is turned on.

[0071] The fin-type NMOS semiconductor structure can form an enhancement-mode HEMT device, in which the NMOS turns on when a positive voltage is applied to the first gate electrode 701.

[0072] The technical solution provided in this application embodiment forms a fin-shaped NMOS semiconductor structure extending along the length direction of the first channel layer in a HEMT device, with the second channel layer and barrier layer forming the structure. The semiconductor layer includes a first PMOS semiconductor layer and a second PMOS semiconductor layer formed on the surface of the first channel layer. The first and second PMOS semiconductor layers are respectively disposed on both sides of the fin-shaped NMOS semiconductor structure. In this solution, both sides of the fin-shaped NMOS semiconductor structure have PMOS semiconductor structures, thereby increasing the two-dimensional hole concentration of the PMOS device and thus improving the output current of the PMOS device. Furthermore, the first and second PMOS semiconductor layers, through the buffer layer and the first channel layer, can achieve through-conduction of two-dimensional hole gas below the fin-shaped NMOS semiconductor structure, thereby reducing the device size and consequently reducing the on-resistance of the HEMT device.

[0073] The fabrication method of the above-mentioned HEMT device is described below.

[0074] Figure 4A This is a schematic diagram of the structure of a HEMT device during the manufacturing process, provided in an embodiment of this application. Figure 4B for Figure 4A A schematic cross-sectional view of a HEMT device along the AA direction. Figures 4A-4B As shown, in fabricating HEMT devices, a buffer layer 20, a first channel layer 30, a second channel layer 40, and a barrier layer 50 can be sequentially grown on the surface of the substrate layer 10 using metal-organic chemical vapor deposition (MOCVD). This allows 2DHG to be formed on the lower surface of the first channel layer 30 and 2DEG to be formed on the upper surface of the second channel layer 40.

[0075] The substrate layer 10 can be made of silicon (Si); the buffer layer 20 can be made of AlGaN; the first channel layer 30 can be made of unintentionally doped GaN; the second channel layer 40 can be made of unintentionally doped GaN; and the barrier layer 50 can be made of AlGaN.

[0076] After the above layers are formed, please refer to Figure 5A and Figure 5B . Figure 5A This application provides a schematic diagram of the structure of a HEMT device during manufacturing. Figure 5B for Figure 5A A schematic cross-sectional view of a HEMT device along the AA direction. Figures 5A-5B As shown, the barrier layer 50 and part of the second channel layer 40 are etched to form a fin-shaped NMOS semiconductor structure and a first PMOS semiconductor layer 801 and a second PMOS semiconductor layer 802 located on both sides of the fin-shaped NMOS semiconductor structure.

[0077] After that, you can refer to Figure 6A , Figure 6B and Figure 6C . Figure 6A This application provides a schematic diagram of the structure of a HEMT device during manufacturing. Figure 6B for Figure 6A A cross-sectional view of a HEMT device along the BB direction; Figure 6C for Figure 6A A schematic cross-sectional view of a HEMT device along the CC direction. (See diagram below.) Figures 6A to 6C As shown, the middle part of the barrier layer 50 is etched to form a first gate groove structure with the bottom embedded in the barrier layer 50; the middle parts of the first PMOS semiconductor layer 801 and the second PMOS semiconductor layer 802 are etched to form a second gate groove structure and a third gate groove structure with the bottom embedded in the first channel layer 30, respectively.

[0078] Then, see Figure 7A , Figure 7B and Figure 7C . Figure 7A This application provides a schematic diagram of the structure of a HEMT device during manufacturing. Figure 7B for Figure 7A A cross-sectional view of a HEMT device along the BB direction; Figure 7C for Figure 7A A schematic cross-sectional view of a HEMT device along the CC direction. (See diagram below.) Figures 7A to 7C As shown, ion implantation is performed on the first PMOS semiconductor layer 801 and the second PMOS semiconductor layer 802 to form a semiconductor layer 80 with the target doping concentration.

[0079] The semiconductor layer 80 may comprise two layers: a first semiconductor layer I and a second semiconductor layer II. Specifically, through ion implantation, the semiconductor layer 80 is p-type GaN, wherein the doping concentration of the second semiconductor layer II is higher than that of the first semiconductor layer I.

[0080] After the semiconductor layer 80 is generated, please refer to Figure 8A , Figure 8B and Figure 8C . Figure 8A This application provides a schematic diagram of the structure of a HEMT device during manufacturing. Figure 8B for Figure 8A A cross-sectional view of a HEMT device along the BB direction; Figure 8C for Figure 8A A schematic cross-sectional view of a HEMT device along the CC direction. (See diagram below.) Figures 8A to 8C As shown, insulating dielectrics can be deposited on the first gate trench structure, the second gate trench structure, and the third gate trench structure using vapor phase epitaxy technology to form the first gate dielectric layer 601, the second gate dielectric layer 602, and the third gate dielectric layer 603, respectively.

[0081] The first gate dielectric layer 601, the second gate dielectric layer 602, and the third gate dielectric layer 603 can all be made of the same insulating material to simplify the fabrication process.

[0082] Then, see Figure 9 , Figure 2 and Figure 3 . Figure 9 This is a schematic diagram of the structure of a HEMT device during the manufacturing process, as provided in an embodiment of this application. Figure 9 As shown, a metal layer is deposited to form a first source electrode, a second source electrode, a third source electrode, a first drain electrode, a second drain electrode, a third drain electrode, a first gate electrode 701, a second gate electrode 702, and a third gate electrode 703.

[0083] In some embodiments, vias can be first made at the contact surfaces of the barrier layer 50 and the second channel layer 40, and the first channel layer 30 and the buffer layer 20, respectively. Then, metal layers are deposited at the locations of the vias and on the first gate dielectric layer 601, the second gate dielectric layer 602, and the third gate dielectric layer 603 to form a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a third source electrode, a third drain electrode, a first gate electrode 701, a second gate electrode 702, and a third gate electrode 703, respectively. The first gate electrode 701 extends downwards to cover the two sidewalls of the fin-type NMOS semiconductor structure and connects to the second gate electrode 702 and the third gate electrode 703.

[0084] In other embodiments, metal layers can be deposited first on the first gate dielectric layer 601, the second gate dielectric layer 602, and the third gate dielectric layer 603 to form the first gate electrode 701, the second gate electrode 702, and the third gate electrode 703, respectively. The first gate electrode 701 extends downward to cover the two sidewalls of the fin-type NMOS semiconductor structure and connects with the second gate electrode 702 and the third gate electrode 703. Then, holes are made at the contact surfaces of the barrier layer 50 and the second channel layer 40, and the first channel layer 30 and the buffer layer 20, respectively, and metal layers are deposited to form the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, the third source electrode, and the third drain electrode, respectively.

[0085] In some embodiments, after the layers are formed, refer to Figure 10 . Figure 10 This is a schematic diagram of the structure of a HEMT device during the manufacturing process, as provided in an embodiment of this application. Figure 10 As shown, device leads can be made by connecting the first drain electrode, the second drain electrode, and the third drain electrode together with a metal wire to form the output terminal Vout of the HEMT device; a metal wire is led onto the first gate electrode 701 to form the input terminal Vin of the HEMT device to receive signals input from the outside; a metal wire is connected to the first source electrode to form the internal input terminal Vdd of the HEMT device, i.e., the internal operating voltage of the HEMT device; and a metal wire is connected to the second and third source electrodes to form the common connection terminal Vss of the HEMT device, which is connected to the ground wire.

[0086] The HEMT device fabrication method provided in this application, wherein the fabricated HEMT device, according to the technical solution provided in this application, forms a fin-shaped NMOS semiconductor structure extending along the length direction of the first channel layer by the second channel layer and the barrier layer. The semiconductor layer includes: a first PMOS semiconductor layer and a second PMOS semiconductor layer formed on the surface of the first channel layer; the first PMOS semiconductor layer and the second PMOS semiconductor layer are respectively disposed on both sides of the fin-shaped NMOS semiconductor structure. In this solution, both sides of the fin-shaped NMOS semiconductor structure have PMOS semiconductor structures, thereby increasing the two-dimensional hole concentration of the PMOS device and thus improving the output current of the PMOS device; moreover, the first PMOS semiconductor layer and the second PMOS semiconductor layer can achieve through-conduction of two-dimensional hole gas under the fin-shaped NMOS semiconductor structure through the buffer layer and the first channel layer, thereby reducing the device size and thus reducing the on-resistance of the HEMT device.

[0087] It should be understood that in the description of this application and the appended claims, the terms "comprising," "including," "having," and any variations thereof are intended to cover non-exclusive inclusion and mean "including but not limited to," unless otherwise specifically emphasized.

[0088] In the description of this application, unless otherwise stated, " / " indicates that the objects before and after are in an "or" relationship. For example, A / B can mean A or B. "And / or" in this application is used to describe the relationship between the related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural.

[0089] Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items.

[0090] Furthermore, it should be understood in the description of this application that the terms "center," "length," "width," "thickness," "longitudinal," "horizontal," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "vertical," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0091] In this application, unless otherwise expressly specified and limited, the terms "installation", "connection", "linking", "fixing", etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Unless otherwise expressly limited, those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0092] Furthermore, in the description of this application and the appended claims, the terms "first," "second," etc., are used to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein; features defined as "first" or "second" may explicitly or implicitly include at least one of those features.

[0093] In the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0094] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A HEMT device, characterized by, include: Substrate layer, buffer layer, first channel layer, second channel layer, barrier layer and semiconductor layer, first gate dielectric layer, first gate electrode, first source electrode, first drain electrode, second gate dielectric layer, second gate electrode, second source electrode, second drain electrode, third gate dielectric layer, third gate electrode, third source electrode and third drain electrode; The substrate layer, the buffer layer, the first channel layer, the second channel layer, and the barrier layer are stacked from bottom to top; wherein, the second channel layer and the barrier layer form a fin-shaped NMOS semiconductor structure extending along the length direction of the first channel layer; The semiconductor layer includes: a first PMOS semiconductor layer and a second PMOS semiconductor layer formed on the surface of the first channel layer; the first PMOS semiconductor layer and the second PMOS semiconductor layer are respectively disposed on both sides of the fin-shaped NMOS semiconductor structure; The first gate dielectric layer is located in the middle of the fin-shaped NMOS semiconductor structure and forms a groove structure with its bottom embedded in the barrier layer; The first gate electrode is located on the first gate dielectric layer; the first source electrode and the first drain electrode are located between the second channel layer and the barrier layer, and are respectively disposed at both ends of the fin-shaped NMOS semiconductor structure; The second gate dielectric layer is located in the middle of the first PMOS semiconductor layer and forms a groove structure with its bottom embedded in the first channel layer; the second gate electrode is located on the second gate dielectric layer; the second source electrode and the second drain electrode are located between the buffer layer and the first channel layer and are respectively disposed at both ends of the first PMOS semiconductor layer; The third gate dielectric layer is located in the middle of the second PMOS semiconductor layer and forms a groove structure with its bottom embedded in the first channel layer; the third gate electrode is located on the third gate dielectric layer; the third source electrode and the third drain electrode are located between the buffer layer and the first channel layer and are respectively disposed at both ends of the second PMOS semiconductor layer.

2. The HEMT device according to claim 1, characterized in that, The semiconductor layer is a P-type semiconductor layer.

3. The HEMT device according to claim 2, characterized in that, The P-type semiconductor layer includes a first semiconductor layer and a second semiconductor layer stacked from bottom to top.

4. The HEMT device according to claim 3, characterized in that, The doping concentration of the second semiconductor layer is higher than that of the first semiconductor layer.

5. The HEMT device according to claim 1, characterized in that, Both the first channel layer and the second channel layer are unintentionally doped nitride layers.

6. The HEMT device according to claim 1, characterized in that, The barrier layer is formed from an aluminum-containing nitride.

7. The HEMT device according to claim 1, characterized in that, The first drain electrode, the second drain electrode, and the third drain electrode are all located on one side of the first gate electrode; the first source electrode, the second source electrode, and the third source electrode are all located on the other side of the first gate electrode.

8. The HEMT device according to claim 1, characterized in that, The first gate electrode extends downward to cover the two sidewalls of the fin-shaped NMOS semiconductor structure and is connected to the second gate electrode and the third gate electrode.

9. The HEMT device according to any one of claims 1-8, characterized in that, The materials of the first source electrode, the first drain electrode, the first gate electrode, the second source electrode, the second gate electrode, the second drain electrode, the third source electrode, the third gate electrode, and the third drain electrode all include one or more of titanium, aluminum, nickel, gold, and tantalum.

10. A method for fabricating a HEMT device, used to fabricate the HEMT device as described in any one of claims 1-9, characterized in that, The method includes: A buffer layer, a first channel layer, a second channel layer, and a barrier layer are sequentially grown on the surface of the substrate. The barrier layer and part of the second channel layer are etched to form a fin-shaped NMOS semiconductor structure and a first PMOS semiconductor layer and a second PMOS semiconductor layer located on both sides of the fin-shaped NMOS semiconductor structure. The middle part of the barrier layer is etched to form a first gate groove structure with the bottom embedded in the barrier layer; the middle parts of the first PMOS semiconductor layer and the second PMOS semiconductor layer are etched to form a second gate groove structure and a third gate groove structure with the bottom embedded in the first channel layer, respectively. Ion implantation is performed on the first PMOS semiconductor layer and the second PMOS semiconductor layer to form a semiconductor layer with the target doping concentration; An insulating dielectric is deposited on the first gate trench structure, the second gate trench structure and the third gate trench structure to form a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer, respectively. A metal layer is deposited to form a first source electrode, a second source electrode, a third source electrode, a first drain electrode, a second drain electrode, a third drain electrode, a first gate electrode, a second gate electrode, and a third gate electrode.

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