SiC top collector region uv phototransistor with integrated temperature sensing unit and method of manufacture

Abstract

The application discloses a SiC top collector area ultraviolet phototransistor integrated with a temperature measuring unit, which comprises an n-type 4H-SiC substrate, an n-type 4H-SiC substrate surface upwardly formed with an n + emitting area, an n + emitting area surface middle position upwardly formed with a p-type base area, a p-type base area surface upwardly sequentially formed with an n-collector area and an n+ collector area, an n+ collector area surface upwardly formed with collector electrode ohmic contact metal and transparent conductive film, collector electrode ohmic contact metal and transparent conductive film being arranged on the n+ collector area surface in an interval mode, and the n+ collector area surface two sides being the collector electrode ohmic contact metal, the collector electrode ohmic contact metal, the n+ collector area, the n-collector area and the p-type base area forming an integral whole, and the application further discloses a preparation method of the SiC top collector area ultraviolet phototransistor integrated with the temperature measuring unit. The application solves the problems of low responsivity and large temperature drift of the SiC ultraviolet phototransistor in the prior art.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a SiC top collector ultraviolet phototransistor with an integrated temperature sensing unit, and also to a method for manufacturing a SiC top collector ultraviolet phototransistor with an integrated temperature sensing unit. Background Technology

[0002] Silicon carbide (SiC) possesses characteristics such as a large bandgap, high thermal conductivity, high critical avalanche breakdown electric field strength, and high carrier saturation drift velocity. Ultraviolet photodetectors made from SiC exhibit advantages such as high temperature resistance, radiation resistance, and strong anti-interference capabilities. SiC ultraviolet phototransistors utilize the current gain principle of bipolar transistors to effectively improve the photoresponse intensity of SiC ultraviolet photoelectric devices. However, traditional SiC ultraviolet phototransistors place the base and collector regions, which primarily bear the light absorption function, at the bottom of the device, significantly affecting the quantum efficiency and limiting the improvement of the photoresponse intensity. This results in a photoresponse intensity that is still lower than theoretically expected. Furthermore, since the current gain of SiC ultraviolet phototransistors directly depends on the emitter junction injection efficiency and base region transport efficiency, SiC ultraviolet phototransistors inherently suffer from large temperature drift. These problems of low photoresponse intensity and large temperature drift have severely limited the widespread application of SiC ultraviolet phototransistors. Summary of the Invention

[0003] The purpose of this invention is to provide a SiC top collector region ultraviolet phototransistor with an integrated temperature sensing unit, which solves the problems of low responsivity and large temperature drift of existing SiC ultraviolet phototransistors.

[0004] Another objective of this invention is to provide a method for fabricating a SiC top collector ultraviolet phototransistor with an integrated temperature sensing unit.

[0005] The first technical solution adopted in this invention is a SiC top-collector ultraviolet phototransistor with an integrated temperature sensing unit, comprising an n-type 4H-SiC substrate, wherein an n-type 4H-SiC substrate has an n-type top-collector region formed on its surface. + Launch area, n + A p-type base region is formed at the center of the emitter region, facing upwards. Above the p-type base region, an n- collector region and an n+ collector region are formed sequentially. Above the n+ collector region, a collector ohmic contact metal and a transparent conductive film are formed. The collector ohmic contact metal and the transparent conductive film are arranged alternately on the surface of the n+ collector region, with collector ohmic contact metal on both sides. The collector ohmic contact metal, the n+ collector region, the n- collector region, and the p-type base region form a single unit. Silicon dioxide dielectric layers are formed on both sides of this unit. +On both sides of the emitter region surface, facing upwards, are also p-type emitter regions. On the surface of each p-type emitter region, a temperature-sensing ohmic contact metal is formed. The upper surface of the temperature-sensing ohmic contact metal is covered with a temperature-sensing PAD metal. A silicon dioxide dielectric layer covers part of the upper surface and the entire side surface of the collector ohmic contact metal. The silicon dioxide dielectric layer also covers the sides of the n+ collector region, n- collector region, and p-type base region, as well as the n-type base region. + The exposed surface of the emitter region, as well as part of the upper surface and the entire side of the p-type emitter region and the ohmic contact metal of the temperature sensing end; the upper surface of the collector ohmic contact metal is covered with collector PAD metal, the lower surface of the n-type 4H-SiC substrate has an emitter ohmic contact metal grown downwards, and the lower surface of the emitter ohmic contact metal is covered with emitter PAD metal.

[0006] The first technical solution of the present invention is further characterized in that,

[0007] The n-type 4H-SiC substrate thickness is 150–350 μm, and the donor impurity concentration is 1.0 × 10⁻⁶. 18 cm -3 ~2.0×10 19 cm -3 ;

[0008] n + The thickness of the upper and lower surfaces of the emission region is 0.5–1.0 μm, and the impurity concentration is 1.0 × 10⁻⁶. 18 cm -3 ~2.0×10 19 cm -3 ;

[0009] The p-type emitter regions are located on either side of the p-type base region, with a lateral spacing of 1.0 μm to 100 μm between them; the width of the p-type emitter region is 10 μm to 1 mm, and the width of the p-type base region is 500 μm to 5 mm; the p-type emitter region and the p-type base region have the same thickness and doping concentration, with a thickness of 0.2 to 1.0 μm and an impurity concentration of 2.0 × 10⁻⁶. 16 cm -3 ~2.0×10 17 cm -3 ;

[0010] The thickness of the n-collector region is 0.5 μm to 10 μm, and the impurity concentration in the n-collector region is 1.0 × 10⁻⁶. 13 cm -3 ~1.0×10 16 cm -3 ;

[0011] The junction depth of the n+ collector region is 0.2 μm to 0.5 μm, and the impurity concentration in the n+ collector region is 1.0 × 10⁻⁶. 18 cm -3~2.0×10 19 cm -3 ;

[0012] The emitter ohmic contact metal is formed from one or more combinations of Ti, Ni, W, and Al, and the thickness of the emitter ohmic contact metal is 100 nm to 300 nm.

[0013] The collector ohmic contact metal is formed from one or more combinations of Ti, Ni, W, and Al, and the thickness of the collector ohmic contact metal is 100 nm to 300 nm.

[0014] The ohmic contact metal at the temperature measuring end is formed by one or more combinations of Ti, Ni, W, and Al, and the thickness of the ohmic contact metal at the temperature measuring end is 100nm to 300nm.

[0015] The thickness of the silicon dioxide dielectric layer is 200nm to 2000nm;

[0016] The emitter PAD metal material is formed by one or more combinations of Ni, Ag, and Au, and the thickness of the emitter PAD metal is 1.0μm to 20μm;

[0017] The temperature sensing PAD metal material is formed by one or more combinations of W, Al, Cu, and Au, and the thickness of the temperature sensing PAD metal is 1.0μm to 10μm;

[0018] The collector PAD metal material is formed by one or more combinations of W, Al, Cu, and Au, and the thickness of the collector PAD metal is 1.0μm to 10μm.

[0019] A transparent conductive film is covered between the collector ohmic contact metals and on the exposed n+ collector region surface. The transparent conductive film is made of one or more of AZO, ITO, and graphene, and has a thickness of 1nm to 1μm.

[0020] The second technical solution adopted in this invention is a method for fabricating a SiC top collector region ultraviolet phototransistor with an integrated temperature sensing unit, specifically implemented according to the following steps:

[0021] Step 1: Prepare n-type 4H-SiC substrates using physical vapor transport (PVT);

[0022] Step 2: An n+ emitter region, a p-type epitaxial layer, an n- collector region, and an n+ collector region are sequentially epitaxially prepared on the surface of an n-type 4H-SiC substrate by chemical vapor deposition (CVD).

[0023] Step 3: Etch the edges of the n- and n+ collector regions using photolithography and dry etching processes to expose the upper surface of the p-type epitaxial layer; perform photolithography and dry etching again to etch the p-type epitaxial layer to expose the upper surface of the n+ emitter region, forming the p-type emitter region and the p-type base region.

[0024] Step 4: Fabricate emitter ohmic contact metal on the lower surface of the n+ substrate by vacuum evaporation and rapid thermal annealing;

[0025] Step 5: Fabricate collector ohmic contact metal on the upper surface of the n+ collector region and temperature sensing ohmic contact metal on the upper surface of the p-type emitter region using photolithography, vacuum evaporation, and lift-off methods.

[0026] Step 6: Fabricate a silicon dioxide dielectric layer on the exposed n+ emitter surface, the exposed n- collector sidewall, the edge and sidewall of the exposed n+ collector surface, the exposed p-type emitter surface and sidewall, and the exposed p-type base sidewall using plasma-enhanced chemical vapor deposition (PECVD).

[0027] Step 7: Cover the lower surface of the emitter ohmic contact metal with emitter PAD metal by vacuum evaporation; cover the upper surface of the temperature sensing end ohmic contact metal with temperature sensing end PAD metal by vacuum evaporation, photolithography and etching, and cover the upper surface of the collector ohmic contact metal with collector PAD metal.

[0028] Step 8: Fabricate a transparent conductive film between the collector ohmic contact metal 9 and on the exposed n+ collector region surface by magnetron sputtering or thin film transfer.

[0029] Step 9: Fabrication of SiC top collector ultraviolet phototransistors with integrated temperature measurement units by dotting, dicing, and packaging.

[0030] The second technical solution of the present invention is further characterized in that,

[0031] In step 1, the growth temperature for preparing the n+ type 4H-SiC substrate by physical vapor transport (PVT) is 2100℃~2200℃.

[0032] In step 2, the n+ emitter region, p-type epitaxial layer, n- collector region and n+ collector region are sequentially epitaxially prepared on the substrate surface by chemical vapor deposition (CVD) at a growth temperature of 1400℃~1700℃.

[0033] In step 4, emitter ohmic contact metal is fabricated on the lower surface of the n+ substrate by vacuum evaporation and rapid thermal annealing, with a rapid annealing temperature of 950℃~1100℃.

[0034] The beneficial effect of this invention is that the SiC top collector ultraviolet phototransistor with integrated temperature sensing unit, 1) by setting the n located at the top - Collector region 4, n + 1) The ultraviolet light response intensity of the SiC top collector region ultraviolet phototransistor with integrated temperature sensing unit of the present invention is stronger than that of the traditional SiC ultraviolet phototransistor, through the setting of the p-type emitter region 6, the ohmic contact metal 10 of the temperature sensing end, and the PAD metal 13 of the temperature sensing end, the SiC top collector region ultraviolet phototransistor with integrated temperature sensing unit of the present invention can realize online monitoring of junction temperature, which solves the problem of large deviation in ultraviolet light intensity measurement results caused by large temperature drift compared with the traditional SiC ultraviolet phototransistor; 3) Through the setting of the transparent conductive film 15, the SiC top collector region ultraviolet phototransistor with integrated temperature sensing unit of the present invention has better photogenerated carrier collection capability than the traditional SiC ultraviolet phototransistor, which helps to improve the ultraviolet light response intensity. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the cross-sectional structure of a SiC-based ultraviolet phototransistor with a top collector region according to the present invention;

[0036] Figure 2 It is to complete n + Launch region 2, p-type epitaxial layer 3, n - Collector region 4, n + A cross-sectional structural diagram of the epitaxial manufacturing process of collector region 5;

[0037] Figure 3 This is a schematic cross-sectional view of the p-type emitter region 6 and p-type base region 7 fabricated by photolithography and dry etching.

[0038] Figure 4 This is a schematic cross-sectional view of the completed manufacturing process of the emitter ohmic contact metal 8.

[0039] Figure 5 This is a cross-sectional structural diagram of the manufacturing process of the collector ohmic contact metal 9 and the temperature sensing end ohmic contact metal 10.

[0040] Figure 6 This is a schematic cross-sectional view of the silicon dioxide dielectric layer 11 fabrication process completed by PECVD deposition, photolithography, and etching.

[0041] Figure 7 This is a schematic cross-sectional view of the manufacturing process of emitter PAD metal 12, temperature sensing PAD metal 13, and collector PAD metal 14, which are completed by vacuum evaporation.

[0042] Figure 8 This is a schematic cross-sectional view of the transparent conductive thin film 15 manufactured by photolithography and sputtering.

[0043] Figure 9 This is the output characteristic curve of a SiC top collector ultraviolet phototransistor with an integrated temperature measurement unit in Embodiment 1 of the present invention.

[0044] In the figure, n-type 4H-SiC substrate, n + Launch region 2, p-type epitaxial layer 3, n - Collector region 4, n + 5. Collector region, 6. p-type emitter region, 7. p-type base region, 8. Emitter ohmic contact metal, 9. Collector ohmic contact metal, 10. Temperature sensing end ohmic contact metal, 11. Silicon dioxide dielectric layer, 12. Emitter PAD metal, 13. Temperature sensing end PAD metal, 14. Collector PAD metal, 15. Transparent conductive film. Detailed Implementation

[0045] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0046] The SiC top collector ultraviolet phototransistor with integrated temperature sensing unit of this invention has the following structure: Figure 1 As shown, it includes an n-type 4H-SiC substrate 1, on which n-type 4H-SiC substrate 1 is formed with n-type 4H-SiC substrate 1 facing upwards. + Launch area 2, n + A p-type base region 7 is formed at the center of the emitter region 2, facing upwards. Above the p-type base region 7 are an n- collector region 4 and an n+ collector region 5. Above the n+ collector region 5 are a collector ohmic contact metal 9 and a transparent conductive film 15. The collector ohmic contact metal 9 and the transparent conductive film 15 are arranged alternately on the surface of the n+ collector region 5, with collector ohmic contact metal 9 on both sides of the n+ collector region 5. The collector ohmic contact metal 9, n+ collector region 5, n- collector region 4, and p-type base region 7 form a single unit. Silicon dioxide dielectric layers 11 are disposed on both sides of this unit. + On both sides of the surface of emitter region 2, facing upwards, are p-type emitter regions 6. On the surface of each p-type emitter region 6, facing upwards, are temperature-sensing ohmic contact metal 10s. The upper surface of the temperature-sensing ohmic contact metal 10 is covered with a temperature-sensing PAD metal 13. A silicon dioxide dielectric layer 11 covers part of the upper surface and the entire side surface of the collector ohmic contact metal 9. The silicon dioxide dielectric layer 11 also covers the sides of the n+ collector region 5, the n- collector region 4, and the p-type base region 7, as well as the n-type base region 7. + The exposed surface of the emitter region 2, as well as part of the upper surface and the entire side of the p-type emitter region 6 and the temperature sensing end ohmic contact metal 10; the upper surface of the collector ohmic contact metal 9 is covered with collector PAD metal 14, and the lower surface of the n-type 4H-SiC substrate 1 has an emitter ohmic contact metal 8 grown downwards, and the lower surface of the emitter ohmic contact metal 8 is covered with emitter PAD metal 12.

[0047] The n-type 4H-SiC substrate has a thickness of 150–350 μm and a donor impurity concentration of 1.0 × 10⁻⁶. 18 cm -3 ~2.0×10 19 cm -3 ;

[0048] n + The thickness of the upper and lower surfaces of emission region 2 is 0.5–1.0 μm, and the impurity concentration is 1.0 × 10⁻⁶. 18 cm -3 ~2.0×10 19 cm -3 ;

[0049] The p-type emitter region 6 is located on both sides of the p-type base region 7, with a lateral spacing of 1.0 μm to 100 μm between them; the width of the p-type emitter region 6 is 10 μm to 1 mm, and the width of the p-type base region 7 is 500 μm to 5 mm; the p-type emitter region 6 and the p-type base region 7 have the same thickness and doping concentration, with a thickness of 0.2 to 1.0 μm and an impurity concentration of 2.0 × 10⁻⁶. 16 cm -3 ~2.0×10 17 cm -3 ;

[0050] The thickness of n-collector region 4 is 0.5 μm to 10 μm, and the impurity concentration of n-collector region 4 is 1.0 × 10⁻⁶. 13 cm -3 ~1.0×10 16 cm -3 ;

[0051] The junction depth of the n+ collector region 5 is 0.2 μm to 0.5 μm, and the impurity concentration of the n+ collector region 5 is 1.0 × 10⁻⁶. 18 cm -3 ~2.0×10 19 cm -3 ;

[0052] The emitter ohmic contact metal 8 is formed from one or more combinations of Ti, Ni, W, and Al, and the thickness of the emitter ohmic contact metal 8 is 100 nm to 300 nm.

[0053] The collector ohmic contact metal 9 is formed from one or more combinations of Ti, Ni, W, and Al, and the thickness of the collector ohmic contact metal 9 is 100 nm to 300 nm.

[0054] The ohmic contact metal 10 of the temperature measuring end is formed by one or more combinations of Ti, Ni, W and Al, and the thickness of the ohmic contact metal 10 of the temperature measuring end is 100nm to 300nm.

[0055] The thickness of the silicon dioxide dielectric layer 11 is 200 nm to 2000 nm;

[0056] The emitter PAD metal 12 is formed of one or more combinations of Ni, Ag, and Au, and the thickness of the emitter PAD metal 12 is 1.0 μm to 20 μm;

[0057] The temperature sensing PAD metal 13 is formed of one or more combinations of W, Al, Cu, and Au, and the thickness of the temperature sensing PAD metal 13 is 1.0μm to 10μm;

[0058] The collector PAD metal 14 is formed of one or more combinations of W, Al, Cu, and Au, and the thickness of the collector PAD metal 14 is 1.0 μm to 10 μm.

[0059] A transparent conductive film 15 is covered between the collector ohmic contact metal 9 and on the exposed n+ collector region 5. The transparent conductive film 15 is made of one or more of AZO, ITO, and graphene, and has a thickness of 1nm to 1μm.

[0060] The fabrication method of the SiC top collector region ultraviolet phototransistor with integrated temperature sensing unit is implemented according to the following steps:

[0061] n-type 4H-SiC substrates were prepared by physical vapor transport (PVT) at a growth temperature of 2100℃~2200℃.

[0062] An n+ emitter region 2, a p-type epitaxial layer 3, an n- collector region 4, and an n+ collector region 5 were sequentially epitaxially deposited on an n-type 4H-SiC substrate 1 using chemical vapor deposition (CVD). The growth temperatures for all regions were between 1400℃ and 1700℃. Figure 2 As shown;

[0063] The edges of the n- collector region 4 and the n+ collector region 5 are etched using photolithography and dry etching processes to expose the upper surface of the p-type epitaxial layer 3. Then, photolithography and dry etching are performed again to etch the p-type epitaxial layer 3, exposing the upper surface of the n+ emitter region 2, thus forming the p-type emitter region 6 and the p-type base region 7. Figure 3 As shown;

[0064] Emitter ohmic contact metal 8 was fabricated on the lower surface of n+ substrate 1 by vacuum evaporation and rapid thermal annealing. The rapid annealing temperature was 950℃~1100℃. Figure 4 As shown;

[0065] Collector ohmic contact metal 9 is fabricated on the upper surface of the n+ collector region 5 using photolithography, vacuum evaporation, and lift-off methods, and temperature sensing ohmic contact metal 10 is fabricated on the upper surface of the p-type emitter region 6. Figure 5 As shown;

[0066] A silicon dioxide dielectric layer 11 is fabricated on the upper surface of the exposed n+ emitter region 2, the sidewall of the exposed n- collector region 4, the edge and sidewall of the upper surface of the exposed n+ collector region 5, the upper surface and sidewall of the exposed p-type emitter region 6, and the sidewall of the exposed p-type base region 7 using plasma-enhanced chemical vapor deposition (PECVD). Figure 6 As shown;

[0067] Emitter PAD metal 12 is deposited on the lower surface of the emitter ohmic contact metal 8 using vacuum evaporation; temperature sensing PAD metal 13 is deposited on the upper surface of the temperature sensing ohmic contact metal 10 using vacuum evaporation, photolithography, and etching; and collector PAD metal 14 is deposited on the upper surface of the collector ohmic contact metal 9. Figure 7 As shown;

[0068] A transparent conductive film 15 is fabricated between the collector ohmic contact metal 9 and on the exposed n+ collector region 5 using magnetron sputtering or thin film transfer methods, such as... Figure 8 As shown;

[0069] The SiC top collector ultraviolet phototransistor with integrated temperature measurement unit was fabricated by dotting, dicing, and packaging.

[0070] To illustrate the advantages of the SiC top collector ultraviolet phototransistor with integrated temperature sensing unit of the present invention, the SiC top collector ultraviolet phototransistor with integrated temperature sensing unit of the above embodiment 1 was verified using the Sentaurus TCAD computer numerical experimental platform.

[0071] Figure 9 The figure shows the output characteristic curve of a SiC top-collector ultraviolet phototransistor with an integrated temperature sensing unit according to Embodiment 1 of the present invention. As can be seen from the figure, under the same ultraviolet light intensity, the SiC top-collector ultraviolet phototransistor with the integrated temperature sensing unit of the present invention has a larger collector than the conventional SiC npn type ultraviolet phototransistor. In summary, the SiC top-collector ultraviolet phototransistor with an integrated temperature sensing unit of the present invention improves the responsivity of existing SiC ultraviolet phototransistors and solves the problem of large temperature drift.

[0072] Example 1

[0073] like Figure 1 The structure of a SiC top-collector ultraviolet phototransistor with an integrated temperature sensing unit in Embodiment 1 of the present invention includes a substrate 1 made of n-type 4H-SiC with a thickness of 180 μm and a donor impurity concentration of 2.0 × 10⁻⁶. 18 cm -3 ;

[0074] n-type 4H-SiC substrate 1 with surface 1 facing upwards has n +Emission region 2 has a thickness of 0.5–1.0 μm on its upper and lower surfaces, and an impurity concentration of 5.0 × 10⁻⁶. 18 cm -3 ;

[0075] n + A p-type emitter region 6 and a p-type base region 7 are fabricated on the surface of emitter region 2 with the surface facing upwards. The p-type emitter region 6 is located on both sides of the p-type base region 7, with a lateral spacing of 10 μm between them. The width of the p-type emitter region 6 is 100 μm, and the width of the p-type base region 7 is 1000 μm. The p-type emitter region 6 and the p-type base region 7 have the same thickness and doping concentration, with a thickness of 0.3 μm and an impurity concentration of 6.0 × 10⁻⁶. 16 cm -3 ;

[0076] The n-collector region 4, located on the upper surface of the p-type base region 7, has a thickness of 6.0 μm and an impurity concentration of 5.0 × 10⁻⁶. 15 cm -3 ;

[0077] The n+ collector region 5, located on the upper surface of the n- collector region 4, has a junction depth of 0.3 μm and an impurity concentration of 2.0 × 10⁻⁶. 18 cm -3 ;

[0078] The emitter ohmic contact metal 8 located on the lower surface of the n-type 4H-SiC substrate 1 is formed of one or more combinations of Ti, Ni, W, Al, etc., with a thickness of 200nm;

[0079] The collector ohmic contact metal 9 located on the upper surface of the n+ collector region 5 is formed by one or more combinations of Ti, Ni, W, Al, etc., and has a thickness of 200 nm.

[0080] The temperature-sensing ohmic contact metal 10 located on the upper surface of the p-type emitter region 6 is formed of one or more combinations of Ti, Ni, W, Al, etc., with a thickness of 200 nm.

[0081] The exposed n+ emitter region 2, the exposed n- collector region 4, the edge and sidewall of the exposed n+ collector region 5, the exposed p-type emitter region 6, and the exposed p-type base region 7 are all covered with a silicon dioxide dielectric layer 11 with a thickness of 1000 nm.

[0082] The lower surface of the emitter ohmic contact metal 8 is covered with emitter PAD metal 12, which is made of one or more of the following materials: Ni, Ag, Au, etc., and has a thickness of 5μm.

[0083] The upper surface of the ohmic contact metal 10 of the temperature measuring end is covered with the temperature measuring end PAD metal 13, which is made of one or more of the following materials: W, Al, Cu, Au, etc., and has a thickness of 5μm.

[0084] The upper surface of the collector ohmic contact metal 9 is covered with collector PAD metal 14, which is made of one or more of the following materials: W, Al, Cu, Au, etc., and has a thickness of 5μm.

[0085] Between the collector ohmic contact metal 9, the exposed n+ collector region 5 is covered with a transparent conductive film 15. The transparent conductive film 15 is made of one or more of the following materials: AZO, ITO, graphene, etc., and has a thickness of 100nm.

[0086] like Figures 2-8 Embodiment 1 of the present invention discloses a method for manufacturing a SiC top collector ultraviolet phototransistor with an integrated temperature sensing unit, which is implemented according to the following steps:

[0087] Substrate 1 of n+ type 4H-SiC was prepared by physical vapor transport (PVT) at a growth temperature of 2150℃.

[0088] The n+ emitter region 2, p-type epitaxial layer 3, n- collector region 4, and n+ collector region 5 were sequentially epitaxially deposited on the surface of substrate 1 by chemical vapor deposition (CVD) at a growth temperature of 1450℃.

[0089] The edges of the n- collector region 4 and the n+ collector region 5 are etched by photolithography and dry etching processes to expose the upper surface of the p-type epitaxial layer 3; the p-type epitaxial layer 3 is etched again by photolithography and dry etching processes to expose the upper surface of the n+ emitter region 2, forming the p-type emitter region 6 and the p-type base region 7.

[0090] Emitter ohmic contact metal 8 was fabricated on the lower surface of n+ substrate 1 by vacuum evaporation and rapid thermal annealing at a rapid annealing temperature of 1050℃.

[0091] Collector ohmic contact metal 9 and temperature sensing ohmic contact metal 10 are fabricated on the upper surfaces of the n+ collector region 5 and the p-type emitter region 6 respectively using photolithography, vacuum evaporation, and lift-off methods. Figure 5 As shown;

[0092] A silicon dioxide dielectric layer 11 is fabricated on the upper surface of the exposed n+ emitter region 2, the sidewall of the exposed n- collector region 4, the edge and sidewall of the upper surface of the exposed n+ collector region 5, the upper surface and sidewall of the exposed p-type emitter region 6, and the sidewall of the exposed p-type base region 7 using plasma-enhanced chemical vapor deposition (PECVD). Figure 6 As shown;

[0093] Emitter PAD metal 12 is deposited on the lower surface of the emitter ohmic contact metal 8 by vacuum evaporation; temperature sensing PAD metal 13 is deposited on the upper surface of the temperature sensing ohmic contact metal 10 by vacuum evaporation, photolithography, and etching, and collector PAD metal 14 is deposited on the upper surface of the collector ohmic contact metal 9, as shown below. Figure 7 As shown;

[0094] A transparent conductive film 15 is fabricated on the upper surface of the exposed n+ collector region 5 between the collector ohmic contact metal 9 by magnetron sputtering or thin film transfer. Figure 8 As shown;

[0095] The SiC top collector ultraviolet phototransistor with integrated temperature sensing unit is manufactured by dotting, dicing, and packaging.

[0096] To illustrate the advantages of the SiC top collector ultraviolet phototransistor with integrated temperature measurement unit in Embodiment 1 of the present invention, the SiC top collector ultraviolet phototransistor with integrated temperature measurement unit in Embodiment 1 was verified using the Sentaurus TCAD computer numerical experimental platform.

[0097] Figure 9 The figure shows the output characteristic curve of a SiC top-collector ultraviolet phototransistor with an integrated temperature sensing unit according to Embodiment 1 of the present invention. As can be seen from the figure, under the same ultraviolet light intensity, the SiC top-collector ultraviolet phototransistor with the integrated temperature sensing unit of the present invention has a larger collector than the conventional SiC npn type ultraviolet phototransistor. In summary, the SiC top-collector ultraviolet phototransistor with an integrated temperature sensing unit of the present invention improves the responsivity of existing SiC ultraviolet phototransistors and solves the problem of large temperature drift.

[0098] Example 2

[0099] The structure of a SiC top-collector ultraviolet phototransistor with an integrated temperature sensing unit in Embodiment 2 of the present invention includes a substrate 1 made of n-type 4H-SiC with a thickness of 150 μm and a donor impurity concentration of 1.0 × 10⁻⁶. 18 cm -3 cm -3 ;

[0100] n-type 4H-SiC substrate 1 with surface 1 facing upwards has n + Emission region 2 has a thickness of 0.5 μm on both its upper and lower surfaces, and an impurity concentration of 1.0 × 10⁻⁶. 18 cm -3 cm -3 ;

[0101] n +A p-type emitter region 6 and a p-type base region 7 are fabricated on the surface of emitter region 2, with the p-type emitter region 6 located on both sides of the p-type base region 7, and the lateral spacing between them is 1.0 μm. The width of the p-type emitter region 6 is 10 μm, and the width of the p-type base region 7 is 500 μm. The p-type emitter region 6 and the p-type base region 7 have the same thickness and doping concentration, with a thickness of 0.2 μm and an impurity concentration of 2.0 × 10⁻⁶. 16 cm -3 ;

[0102] The n-collector region 4, located on the upper surface of the p-type base region 7, has a thickness of 0.5 μm and an impurity concentration of 1.0 × 10⁻⁶. 13 cm -3 cm -3 ;

[0103] The n+ collector region 5, located on the upper surface of the n- collector region 4, has a junction depth of 0.2 μm and an impurity concentration of 1.0 × 10⁻⁶. 18 cm -3 cm -3 ;

[0104] The emitter ohmic contact metal 8 located on the lower surface of the n-type 4H-SiC substrate 1 is formed by one or more combinations of Ti, Ni, W, Al, etc., and has a thickness of 100nm;

[0105] The collector ohmic contact metal 9 located on the upper surface of the n+ collector region 5 is formed by one or more combinations of Ti, Ni, W, Al, etc., and has a thickness of 100 nm.

[0106] The temperature-sensing ohmic contact metal 10 located on the upper surface of the p-type emitter region 6 is formed of one or more combinations of Ti, Ni, W, Al, etc., with a thickness of 100 nm.

[0107] The exposed n+ emitter region 2, the exposed n- collector region 4, the edge and sidewall of the exposed n+ collector region 5, the exposed p-type emitter region 6, and the exposed p-type base region 7 are all covered with a silicon dioxide dielectric layer 11 with a thickness of 200 nm.

[0108] The lower surface of the emitter ohmic contact metal 8 is covered with emitter PAD metal 12, which is made of one or more of the following materials: Ni, Ag, Au, etc., and has a thickness of 1.0 μm.

[0109] The upper surface of the ohmic contact metal 10 of the temperature measuring end is covered with the temperature measuring end PAD metal 13, which is made of one or more of the following materials: W, Al, Cu, Au, etc., and has a thickness of 1.0 μm.

[0110] The upper surface of the collector ohmic contact metal 9 is covered with collector PAD metal 14, which is made of one or more of the following materials: W, Al, Cu, Au, etc., and has a thickness of 1.0 μm.

[0111] Between the collector ohmic contact metal 9, the exposed n+ collector region 5 is covered with a transparent conductive film 15. The transparent conductive film 15 is made of one or more of the following materials: AZO, ITO, graphene, etc., and has a thickness of 1nm.

[0112] Embodiment 2 of the present invention discloses a method for manufacturing a SiC top collector ultraviolet phototransistor with an integrated temperature sensing unit, which is implemented according to the following steps:

[0113] Substrate 1 of n+ type 4H-SiC was prepared by physical vapor transport (PVT) at a growth temperature of 2100℃.

[0114] The n+ emitter region 2, p-type epitaxial layer 3, n- collector region 4, and n+ collector region 5 were sequentially epitaxially prepared on the surface of substrate 1 by chemical vapor deposition (CVD) at a growth temperature of 1400℃.

[0115] The edges of the n- collector region 4 and the n+ collector region 5 are etched by photolithography and dry etching processes to expose the upper surface of the p-type epitaxial layer 3; the p-type epitaxial layer 3 is etched again by photolithography and dry etching processes to expose the upper surface of the n+ emitter region 2, forming the p-type emitter region 6 and the p-type base region 7.

[0116] Emitter ohmic contact metal 8 was fabricated on the lower surface of n+ substrate 1 by vacuum evaporation and rapid thermal annealing at a rapid annealing temperature of 950℃.

[0117] The n-type substrates were deposited using photolithography, vacuum evaporation, and lift-off methods. + Collector ohmic contact metal 9 and temperature sensing end ohmic contact metal 10 are fabricated on the upper surfaces of collector region 5 and p-type emitter region 6;

[0118] A silicon dioxide dielectric layer 11 is fabricated on the upper surface of the exposed n+ emitter region 2, the sidewall of the exposed n- collector region 4, the edge and sidewall of the upper surface of the exposed n+ collector region 5, the upper surface and sidewall of the exposed p-type emitter region 6, and the sidewall of the exposed p-type base region 7 using PECVD.

[0119] Emitter PAD metal 12 is coated on the lower surface of emitter ohmic contact metal 8 by vacuum evaporation; temperature sensing PAD metal 13 is coated on the upper surface of temperature sensing ohmic contact metal 10 by vacuum evaporation, photolithography and etching, and collector PAD metal 14 is coated on the upper surface of collector ohmic contact metal 9.

[0120] A transparent conductive film 15 is fabricated on the upper surface of the exposed n+ collector region 5 between the collector ohmic contact metal 9 by magnetron sputtering or thin film transfer.

[0121] The SiC top collector ultraviolet phototransistor with integrated temperature sensing unit is manufactured by dotting, dicing, and packaging.

[0122] Example 3

[0123] The structure of a SiC top-collector ultraviolet phototransistor with an integrated temperature sensing unit in Embodiment 3 of the present invention includes a substrate 1 made of n-type 4H-SiC with a thickness of 350 μm and a donor impurity concentration of 2.0 × 10⁻⁶. 19 cm -3 ;

[0124] n-type 4H-SiC substrate 1 with surface 1 facing upwards has n + Emission region 2 has a thickness of 1.0 μm on both its upper and lower surfaces, and an impurity concentration of 2.0 × 10⁻⁶. 19 cm -3 ;

[0125] n + A p-type emitter region 6 and a p-type base region 7 are fabricated on the surface of emitter region 2 with the surface facing upwards. The p-type emitter region 6 is located on both sides of the p-type base region 7, with a lateral spacing of 100 μm between them. The width of the p-type emitter region 6 is 1 mm, and the width of the p-type base region 7 is 5 mm. The p-type emitter region 6 and the p-type base region 7 have the same thickness and doping concentration, with a thickness of 1.0 μm and an impurity concentration of 2.0 × 10⁻⁶. 17 cm -3 ;

[0126] The n-collector region 4, located on the upper surface of the p-type base region 7, has a thickness of 10 μm and an impurity concentration of 1.0 × 10⁻⁶. 16 cm -3 ;

[0127] The n+ collector region 5, located on the upper surface of the n- collector region 4, has a junction depth of 0.5 μm and an impurity concentration of 2.0 × 10⁻⁶. 19 cm -3 ;

[0128] The emitter ohmic contact metal 8 located on the lower surface of the n-type 4H-SiC substrate 1 is formed by one or more combinations of Ti, Ni, W, Al, etc., and has a thickness of 300nm;

[0129] The collector ohmic contact metal 9 located on the upper surface of the n+ collector region 5 is formed by one or more combinations of Ti, Ni, W, Al, etc., and has a thickness of 300 nm.

[0130] The temperature-sensing ohmic contact metal 10 located on the upper surface of the p-type emitter region 6 is formed of one or more combinations of Ti, Ni, W, Al, etc., with a thickness of 300 nm.

[0131] The exposed n+ emitter region 2, the exposed n- collector region 4, the edge and sidewall of the exposed n+ collector region 5, the exposed p-type emitter region 6, and the exposed p-type base region 7 are all covered with a silicon dioxide dielectric layer 11 with a thickness of 2000 nm.

[0132] The lower surface of the emitter ohmic contact metal 8 is covered with emitter PAD metal 12, which is made of one or more of the following materials: Ni, Ag, Au, etc., and has a thickness of 20μm.

[0133] The upper surface of the ohmic contact metal 10 of the temperature measuring end is covered with the temperature measuring end PAD metal 13, which is made of one or more of the following materials: W, Al, Cu, Au, etc., and has a thickness of 10μm.

[0134] The upper surface of the collector ohmic contact metal 9 is covered with collector PAD metal 14, which is made of one or more of the following materials: W, Al, Cu, Au, etc., and has a thickness of 10 μm.

[0135] Between the collector ohmic contact metal 9, the exposed n+ collector region 5 is covered with a transparent conductive film 15. The transparent conductive film 15 is made of one or more of the following materials: AZO, ITO, graphene, etc., and has a thickness of 1μm.

[0136] like Figures 2-8 The present invention discloses a method for manufacturing a SiC top collector region ultraviolet phototransistor with an integrated temperature sensing unit, which is implemented according to the following steps:

[0137] Substrate 1 of n+ type 4H-SiC was prepared by physical vapor transport (PVT) at a growth temperature of 2200℃.

[0138] The n+ emitter region 2, p-type epitaxial layer 3, n- collector region 4, and n+ collector region 5 were sequentially epitaxially deposited on the surface of substrate 1 by chemical vapor deposition (CVD) at a growth temperature of 1700℃.

[0139] The edges of the n- collector region 4 and the n+ collector region 5 are etched by photolithography and dry etching processes to expose the upper surface of the p-type epitaxial layer 3; the p-type epitaxial layer 3 is etched again by photolithography and dry etching processes to expose the upper surface of the n+ emitter region 2, forming the p-type emitter region 6 and the p-type base region 7.

[0140] Emitter ohmic contact metal 8 was fabricated on the lower surface of n+ substrate 1 by vacuum evaporation and rapid thermal annealing at a rapid annealing temperature of 1100℃.

[0141] The collector ohmic contact metal 9 and the temperature sensing end ohmic contact metal 10 are fabricated on the upper surfaces of the n+ collector region 5 and the p-type emitter region 6 respectively by photolithography, vacuum evaporation and lift-off.

[0142] A silicon dioxide dielectric layer 11 is fabricated on the upper surface of the exposed n+ emitter region 2, the sidewall of the exposed n- collector region 4, the edge and sidewall of the upper surface of the exposed n+ collector region 5, the upper surface and sidewall of the exposed p-type emitter region 6, and the sidewall of the exposed p-type base region 7 using PECVD.

[0143] Emitter PAD metal 12 is coated on the lower surface of emitter ohmic contact metal 8 by vacuum evaporation; temperature sensing PAD metal 13 is coated on the upper surface of temperature sensing ohmic contact metal 10 by vacuum evaporation, photolithography and etching, and collector PAD metal 14 is coated on the upper surface of collector ohmic contact metal 9.

[0144] A transparent conductive film 15 is fabricated on the upper surface of the exposed n+ collector region 5 between the collector ohmic contact metal 9 by magnetron sputtering or thin film transfer.

[0145] The SiC top collector ultraviolet phototransistor with integrated temperature sensing unit is manufactured by dotting, dicing, and packaging.

Claims

1. A SiC top-collector ultraviolet phototransistor with an integrated temperature sensing unit, characterized in that, Including an n-type 4H-SiC substrate (1), on which n-type 4H-SiC substrate (1) is fabricated with n-type 4H-SiC substrate (1) facing upwards. + Launch area (2), n + A p-type base region (7) is formed at the center of the emitter region (2), and an n- collector region (4) and an n+ collector region (5) are formed sequentially on the surface of the p-type base region (7). An ohmic collector metal (9) and a transparent conductive film (15) are formed on the surface of the n+ collector region (5), with the ohmic collector metal (9) and the transparent conductive film (15) arranged alternately on the surface of the n+ collector region (5). The ohmic collector metal (9), the n+ collector region (5), the n- collector region (4), and the p-type base region (7) form a whole. A silicon dioxide dielectric layer (11) is provided on both sides of the whole. + On both sides of the surface of the emitting region (2), p-type emitting regions (6) are formed facing upwards. On the surface of each p-type emitting region (6), a temperature-sensing ohmic contact metal (10) is formed facing upwards. The upper surface of the temperature-sensing ohmic contact metal (10) is covered with a temperature-sensing PAD metal (13). A silicon dioxide dielectric layer (11) covers part of the upper surface and the entire side of the collector ohmic contact metal (9). The silicon dioxide dielectric layer (11) also covers the side of the n+ collector region (5), the n- collector region (4), and the p-type base region (7), as well as the n-type base region (7). + The exposed surface of the emitter region (2), as well as part of the upper surface and the entire side of the p-type emitter region (6) and the temperature measuring end ohmic contact metal (10); the upper surface of the collector ohmic contact metal (9) is covered with collector PAD metal (14), the lower surface of the n-type 4H-SiC substrate (1) is grown downward with emitter ohmic contact metal (8), and the lower surface of the emitter ohmic contact metal (8) is covered with emitter PAD metal (12).

2. The SiC top collector ultraviolet phototransistor of the integrated temperature sensing unit according to claim 1, characterized in that, The n-type 4H-SiC substrate (1) has a thickness of 150–350 μm and a donor impurity concentration of 1.0 × 10⁻⁶. 18 cm -3 ~2.0×10 19 cm -3 ; n + The thickness of the upper and lower surfaces of the emission region (2) is 0.5–1.0 μm, and the impurity concentration is 1.0 × 10⁻⁶. 18 cm -3 ~2.0×10 19 cm -3 ; The p-type emitter region (6) is located on both sides of the p-type base region (7), with a lateral spacing of 1.0 μm to 100 μm between them; the width of the p-type emitter region (6) is 10 μm to 1 mm, and the width of the p-type base region (7) is 500 μm to 5 mm; the p-type emitter region (6) and the p-type base region (7) have the same thickness and doping concentration, with a thickness of 0.2 to 1.0 μm and an impurity concentration of 2.0 × 10⁻⁶. 16 cm -3 ~2.0×10 17 cm -3 ; The thickness of the n-collector region (4) is 0.5 μm to 10 μm, and the impurity concentration of the n-collector region (4) is 1.0 × 10⁻⁶. 13 cm -3 ~1.0×10 16 cm -3 ; The junction depth of the n+ collector region (5) is 0.2 μm to 0.5 μm, and the impurity concentration of the n+ collector region (5) is 1.0 × 10⁻⁶. 18 cm -3 ~2.0×10 19 cm -3 .

3. The SiC top collector ultraviolet phototransistor of the integrated temperature sensing unit according to claim 1, characterized in that, The emitter ohmic contact metal (8) is formed from one or more combinations of Ti, Ni, W and Al, and the thickness of the emitter ohmic contact metal (8) is 100nm to 300nm. The current collector ohmic contact metal (9) is formed by one or more combinations of Ti, Ni, W and Al, and the thickness of the current collector ohmic contact metal (9) is 100nm to 300nm. The ohmic contact metal (10) of the temperature measuring end is formed by one or more combinations of Ti, Ni, W and Al, and the thickness of the ohmic contact metal (10) of the temperature measuring end is 100nm to 300nm. The thickness of the silicon dioxide dielectric layer (11) is 200 nm to 2000 nm; The emitter PAD metal (12) is made of one or more of Ni, Ag, and Au, and the thickness of the emitter PAD metal (12) is 1.0 μm to 20 μm. The temperature measuring end PAD metal (13) is made of one or more of W, Al, Cu and Au, and the thickness of the temperature measuring end PAD metal (13) is 1.0 μm to 10 μm. The collector PAD metal (14) is formed of one or more combinations of W, Al, Cu and Au, and the thickness of the collector PAD metal (14) is 1.0 μm to 10 μm.

4. The SiC top collector ultraviolet phototransistor of the integrated temperature sensing unit according to claim 1, characterized in that, The ohmic contact metals (9) between the collector electrodes and the upper surface of the exposed n+ collector region (5) are covered with a transparent conductive film (15). The transparent conductive film (15) is made of one or more of AZO, ITO, and graphene, and has a thickness of 1 nm to 1 μm.

5. A method for fabricating a SiC top-collector ultraviolet phototransistor with an integrated temperature sensing unit, characterized in that, The specific steps are as follows: Step 1: n-type 4H-SiC substrates are prepared by physical vapor transport (PVT) (1); Step 2: An n+ emitter region (2), a p-type epitaxial layer (3), an n- collector region (4), and an n+ collector region (5) are sequentially epitaxially prepared on the surface of an n-type 4H-SiC substrate (1) by chemical vapor deposition (CVD). Step 3: The edges of the n- collector region (4) and the n+ collector region (5) are etched by photolithography and dry etching process to expose the upper surface of the p-type epitaxial layer (3); the p-type epitaxial layer (3) is etched again by photolithography and dry etching process to expose the upper surface of the n+ emitter region (2) to form the p-type emitter region (6) and the p-type base region (7); Step 4: Fabricate emitter ohmic contact metal (8) on the lower surface of n+ substrate (1) by vacuum evaporation and rapid thermal annealing; Step 5: Fabricate collector ohmic contact metal (9) on the upper surface of the n+ collector region (5) and temperature sensing end ohmic contact metal (10) on the upper surface of the p-type emitter region (6) by photolithography, vacuum evaporation and stripping. Step 6: A silicon dioxide dielectric layer (11) is fabricated on the exposed n+ emitter region (2) upper surface, the exposed n- collector region (4) sidewall, the exposed n+ collector region (5) upper surface edge and sidewall, the exposed p-type emitter region (6) upper surface and sidewall, and the exposed p-type base region (7) sidewall by plasma-enhanced chemical vapor deposition (PECVD). Step 7: Cover the lower surface of the emitter ohmic contact metal (8) with emitter PAD metal (12) by vacuum evaporation; cover the upper surface of the temperature sensing end ohmic contact metal (10) with temperature sensing end PAD metal (13) by vacuum evaporation, photolithography and etching, and cover the upper surface of the collector ohmic contact metal (9) with collector PAD metal (14). Step 8: A transparent conductive film (15) is fabricated between the collector ohmic contact metal (9) and on the exposed n+ collector region (5) by magnetron sputtering or thin film transfer. Step 9: Fabrication of SiC top collector ultraviolet phototransistors with integrated temperature measurement units by dotting, dicing, and packaging.

6. The method for fabricating the SiC top collector region ultraviolet phototransistor with integrated temperature measurement unit according to claim 5, wherein the growth temperature of the substrate (1) of n+ type 4H-SiC prepared by physical vapor transport (PVT) in step 1 is 2100℃~2200℃.

7. The method for fabricating the SiC top collector region ultraviolet phototransistor with integrated temperature measurement unit according to claim 5, wherein in step 2, the growth temperature of the n+ emitter region (2), p-type epitaxial layer (3), n- collector region (4) and n+ collector region (5) are sequentially epitaxially prepared on the surface of the substrate (1) by chemical vapor deposition (CVD) is 1400℃~1700℃.

8. The method for fabricating the SiC top collector region ultraviolet phototransistor with integrated temperature measurement unit according to claim 5, wherein in step 4, an emitter ohmic contact metal (8) is fabricated on the lower surface of the n+ substrate (1) by vacuum evaporation and rapid thermal annealing, and the rapid annealing temperature is 950℃~1100℃.

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