A mixed-signal crystal oscillator circuit and method

Abstract

The application discloses a crystal oscillation circuit based on a mixed signal, which comprises a crystal oscillator, a dividing circuit, a delay phase-locked loop, a pulse generating circuit and a driving circuit; the dividing circuit is connected with the input end of the crystal oscillator; the delay phase-locked loop comprises a dynamic comparator, an add-subtract counter, a data selector and a delay circuit; the dynamic comparator is connected with the output end of the crystal oscillator and the pulse generating circuit respectively; the add-subtract counter is connected with the dynamic comparator; the data selector is connected with the add-subtract counter; the delay circuit is connected with the data selector; the pulse generating circuit is connected with the delay circuit; and the driving circuit is connected with the pulse generating circuit. The application can reduce the phase noise and improve the energy injection efficiency, reduce the circuit area and facilitate the process migration.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a crystal oscillator circuit and method based on mixed signals. Background Technology

[0002] To reduce the power consumption of the crystal oscillator circuit, a time-delayed phase-locked loop (TLL) circuit is used to precisely inject energy into the crystal oscillator at the peaks and troughs of a wave using negative feedback, thereby achieving a high signal-to-noise ratio and low power consumption. According to phase noise theory, phase noise is minimized only when energy is injected at the peaks and troughs of a sine wave.

[0003] However, the time-delay phase-locked loop (PDL) circuits currently used in crystal oscillator circuits are generally based on fully analog signals. These circuits typically require capacitors, which occupy a large area. Furthermore, the transistor characteristics differ across process nodes in fully analog circuits, necessitating redesign of circuit parameters. Therefore, using fully analog-based PLL modules is inconvenient for process migration.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a crystal oscillator circuit and method based on mixed signals, so as to solve the problems of large area occupation and inconvenience of process migration of crystal oscillator circuits in the prior art.

[0006] This invention provides a crystal oscillator circuit based on mixed signals, comprising: a crystal oscillator, a splitting circuit, a dynamic comparator, an up / down counter, a data selector, a delay circuit, a pulse generator circuit, and a driving circuit;

[0007] The splitting circuit is connected to the input terminal of the crystal oscillator and is used to split the input signal of the crystal oscillator into a first square wave signal of the same frequency.

[0008] The delay circuit is connected to the segmentation circuit and is used to delay the first square wave signal;

[0009] The dynamic comparator is connected to the output terminal of the crystal oscillator and the pulse generation circuit respectively, and is used to compare the phase of the pull-down pulse signal generated by the pulse generation circuit with the phase of the valley of the output signal of the crystal oscillator, and output a first signal according to the comparison result;

[0010] The up-and-down counter is connected to the dynamic comparator and is used to perform up-and-down counting based on the first signal;

[0011] The data selector is connected to the up / down counter and the delay circuit respectively, and is used to control the delay time of the first square wave signal according to the counting result to output the second square wave signal.

[0012] The pulse generation circuit is connected to the data selector and is used to generate a pull-down pulse signal on the rising edge of the second square wave signal and a pull-up pulse signal on the falling edge of the second square wave signal.

[0013] The driving circuit is connected to the pulse generating circuit and is used to pull up when receiving the pull-up pulse signal and pull down when receiving the pull-down pulse signal.

[0014] The present invention further provides that the up-down counter is an N-bit up-down counter and the data selector is a 2^N-bit data selector.

[0015] The present invention further comprises that the positive input terminal of the dynamic comparator is grounded, the inverting input terminal of the dynamic comparator is connected to the output terminal of the crystal oscillator, the enable terminal of the dynamic comparator is connected to the pulse generating circuit, and the output terminal of the dynamic comparator is connected to the up-down counter.

[0016] The present invention further comprises that the input terminal of the up-down counter is connected to the dynamic comparator, the enable terminal of the up-down counter is connected to the pulse generating circuit, and the output terminal of the up-down counter is connected to the data selector.

[0017] The present invention further provides that the delay circuit includes a plurality of delay units connected in series, wherein the delay units are used to delay the first square wave signal to obtain the second square wave signal.

[0018] The present invention further provides that the delay unit includes a plurality of inverters connected in series, and the ground terminal of the inverter is grounded through a current source.

[0019] The present invention further provides that the driving circuit includes: a first switch and a second switch;

[0020] The control terminal of the first switch receives the pull-up pulse signal, the first terminal of the first switch is connected to the power supply voltage, the second terminal of the first switch is connected to the first terminal of the second switch and the output terminal of the crystal oscillator, and the second terminal of the second switch is grounded.

[0021] The present invention further includes: a first resonant capacitor and a second resonant capacitor;

[0022] The input terminal of the crystal oscillator is connected to one end of the first resonant capacitor, and the other end of the first resonant capacitor is grounded.

[0023] The output terminal of the crystal oscillator is connected to one end of the second resonant capacitor, and the other end of the second resonant capacitor is grounded.

[0024] The present invention also provides a crystal oscillation method based on mixed signals, characterized in that the method includes:

[0025] The input signal of the crystal oscillator is divided into a first square wave signal of the same frequency by a splitting circuit;

[0026] The first square wave signal is delayed by a delay circuit;

[0027] When a pull-down pulse signal generated by the pulse generation circuit is detected by the dynamic comparator, the phase of the pull-down pulse signal is compared with the phase of the valley of the output signal of the crystal oscillator, and a first signal is output according to the comparison result.

[0028] The count is incremented or decremented based on the first signal using an up-and-down counter.

[0029] The delay time of the first square wave signal is controlled by the data selector according to the counting result to output the second square wave signal;

[0030] The pulse generation circuit generates the next pull-down pulse signal on the rising edge of the second square wave signal and the next pull-up pulse signal on the falling edge of the second square wave signal.

[0031] The output signal is pulled up by the drive circuit according to the pull-up pulse signal, and the output signal is pulled down according to the pull-down pulse signal.

[0032] The present invention further includes the step of comparing the phase of the pull-down pulse signal generated by the pulse generation circuit with the phase of the valley of the output signal of the crystal oscillator when the pull-down pulse signal is detected by the dynamic comparator, and outputting a first signal according to the comparison result, which includes:

[0033] When the output signal of the crystal oscillator is greater than zero potential, the first signal is at a low level; when the output signal of the crystal oscillator is less than zero potential, the first signal is at a high level.

[0034] This invention provides a mixed-signal-based crystal oscillator circuit, comprising a crystal oscillator, a splitting circuit, a dynamic comparator, an up / down counter, a data selector, a delay circuit, a pulse generator circuit, and a driving circuit. The splitting circuit is connected to the input terminal of the crystal oscillator and is used to split the input signal of the crystal oscillator into a first square wave signal of the same frequency. The delay circuit is connected to the splitting circuit and is used to delay the first square wave signal. The dynamic comparator is connected to both the output terminal of the crystal oscillator and the pulse generator circuit, and is used to compare the phase of the pull-down pulse signal generated by the pulse generator circuit with the phase of the valley of the output signal of the crystal oscillator, and output a second pulse based on the comparison result. A first signal; the up / down counter is connected to the dynamic comparator and is used to perform up / down counting based on the first signal; the data selector is connected to the up / down counter and the delay circuit respectively, and is used to control the delay time of the first square wave signal to output a second square wave signal based on the counting result; the pulse generation circuit is connected to the data selector and is used to generate a pull-down pulse signal on the rising edge of the second square wave signal and a pull-up pulse signal on the falling edge of the second square wave signal; the driving circuit is connected to the pulse generation circuit and is used to perform pull-up when receiving the pull-up pulse signal and pull-down when receiving the pull-down pulse signal.

[0035] The present invention uses the up-down counter to count according to the first signal, and uses the data selector and the delay circuit to control the delay time of the first square wave signal according to the counting result, so that the pull-up pulse signal is aligned with the valley of the output signal of the crystal oscillator, thereby reducing phase noise and improving energy injection efficiency, while reducing circuit area and facilitating process migration. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0037] Figure 1 This is a structural diagram of the crystal oscillator circuit based on mixed signals in this invention;

[0038] Figure 2 This is a schematic diagram of the crystal oscillator circuit based on mixed signals in this invention;

[0039] Figure 3 This is a timing diagram of the crystal oscillator circuit based on mixed signals in this invention;

[0040] Figure 4This is a phase relationship diagram between the pull-up pulse signal and the valley of the output signal in the crystal oscillator circuit based on mixed signals in this invention;

[0041] Figure 5 This is a circuit diagram of the delay-locked loop circuit in the mixed-signal crystal oscillator circuit of this invention;

[0042] Figure 6 This is a circuit diagram of the driving circuit in the mixed-signal crystal oscillator circuit of this invention;

[0043] Figure 7 This is a flowchart of the crystal oscillation method based on mixed signals in this invention. Detailed Implementation

[0044] This invention provides a crystal oscillator circuit and method based on mixed signals. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0045] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0046] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any of the circuits and all combinations thereof of one or more associated listed items.

[0047] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0048] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0049] Please also refer to Figures 1 to 6 The present invention provides a preferred embodiment of a crystal oscillator circuit based on mixed signals.

[0050] Please see Figures 1 to 6 This invention provides a crystal oscillator circuit based on mixed signals, comprising: a crystal oscillator 100, a splitting circuit 200, a delay phase-locked loop (PLL) circuit 300, a pulse generation circuit 400, and a driving circuit 500; the splitting circuit 200 is connected to the input terminal XIN of the crystal oscillator 100, and is used to split the input signal of the crystal oscillator 100 into a first square wave signal Vs of the same frequency; the delay phase-locked loop (PLL) circuit 300 includes: a dynamic comparator 310, an up / down counter 320, a data selector 330, and a delay circuit 340; the delay circuit 340 is connected to the splitting circuit 200, and is used to delay the first square wave signal Vs; the dynamic comparator 310 is connected to the output terminal of the crystal oscillator 100 and the pulse generation circuit 400 respectively, and is used to compare the pull-down pulse signal DP generated by the pulse generation circuit 400. The phase of the output signal valley of the crystal oscillator is compared with the phase of the first signal valley, and a first signal is output according to the comparison result; the up-down counter 320 is connected to the dynamic comparator 310 and is used to perform up-down counting according to the first signal; the data selector 330 is connected to the up-down counter 320 and is used to control the delay time of the first square wave signal Vs according to the counting result Count to output a second square wave signal Vd; the pulse generation circuit 400 is connected to the data selector 330 and is used to generate a pull-down pulse signal DP at the rising edge of the second square wave signal Vd and a pull-up pulse signal UP at the falling edge of the second square wave signal Vd; the drive circuit 500 is connected to the pulse generation circuit 400 and is used to pull up when receiving the pull-up pulse signal UP and pull down when receiving the pull-down pulse signal DP.

[0051] Specifically, such as Figure 1 As shown, the input terminal XIN of the crystal oscillator 100 is connected to one end of the first resonant capacitor CL1, and the other end of the first resonant capacitor CL1 is grounded. The output terminal XOUT of the crystal oscillator 100 is connected to one end of the second resonant capacitor CL2, and the other end of the second resonant capacitor CL2 is grounded. The crystal oscillator 100, the first resonant capacitor CL1, and the second resonant capacitor CL2 form a three-point capacitor structure to enable the crystal oscillator 100 to continuously oscillate. The first resonant capacitor CL1 and the second resonant capacitor CL2 are used to maintain the continuous oscillation of the crystal oscillator 100. The internal pin of the crystal oscillator 100 is usually an inverter. Therefore, the input terminal XIN of the crystal oscillator 100 is out of phase with the sine wave generated by the oscillation at the output terminal, that is, the waveform phase difference between the input signal and the output signal of the crystal oscillator 100 is 180°.

[0052] The segmentation circuit 200 is connected to the input terminal XIN of the crystal oscillator 100, and is used to segment the input signal (sine wave signal) into a first square wave with the same frequency and a duty cycle of 50%. The delay phase-locked circuit 300 is connected to the segmentation circuit 200, the pulse generation circuit 400, and the output terminal XOUT of the crystal oscillator 100, respectively. The delay phase-locked circuit 300 uses the pull-down pulse signal DP as the enable signal CLK.

[0053] When there is no pull-down pulse signal DP to enable triggering, the delay-locked loop circuit 300 delays the first square wave signal Vs according to the previously fixed delay time, so as to output a second square wave signal Vd whose rising edge coincides with the valley of the output signal of the crystal oscillator 100. (For example: such as...) Figure 2 As shown, initially, when the power is first turned on, since the input signal and output signal are out of phase and the input signal is at the same frequency as the first square wave signal Vs, delaying the first square wave signal Vs by 1 / 4 period of the input signal will allow it to coincide with the trough of the output signal. Then, the pulse generation circuit 400 generates a pull-down pulse signal DP at the rising edge of the second square wave signal Vd and a pull-up pulse signal UP at the falling edge of the second square wave signal Vd. The driving circuit 500 pulls up the output signal when it receives the pull-up pulse signal UP and pulls down the output signal when it receives the pull-down pulse signal DP, thereby injecting energy into the troughs and peaks of the output signal and reducing phase noise.

[0054] When an enable signal DP is applied, the delay-locked loop circuit 300 captures the phase of the output signal's trough and controls the delay time based on the phase relationship between the pull-down pulse signal DP and the output signal. Figure 3As shown, if the pull-down pulse signal DP leads the output signal trough, that is, the rising edge of the second square wave signal Vd leads the output signal trough (the pulse generation module generates the pull-down pulse signal DP at the rising edge of the second square wave signal Vd), the delay time of the first square wave signal Vs is increased, and the next second square wave signal Vd is output. Figure 3 As shown, if the pull-down pulse signal DP lags behind the output signal trough, that is, when the rising edge of the second square wave signal Vd lags behind the output signal trough, the delay time is reduced, and the next second square wave signal Vd is output. This dynamically locks the rising edge of the second square wave and the output signal trough, thereby effectively resisting the influence of PVT on the injection time, thereby improving the energy injection efficiency, reducing the phase noise caused by injection, reducing the distortion of the output signal caused by energy injection, and reducing the frequency and duty cycle jitter of the first square wave signal Vs.

[0055] like Figure 2 As shown, the delay-locked loop circuit 300 includes: a dynamic comparator 310, an up-down counter 320, a data selector 330, and a delay circuit 340; the delay circuit 340 is connected to the segmentation circuit 200 and is used to delay the first square wave signal Vs; the dynamic comparator 310 is connected to the output terminal of the crystal oscillator 100 and the pulse generation circuit 400 respectively, and is used to compare the phase of the pull-down pulse signal DP generated by the pulse generation circuit 400 with the phase of the valley of the output signal of the crystal oscillator, and output a first signal according to the comparison result; the up-down counter 320 is connected to the dynamic comparator 310 and is used to perform up-down counting according to the first signal; the data selector 330 is connected to the up-down counter 320 and is used to control the delay time of the first square wave signal Vs according to the counting result Count to output a second square wave signal Vd;

[0056] Specifically, such as Figure 5 As shown, the positive input terminal of the dynamic comparator 310 is grounded, the inverting input terminal of the dynamic comparator 310 is connected to the output terminal of the crystal oscillator 100, the enable terminal of the dynamic comparator 310 is connected to the pulse generation circuit 400, and the output terminal P1 of the dynamic comparator 310 is connected to the up / down counter 320. The enable terminal of the dynamic comparator 310 is triggered by a falling edge.

[0057] like Figure 4As shown in (a), when the pulse generation circuit 400 outputs a pull-down pulse signal DP, the driving circuit 500 instantly pulls the output signal down to zero potential. If the pull-down pulse signal DP leads the output signal trough at this time, then after a short period of time, when the pull-down pulse signal DP shows a falling edge, the voltage of the crystal oscillator 100 output signal will be less than zero potential, and the dynamic comparator 310 outputs a high level to the up / down counter 320. When the up / down counter 320 receives the high level, it increments the count by one. The data selector 330 decodes the count result Count and selects the output terminal with the larger number connected to the delay circuit 340, that is, increases the delay time of the first square wave signal Vs, and outputs the second square wave signal Vd. This ensures that the rising edge of the second square wave signal Vd is precisely aligned with the trough of the output signal.

[0058] like Figure 4 As shown in (b), when the pulse generation circuit 400 outputs a pull-down pulse signal DP, the driving circuit 500 instantly pulls the output signal down to zero potential. If the pull-down pulse signal DP lags behind the output signal trough at this time, then after a short period of time, i.e., when the pull-down pulse signal DP has a falling edge, the voltage of the crystal oscillator 100 output signal will be greater than zero potential, and the dynamic comparator 310 outputs a low level to the up / down counter 320. When the up / down counter 320 receives the low level, it decrements the count by one. The data selector 330 decodes the count result Count and selects the output terminal with the smaller number connected to the delay circuit 340, i.e., reduces the delay time of the first square wave signal Vs, and outputs the second square wave signal Vd. This ensures that the rising edge of the second square wave signal Vd is precisely aligned with the trough of the output signal.

[0059] The up / down counter 320 and the data selector 330 use digital units, and the transistor structure in digital units is the same. Therefore, using different process nodes will not affect the circuit structure, thus facilitating process migration. Furthermore, the up / down counter 320 and the data selector 330 do not require capacitors, thereby reducing the circuit area.

[0060] In one embodiment, such as Figure 5 As shown, the input terminal of the up-down counter 320 is connected to the dynamic comparator 310, the enable terminal of the up-down counter 320 is connected to the pulse generation circuit 400, and the output terminal of the up-down counter 320 is connected to the data selector 330.

[0061] Specifically, the pulse generation circuit 400 is connected to the dynamic comparator 310 and the up-down counter 320 respectively. When the pulse generation circuit 400 outputs the pull-down pulse signal DP, the up-down counter 320 performs up-down calculations according to the first signal output by the dynamic comparator 310 and outputs the counting result Count to the data selector 330.

[0062] Taking a four-bit up / down counter 320 as an example, the four-bit up / down counter 320 includes four ports and can represent 16 binary numbers from 0 to 15. When the dynamic comparator 310 outputs a high level, the count value of the four-bit up / down counter 320 automatically increments by one each time the pull-down pulse signal DP arrives. When the dynamic comparator 310 outputs a low level, the count value of the four-bit up / down counter 320 automatically decrements by one each time the pull-down pulse signal DP arrives.

[0063] In one embodiment, such as Figure 5 As shown, the delay circuit 340 includes a plurality of delay units 341 connected in series. The delay units 341 are used to delay the first square wave signal Vs to obtain the second square wave signal Vd. The delay unit includes a plurality of inverters connected in series (e.g., inverter X1), and the ground terminal of the inverter is grounded through a current source (e.g., current source S1).

[0064] Specifically, such as Figure 5 As shown, the delay circuit 340 consists of several delay units 341, each providing a fixed delay time. Each delay unit 341 is composed of two current-starved inverters connected in series. The delay time of a single delay unit can be controlled by controlling the magnitude of the current from the current source connected to the ground terminal of the inverter. It should be noted that the total delay time of the delay circuit 340 is greater than one-quarter of the output signal's cycle time; that is, the total delay time of the delay circuit 340 is greater than the maximum delay time required for the rising edge of the second square wave signal Vd to align with the trough of the output signal.

[0065] The output of each delay unit 341 corresponds one-to-one with the output of the data selector 330. Taking the sixteen-bit data selector 330 as an example... Figure 4As shown, each delay unit 341 provides a fixed delay time (0.5µs), and the delay circuit 340 can provide a maximum delay time of 8µs. For a 32.768kHz crystal oscillator, one cycle time is 30.5µs, and a quarter cycle time is 7.625µs (the maximum delay time required for the rising edge of the second square wave signal Vd to align with the valley of the output signal). The delay time provided by the delay circuit 340 is sufficient to meet the requirements. The delay circuit 340 can provide 16 output selections, D0, D1...D15, corresponding to the 16 data terminals of the data selector 330. The larger the number, the longer the delay time. It should be noted that the data selector 330 is not limited to a 16-bit data selector 330. If the up / down counter 320 is an N-bit up / down counter 320, then the data selector 330 is a 2^N-bit data selector 330, specifically set according to the actual situation.

[0066] In one embodiment, the driving circuit 500 includes: a first switch K1 and a second switch K2; the control terminal of the first switch K1 receives the pull-up pulse signal UP, the first terminal of the first switch K1 is connected to the power supply voltage, the second terminal of the first switch K1 is connected to the first terminal of the second switch K2 and the output terminal of the crystal oscillator 100, and the second terminal of the second switch K2 is grounded.

[0067] Specifically, when the control terminal of the first switch K1 receives the pull-up pulse signal UP, the first switch K1 closes, and the output signal of the crystal oscillator 100 is instantly pulled high to the power supply voltage; when the control terminal of the second switch K2 receives the pull-down pulse signal DP, the second switch K2 closes, and the output signal of the crystal oscillator 100 is instantly pulled low to zero potential (ground). Under the premise that the delay-locked loop circuit 300 aligns the rising edge of the first square wave signal Vs with the trough of the output signal, that is, under the premise that the pull-down pulse signal DP is aligned with the trough of the output signal, the pull-up pulse signal UP automatically aligns with the peak of the output signal. By pulling the output signal high to the power supply voltage when the pull-up pulse signal UP is received, and pulling the output signal low to zero potential when the pull-down pulse signal DP is received, energy is released at the trough of the output signal and injected at the peak of the output signal, thereby improving energy injection efficiency.

[0068] like Figure 7 As shown, the present invention also provides a crystal oscillation method based on mixed signals, comprising:

[0069] S100, the input signal of the crystal oscillator 100 is divided into a first square wave signal Vs of the same frequency by the splitting circuit 200;

[0070] The input signal (sine wave) of the crystal oscillator 100 is divided into a first square wave signal Vs of the same frequency by the splitting circuit 200. This is specifically described in an embodiment of a crystal oscillator circuit based on mixed signals, and will not be repeated here.

[0071] S200: The first square wave signal is delayed by the delay circuit 340. This is specifically described in an embodiment of a crystal oscillator circuit based on mixed signals, and will not be repeated here.

[0072] S300: When the pull-down pulse signal DP generated by the pulse generation circuit is detected by the dynamic comparator 310, the phase of the pull-down pulse signal DP is compared with the phase of the valley of the output signal, and a first signal is output according to the comparison result; as described in an embodiment of a crystal oscillator circuit based on mixed signals, it will not be repeated here.

[0073] In one embodiment, step S300 includes:

[0074] S310. If the output signal of the crystal oscillator 100 is greater than zero potential when the pull-down pulse signal DP arrives, the first signal is at a low level, that is, a low level is output to the up / down counter 320; if the output signal of the crystal oscillator 100 is less than zero potential when the pull-down pulse signal DP arrives, the first signal is at a high level, that is, a high level is output to the up / down counter 320. This is specifically illustrated in an embodiment of a crystal oscillator circuit based on mixed signals, and will not be repeated here.

[0075] S400, The up-down counter 320 performs up-down counting based on the first signal; specifically as described in an embodiment of a crystal oscillator circuit based on mixed signals, which will not be repeated here.

[0076] S500, the delay time of the first square wave signal Vs is controlled by the data selector 330 according to the counting result Count to output the second square wave signal Vd; as described in an embodiment of a crystal oscillator circuit based on mixed signals, it will not be repeated here.

[0077] S600, the pulse generation circuit 400 generates a next pull-down pulse signal DP at the rising edge of the second square wave signal Vd and a next pull-up pulse signal UP at the falling edge of the second square wave signal Vd; specifically as described in an embodiment of a crystal oscillator circuit based on mixed signals, which will not be repeated here.

[0078] S700: The output signal is pulled up according to the pull-up pulse signal UP by the driving circuit, and the output signal is pulled down according to the pull-down pulse signal DP. This is specifically described in an embodiment of a mixed-signal crystal oscillator circuit, and will not be repeated here.

[0079] In summary, the present invention provides a mixed-signal-based crystal oscillator circuit comprising a crystal oscillator 100, a segmentation circuit 200, a dynamic comparator 310, an up / down counter 320, a data selector 330, a delay circuit 340, a pulse generator circuit 400, and a drive circuit 500. The segmentation circuit 200 is connected to the input terminal of the crystal oscillator 100 and is used to segment the input signal of the crystal oscillator 100 into a first square wave signal of the same frequency. The delay circuit 340 is connected to the segmentation circuit 200 and is used to delay the first square wave signal. The dynamic comparator 310 is connected to both the output terminal of the crystal oscillator 100 and the pulse generator circuit, and is used to compare the pull-down pulse signal generated by the pulse generator circuit 400 with the valley of the output signal of the crystal oscillator 100. The phase of the first square wave signal is determined, and a first signal is output based on the comparison result. The up / down counter 320 is connected to the dynamic comparator 310 and is used to perform up / down counting based on the first signal. The data selector 330 is connected to the up / down counter 320 and the delay circuit 340 respectively, and is used to control the delay time of the first square wave signal based on the counting result to output a second square wave signal. The pulse generation circuit 400 is connected to the data selector 330 and is used to generate a pull-down pulse signal on the rising edge of the second square wave signal and a pull-up pulse signal on the falling edge of the second square wave signal. The drive circuit 500 is connected to the pulse generation circuit 400 and is used to perform pull-up when receiving the pull-up pulse signal and pull-down when receiving the pull-down pulse signal. The present invention uses the up-down counter 320 to count according to the first signal, and uses the data selector 330 and the delay circuit 340 to control the delay time of the first square wave signal according to the counting result, so that the pull-up pulse signal is aligned with the valley of the output signal of the crystal oscillator 100, thereby reducing phase noise and improving energy injection efficiency, while reducing circuit area and facilitating process migration.

[0080] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A crystal oscillator circuit based on mixed signals, characterized in that, include: Crystal oscillator, switching circuit, dynamic comparator, up / down counter, data selector, delay circuit, pulse generator circuit, and drive circuit; The splitting circuit is connected to the input terminal of the crystal oscillator and is used to split the input signal of the crystal oscillator into a first square wave signal of the same frequency. The delay circuit is connected to the segmentation circuit and is used to delay the first square wave signal; The dynamic comparator is connected to the output terminal of the crystal oscillator and the pulse generation circuit respectively, and is used to compare the phase of the pull-down pulse signal generated by the pulse generation circuit with the phase of the valley of the output signal of the crystal oscillator, and output a first signal according to the comparison result; The up-and-down counter is connected to the dynamic comparator and is used to perform up-and-down counting based on the first signal; The data selector is connected to the up / down counter and the delay circuit respectively, and is used to control the delay time of the first square wave signal according to the counting result to output the second square wave signal. The pulse generation circuit is connected to the data selector and is used to generate a pull-down pulse signal on the rising edge of the second square wave signal and a pull-up pulse signal on the falling edge of the second square wave signal. The driving circuit is connected to the pulse generating circuit and is used to pull up when receiving the pull-up pulse signal and pull down when receiving the pull-down pulse signal.

2. The crystal oscillator circuit based on mixed signals according to claim 1, characterized in that, The up / down counter is an N-bit up / down counter, and the data selector is a 2^N-bit data selector.

3. The crystal oscillator circuit based on mixed signals according to claim 1, characterized in that, The positive input terminal of the dynamic comparator is grounded, the inverting input terminal of the dynamic comparator is connected to the output terminal of the crystal oscillator, the enable terminal of the dynamic comparator is connected to the pulse generation circuit, and the output terminal of the dynamic comparator is connected to the up / down counter.

4. The crystal oscillator circuit based on mixed signals according to claim 1, characterized in that, The input terminal of the up-down counter is connected to the dynamic comparator, the enable terminal of the up-down counter is connected to the pulse generation circuit, and the output terminal of the up-down counter is connected to the data selector.

5. The crystal oscillator circuit based on mixed signals according to claim 1, characterized in that, The delay circuit includes several delay units connected in series, which are used to delay the first square wave signal to obtain the second square wave signal.

6. The crystal oscillator circuit based on mixed signals according to claim 5, characterized in that, The delay unit includes several inverters connected in series, and the ground terminal of the inverter is grounded through a current source.

7. The crystal oscillator circuit based on mixed signals according to claim 1, characterized in that, The driving circuit includes: a first switch and a second switch; The control terminal of the first switch receives the pull-up pulse signal, the first terminal of the first switch is connected to the power supply voltage, the second terminal of the first switch is connected to the first terminal of the second switch and the output terminal of the crystal oscillator, and the second terminal of the second switch is grounded.

8. The crystal oscillator circuit based on mixed signals according to claim 1, characterized in that, Also includes: The first resonant capacitor and the second resonant capacitor; The input terminal of the crystal oscillator is connected to one end of the first resonant capacitor, and the other end of the first resonant capacitor is grounded. The output terminal of the crystal oscillator is connected to one end of the second resonant capacitor, and the other end of the second resonant capacitor is grounded.

9. A crystal oscillation method based on mixed signals, characterized in that, The crystal oscillation method is based on the mixed-signal-based crystal oscillation circuit according to any one of claims 1-8, and the method includes: The input signal of the crystal oscillator is divided into a first square wave signal of the same frequency by a splitting circuit; The first square wave signal is delayed by a delay circuit; When a pull-down pulse signal generated by the pulse generation circuit is detected by the dynamic comparator, the phase of the pull-down pulse signal is compared with the phase of the valley of the output signal of the crystal oscillator, and a first signal is output according to the comparison result. The count is incremented or decremented based on the first signal using an up-and-down counter. The delay time of the first square wave signal is controlled by the data selector according to the counting result to output the second square wave signal; The pulse generation circuit generates the next pull-down pulse signal on the rising edge of the second square wave signal and the next pull-up pulse signal on the falling edge of the second square wave signal. The output signal is pulled up by the drive circuit according to the pull-up pulse signal, and the output signal is pulled down according to the pull-down pulse signal.

10. The crystal oscillation method based on mixed signals according to claim 9, characterized in that, The step of comparing the phase of the pull-down pulse signal generated by the pulse generation circuit with the phase of the valley of the crystal oscillator's output signal when the pull-down pulse signal is detected by the dynamic comparator includes: When the output signal of the crystal oscillator is greater than zero potential, the first signal is at a low level; when the output signal of the crystal oscillator is less than zero potential, the first signal is at a high level.

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