Circuit structure and control adjustment method for adjusting Hall effect detection accuracy

Abstract

This invention relates to a circuit structure for adjusting the accuracy of Hall effect detection. The circuit structure includes: a power-on reset module for generating a power-on reset signal; a frequency divider processing module connected to the power-on reset module and an oscillation module for generating a frequency division signal; a combinational logic processing module connected to the frequency divider processing module for generating output signals at different frequency states; a fuse control processing module connected to the power-on reset module for controlling the fuse programming logic of the circuit structure; and a fuse logic processing module connected to the power-on reset module, the combinational logic processing module, and the fuse control processing module for generating fuse logic signals at the required operating frequency of the circuit structure. This invention also relates to a corresponding method. The circuit structure and adjustment method for adjusting the accuracy of Hall effect detection using this invention are simple to operate, cost-effective, and offer flexible standby time adjustment, meeting the needs of customers in various applications.

Description

Technical Field

[0001] This invention relates to the field of Hall circuit technology, and more particularly to the field of Hall circuit accuracy detection technology, specifically to a circuit structure and control method for adjusting the accuracy of Hall detection. Background Technology

[0002] Hall effect circuits, as non-contact detection circuits, are widely used in electromagnetic measurement, non-electrical quantity measurement, and magnetically driven electronic switches due to their sensitivity to magnetic fields, simple structure, and small size. The required detection accuracy of Hall effect chips varies across these applications. For example, high-precision automotive Hall effect sensors used to detect wheel speed require a higher number of magnetic field detections within a given time compared to rope skipping applications. When used for rope skipping counting, the required magnetic field detection accuracy decreases, but low static power consumption is still necessary. To meet the needs of different applications, a circuit was designed that adjusts the standby time via a fuse while keeping the operating time constant, thereby adjusting the duty cycle (working / standby) to regulate magnetic field detection accuracy. This allows for high-precision magnetic field detection, while applications with lower accuracy requirements can reduce static power consumption. However, existing technologies do not provide a solution for adjusting the working-standby duty cycle. Adjusting this parameter would require redesigning the circuit and fabricating a new chip, which is costly, time-consuming, and inconvenient. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a circuit structure and control adjustment method for adjusting the accuracy of Hall detection that is simple to operate and low in cost.

[0004] To achieve the above objectives, the circuit structure and control method for adjusting the Hall detection accuracy of the present invention are as follows:

[0005] The main feature of this circuit structure for adjusting the accuracy of Hall detection is that the circuit structure includes:

[0006] The power-on reset module is used to generate a power-on reset signal;

[0007] The frequency divider processing module is connected to the power-on reset module and the oscillation module, and is used to generate the frequency division signal of the circuit structure.

[0008] A combinational logic processing module, connected to the power-on reset module and the frequency divider processing module, is used to generate output signals of the circuit structure under different frequency states.

[0009] A fuse control processing module, connected to the power-on reset module, is used to control the fuse programming logic of the circuit structure; and

[0010] The fuse logic processing module is connected to the power-on reset module, the combinational logic processing module, and the fuse control processing module, and is used to generate fuse logic signals at the operating frequency required by the circuit structure.

[0011] Preferably, the oscillation module specifically comprises:

[0012] Used to generate a clock signal at a preset frequency, and the clock signal is used as the input signal of the frequency divider processing module.

[0013] Preferably, the frequency divider processing module is:

[0014] The system is equipped with a preset number of Class D flip-flops, which are interconnected with each other. The set terminal of each Class D flip-flop is connected to the power-on reset module to receive the reset signal generated by the power-on reset module.

[0015] Preferably, the output signal frequency of the frequency divider processing module is divided by two n times, where n is the number of the Class D flip-flops.

[0016] Preferably, the combinational logic processing module includes:

[0017] The circuit is equipped with a preset number of logic gate processing circuits and a transmission gate structure connected to the logic gates. It is used to generate a group of fuse logic output signals that matches the preset number of transmission gate structures. By changing the state of the fuse bits, the output signals of the circuit structure under different frequency states can be obtained.

[0018] Preferably, by changing the frequency of the output signal, the duty cycle of the output signal is changed, thereby obtaining duty cycle output signals under different duty cycle conditions.

[0019] Preferably, the duty cycle output signal is used to control the on-time and sleep time of the Hall sensor. When the on-time of the Hall sensor remains unchanged, the sleep time of the Hall sensor will be adjusted by the fuse position to meet the Hall application requirements under different conditions.

[0020] Preferably, the fuse control processing module:

[0021] It includes a preset number of Class D flip-flops, which are interconnected with each other, and the input terminals of each Class D flip-flop are connected to the power-on reset module to receive the reset signal generated by the power-on reset module.

[0022] Preferably, the fuse logic processing module:

[0023] It includes a preset number of fuse logic units, and each fuse logic unit is equipped with a preset number of logic gate processing circuits and NMOS field-effect transistors, which are used to combine and output the clock signal required by the transmission gate structure.

[0024] Preferably, the fuse logic processing module further includes a preset number of fuse structures, wherein the fuse structures are configured as resistors matching the number of fuse logic units, and each of the resistors is connected to the NMOS field-effect transistor.

[0025] The method for controlling and adjusting the accuracy of Hall effect detection using the circuit structure described above is characterized by the following steps:

[0026] (1) Input a signal containing a power-on reset signal and a frequency signal into the circuit structure described above;

[0027] (2) The frequency divider processing module, the fuse control processing module and the fuse logic processing module receive the input signal and execute the logic processing of the corresponding modules.

[0028] (3) The combinational logic processing module performs logical combination processing on the output signal obtained after being processed by the frequency divider processing module and the fuse logic processing module to generate the total circuit output signal under the current frequency state.

[0029] Preferably, step (2) includes:

[0030] The frequency divider processing module simultaneously receives the power-on reset signal and the frequency signal, and performs n-fold frequency division processing on the frequency signal.

[0031] The fuse control processing module receives the power-on reset signal and generates the corresponding fuse programming logic for the current circuit structure based on the triggering changes of each Class D flip-flop in the fuse control processing module.

[0032] The fuse logic processing module receives the power-on reset signal and the output signal processed by the fuse control processing module. Based on the changes in the state of the fuse bits corresponding to each fuse structure in the fuse programming logic of the fuse logic processing module, it generates corresponding fuse logic control signals to adjust the operating frequency of the current circuit structure.

[0033] Preferably, step (3) includes:

[0034] The combinational logic processing module receives the frequency division signal generated by the frequency divider processing module and the fuse logic control signal generated by the fuse logic processing module, and generates the total circuit output signal at the current preset frequency through AND-NOT logic gates, NOR logic gates and transmission gate structures.

[0035] The circuit structure and control method for adjusting Hall effect detection accuracy adopted in this invention offer advantages over existing technologies. The Hall effect circuit's operating frequency is adjustable, and through fuse control, the fuse can be programmed during the measurement phase to adjust the duty cycle (working or standby) according to the varying magnetic field detection accuracy requirements in different applications. This allows for multiple functions on a single chip. Compared to existing technologies, this method is simpler to operate, saves costs, and meets the needs of customers in various applications. By adjusting the frequency of the OUT signal through the fuse—keeping the working time constant while adjusting the standby time—different working-standby duty cycle signals can be obtained, avoiding re-fabrication and saving time and costs. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the frequency divider processing module of the circuit structure for adjusting the Hall detection accuracy of the present invention.

[0037] Figure 2 This is a schematic diagram of the combinational logic processing module of the circuit structure for adjusting the Hall detection accuracy of the present invention.

[0038] Figure 3 This is a schematic diagram of the fuse control processing module of the circuit structure for adjusting the Hall detection accuracy of the present invention.

[0039] Figure 4 This is a schematic diagram of the fuse logic processing module of the circuit structure for adjusting the Hall detection accuracy of the present invention. Detailed Implementation

[0040] To more clearly describe the technical content of the present invention, the following description is provided in conjunction with specific embodiments.

[0041] Before detailing embodiments of the invention, it should be noted that, hereinafter, relational terms such as "first" and "second" are used merely to distinguish one entity or action from another, and do not necessarily require or imply any actual such relationship or order between such entities or actions. The terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, thereby causing a process, method, article, or apparatus that comprises a list of elements to include not only those elements but also other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0042] The circuit structure for adjusting the accuracy of Hall effect detection includes:

[0043] The power-on reset module is used to generate a power-on reset signal;

[0044] The frequency divider processing module is connected to the power-on reset module and the oscillation module OSC, and is used to generate the frequency division signal of the circuit structure.

[0045] A combinational logic processing module, connected to the power-on reset module and the frequency divider processing module, is used to generate output signals of the circuit structure under different frequency states.

[0046] A fuse control processing module, connected to the power-on reset module, is used to control the fuse programming logic of the circuit structure; and

[0047] The fuse logic processing module is connected to the power-on reset module, the combinational logic processing module, and the fuse control processing module, and is used to generate fuse logic signals at the operating frequency required by the circuit structure.

[0048] In a preferred embodiment of the present invention, the oscillation module OSC is:

[0049] Used to generate a clock signal at a preset frequency, and the clock signal is used as the input signal of the frequency divider processing module.

[0050] In a preferred embodiment of the present invention, the frequency divider processing module is as follows:

[0051] The system is equipped with a preset number of Class D flip-flops, which are interconnected with each other. The set terminal of each Class D flip-flop is connected to the power-on reset module to receive the reset signal generated by the power-on reset module.

[0052] In a preferred embodiment of the present invention, the output signal frequency of the frequency divider processing module is subjected to n-fold frequency division processing, where n is the number of the Class D flip-flops.

[0053] Please see Figure 1 As shown, in practical applications, the power-on reset module (POR) works as follows: when the power supply voltage is powered on, R changes from "GND" to "VCC". R serves as the Reset signal for the triggers of the frequency divider processing module and the fuse control processing module. When R is "GND", the output terminals of the triggers of the above modules are cleared to zero. When R is "VCC", the trigger input is valid.

[0054] The aforementioned oscillation module (OSC) is used to generate a CLK signal with a frequency of f as the input signal for the trigger of the frequency division processing module.

[0055] In practical applications, the frequency divider processing module is used to divide the frequency-divided signal generated by the oscillation module. After passing through 8 flip-flops, the OUTP terminal generates f1-f8 respectively, and the OUTN terminal generates e1-e8 respectively. Each time the signal passes through a frequency divider, the frequency of the signal at the OUTP terminal is divided by 2, that is, f1 = CLK / 2, f2 = f1 / 2 ... f8 = f7 / 2 = CLK / 2 8 .

[0056] In a specific embodiment of the present invention, the frequency divider processing module employs eight Class D flip-flops. The CP input of the first Class D flip-flop is used to connect to the CLK signal generated by the oscillation module. The SET inputs of the first to eighth Class D flip-flops are all used to connect to the reset signal R generated by the power-on reset module. The IN input and OUTN output of the first Class D flip-flop are both connected to the CP input of the second Class D flip-flop to generate the frequency signal e1. The OUTP output of the first Class D flip-flop is used to generate the frequency signal f1. The IN input and OUTN output of the second Class D flip-flop are connected to the CP input of the second Class D flip-flop. The output terminals are all connected to the CP input terminal of the third Class D flip-flop to generate frequency signal e2, and the OUTP output terminal of the second Class D flip-flop is used to generate frequency signal f2; the IN input terminal and OUTN output terminal of the third Class D flip-flop are both connected to the CP input terminal of the fourth Class D flip-flop to generate frequency signal e3, and the OUTP output terminal of the third Class D flip-flop is used to generate frequency signal f3; the IN input terminal and OUTN output terminal of the fourth Class D flip-flop are both connected to the CP input terminal of the fifth Class D flip-flop to generate frequency signal e4, and the OUTP output terminal of the fourth Class D flip-flop is used to generate frequency signal f4; the IN input terminal and OUTN output terminal of the fifth Class D flip-flop are both connected to the CP input terminal of the sixth Class D flip-flop to generate frequency signal e5, and the OUTP output terminal of the fifth Class D flip-flop is used to generate frequency signal f5; the IN input terminal and OUTN output terminal of the sixth Class D flip-flop are both connected to the CP input terminal of the seventh Class D flip-flop to generate frequency signal e6, and the OUTP output terminal of the sixth Class D flip-flop is used to generate frequency signal f1; the IN input terminal of the seventh Class D flip-flop... The input terminal and the OUTN output terminal are both connected to the CP input terminal of the eighth class D flip-flop to generate the frequency signal e7. The OUTP output terminal of the seventh class D flip-flop is used to generate the frequency signal f7. The IN input terminal of the eighth class D flip-flop is connected to the OUTN output terminal of the eighth class D flip-flop to generate the frequency signal e8. The OUTP output terminal of the eighth class D flip-flop is used to generate the frequency signal f8.

[0057] In practical applications, the number of Class D flip-flops in the frequency divider processing module can be selected adaptively according to the user's requirements for the output frequency of the combinational logic processing module. The purpose of this invention is not to protect a specific preset value, but rather to select the specific logic.

[0058] In a preferred embodiment of the present invention, the combinational logic processing module is described as follows:

[0059] It includes a preset number of logic gate processing circuits and a transmission gate structure connected to the logic gates, used to generate a fuse logic output signal group that matches the preset number of transmission gate structures, and to obtain the output signal of the circuit structure under different frequency states by changing the state of the fuse bits.

[0060] In a preferred embodiment of the present invention, the duty cycle of the output signal is changed by changing the frequency of the output signal, thereby obtaining output signals with different duty cycles under different duty cycle conditions.

[0061] In a preferred embodiment of the present invention, the duty cycle output signal is used to control the on-time and sleep time of the Hall sensor. When the on-time of the Hall sensor remains unchanged, the sleep time of the Hall sensor will be adjusted by adjusting the fuse position to meet the Hall application requirements under different conditions.

[0062] Please see Figure 2 As shown, in a specific embodiment of the present invention, the combinational logic processing module is specifically configured with:

[0063] The first NAND gate, wherein its A input is used to connect to the frequency signal e8 of the eighth Class D flip-flop, its B input is used to connect to the frequency signal f7 of the seventh Class D flip-flop, its output is connected to the A input of the first NOR gate, its B input is used to connect to the frequency signal e6 of the sixth Class D flip-flop, its output is used to connect to the first input of the first transmission gate structure TRAN1, its second input is used to connect to the frequency signal e6 of the sixth Class D flip-flop, and its first and second control terminals are used to input a pair of fuse logic signals C1 and C2 with opposite phases. The output of the first transmission gate structure TRAN1 is connected to the A input of the second NAND gate. The B input of the second NAND gate is used to input the frequency signal f5 of the fifth Class D flip-flop. The output of the second NAND gate is connected to the A input of the second NOR gate. The B input of the second NOR gate is used to input the frequency signal e4 of the fourth Class D flip-flop. The output of the second NOR gate is used to input the first input of the second transmission gate structure TRAN2. The second input of the second transmission gate structure TRAN2 is used to input the frequency signal e4 of the fourth Class D flip-flop. The first and second control terminals of the second transmission gate structure TRAN2 are used to input a pair of fuse logic signals C2 with opposite phases and a AND gate. The output of the second transmission gate structure TRAN2 is connected to the A input of the third NAND gate. The B input of the third NAND gate is used to input the frequency signal f3 of the third Class D flip-flop. The output of the third NAND gate is connected to the A input of the third NOR gate. The B input of the third NOR gate is used to input the frequency signal e2 of the second Class D flip-flop. The output of the third NOR gate is used to input the first input of the third transmission gate structure TRAN3. The second input of the third transmission gate structure TRAN3 is used to input the frequency signal e2 of the second Class D flip-flop. The first and second control terminals of the third transmission gate structure TRAN3 are used to input a pair of fuse logic signals C3 with opposite phases. The output of the third transmission gate structure TRAN3 is connected to the input of the NOT gate, and the output of the NOT gate is used to output OUT signals of different frequencies.

[0064] In practical applications, the combinational logic processing modules C1, C2, and C3, as well as This is the output of the fuse logic, and C1 is... These are a pair of signals with opposite phases, i.e., C1 is "VCC". C1 is "GND". For "VCC"; C2 and As a pair of signals with opposite phases, C3 and These are a pair of opposite signals. The truth table for C1, C2, C3, and OUT is as follows: "1" represents the potential as "VCC", and "0" represents the potential as "GND". Table 1 below shows the changes in the frequency and duty cycle of the output terminal OUT when the fuse bit state is changed:

[0065] Table 1

[0066] C1 C2 C3 OUT(f frequency) Working / Standby Duty Cycle 0 0 0 <![CDATA[1 / 2 8 *(CLK)]]> 1 / 32(3.125％) 1 0 0 <![CDATA[1 / 2 6 *(CLK)]]> 1 / 16(6.25％) 0 1 0 <![CDATA[1 / 2 4 *(CLK)]]> 1 / 8(12.5％) 0 1 1 <![CDATA[1 / 2 2 *(CLK)]]> 1 / 4(25％)

[0067] As shown in Table 1, four different frequencies of OUT signals can be obtained by changing the state of the fuse bit. Since the high level time of OUT is the high level of f1, the duty cycle of OUT can be changed by changing the frequency of OUT, thus obtaining OUT signals with different duty cycles. This output can be used as a control Hall awake-sleep, that is, the awake time remains unchanged, and the sleep time can be adjusted by the fuse bit to meet the needs of different Hall applications.

[0068] In a preferred embodiment of the present invention, the fuse control processing module is described as follows:

[0069] It includes a preset number of Class D flip-flops, which are interconnected with each other, and the input terminals of each Class D flip-flop are connected to the power-on reset module to receive the reset signal generated by the power-on reset module.

[0070] Please see Figure 3 As shown, in a specific embodiment of the present invention, the fuse control processing module is provided with four Class D flip-flops. The D input of the first Class D flip-flop is used to connect to the VCC signal, the OUTP output of the first Class D flip-flop is used to output the OUTP1 signal, the OUTN output of the first Class D flip-flop is used to output the OUTN1 signal, and the OUTN output of the first Class D flip-flop is connected to the D input of the second Class D flip-flop. The OUTP output of the second Class D flip-flop is used to output the OUTP2 signal and is connected to the D input of the second Class D flip-flop, and the OUTN output of the second Class D flip-flop is used to output the OUTN2 signal. The OUTP output of the third Class D flip-flop is used to output the OUTP3 signal and is connected to the D input of the fourth Class D flip-flop, and the OUTN output of the third Class D flip-flop is used to output the OUTN3 signal. The OUTP output of the fourth Class D flip-flop is used to output the OUTP4 signal. The OUTN output terminal of the Class D flip-flop is used to output the OUTN4 signal; wherein, the CK input terminal of the first Class D flip-flop to the CK input terminal of the fourth Class D flip-flop are all used to connect the FUSE_IN signal, and the R input terminal of the first Class D flip-flop to the R input terminal of the fourth Class D flip-flop are all used to connect the reset signal R output by the power-on reset module.

[0071] In practical applications, fuse control consists of four flip-flops, each triggered on the rising edge. The D input of the first flip-flop is "VCC", and the CK input of the third flip-flop is the FUSE_IN input. When the flip-flop detects the rising edge of FUSE_IN, it outputs the D signal to the OUTP terminal. After power-on reset, if there is no FUSE_IN input, the default output of the OUTP terminal is "GND". On the first rising edge of FUSE_IN, OUTP1 = "VCC", OUTP2 = "VCC", OUTP3 = "GND", OUTP4 = "GND". On the second rising edge of FUSE_IN, OUTP1 = "VCC", OUTP2 = "GND", OUTP3 = "VCC", OUTP4 = "GND". On the third rising edge of FUSE_IN, OUTP1 = "VCC", OUTP2 = "GND", OUTP3 = "GND", OUTP4 = "VCC". That is, starting from the second rising edge, the flip-flop passes "VCC" from OUTP2 sequentially. This allows us to obtain the states in the truth table of C1 / C2 / C3.

[0072] In a preferred embodiment of the present invention, the fuse logic processing module is as follows:

[0073] It includes a preset number of fuse logic units, and each fuse logic unit is equipped with a preset number of logic gate processing circuits and NMOS field-effect transistors, which are used to combine and output the clock signal required by the transmission gate structure.

[0074] In a preferred embodiment of the present invention, the fuse logic processing module further includes a preset number of fuse structures, wherein the fuse structures are configured as resistors matching the number of fuse logic units, and each of the resistors is connected to the NMOS field-effect transistor.

[0075] Please see Figure 4 As shown, in a specific embodiment of the present invention, the fuse logic processing module is provided with three fuse logic units, each of which is provided with a logic gate processing circuit, an NMOS field-effect transistor, and a resistor.

[0076] The first fuse logic unit specifically includes: a first NAND gate, whose A input is used to receive the reset signal R output by the power-on reset module; its B input is used to receive the OUTP2 signal of the second D-type flip-flop of the fuse control processing module; the output of the first NAND gate is connected to the input of the second NAND gate; the output of the second NAND gate is connected to the gate of the third NMOS transistor; the drain of the first NMOS transistor is connected between the first resistor and the B input of the second NAND gate; the source of the first NMOS transistor is grounded; the output of the second NAND gate is connected to the B input of the third NAND gate; the A input of the third NAND gate is used to receive the reset signal R output by the power-on reset module; and the A input of the second NAND gate is connected between the output of the third NAND gate and the A input of the fourth NAND gate; the B input of the fourth NAND gate is used to receive the OUTN2 signal of the second D-type flip-flop of the fuse control processing module; and the output of the fourth NAND gate is used to output a fuse logic signal C1. The fuse logic signal C1 is processed by an NAND gate to generate an output fuse logic signal.

[0077] The second fuse logic unit specifically includes: a first NAND gate, whose A input is used to receive the reset signal R output by the power-on reset module; its B input is used to receive the OUTP3 signal of the third Class D flip-flop of the fuse control processing module; the output of the first NAND gate is connected to the input of the second NAND gate; the output of the second NAND gate is connected to the gate of the second NMOS transistor; the drain of the second NMOS transistor is connected between the second resistor and the B input of the second NAND gate; the source of the second NMOS transistor is grounded; the output of the second NAND gate is connected to the B input of the third NAND gate; the A input of the third NAND gate is used to receive the reset signal R output by the power-on reset module; and the A input of the second NAND gate is connected between the output of the third NAND gate and the A input of the fourth NAND gate; the B input of the fourth NAND gate is used to receive the OUTN3 signal of the third Class D flip-flop of the fuse control processing module; and the output of the fourth NAND gate is used to output the fuse logic signal C2. The fuse logic signal C2 is processed by an NAND gate to generate the output fuse logic signal.

[0078] The third fuse logic unit specifically includes: a first NAND gate, whose A input is used to receive the reset signal R output by the power-on reset module; its B input is used to receive the OUTP4 signal of the fourth Class D flip-flop of the fuse control processing module; the output of the first NAND gate is connected to the input of the second NAND gate; the output of the second NAND gate is connected to the gate of the third NMOS transistor; the drain of the third NMOS transistor is connected between the third resistor and the B input of the second NAND gate; the source of the third NMOS transistor is grounded; the output of the second NAND gate is connected to the B input of the third NAND gate; the A input of the third NAND gate is used to receive the reset signal R output by the power-on reset module; and the A input of the second NAND gate is connected between the output of the third NAND gate and the A input of the fourth NAND gate; the B input of the fourth NAND gate is used to receive the OUTN4 signal of the fourth Class D flip-flop of the fuse control processing module; and the output of the fourth NAND gate is used to output the fuse logic signal C3. The fuse logic signal C3 is processed by an NOT gate to generate the output fuse logic signal.

[0079] In practical applications of this invention, the fuse structure is replaced by a resistor, and the fuse programming logic is determined by the fuse control module. By default, if the fuse is not blown, C1, C2, and C3 are set to "000".

[0080] The OUT output frequency is 1 / 2 8 ×(CLK), when OUTP2\OUTP3\OUTP4 are "VCC", "GND", and "GND" respectively, fuse 1 is blown, C1\C2\C3 are "100", and the OUT output frequency is 1 / 2. 6 ×(CLK); When OUTP2, OUTP3, and OUTP4 are "GND", "VCC", and "GND" respectively, fuse 2 is blown, C1, C2, and C3 are "010", and the OUT output frequency is 1 / 2. 6 ×(CLK); When OUTP2, OUTP3, and OUTP4 are respectively "GND", "GND", and "VCC", fuse 3 is blown, C1, C2, and C3 are "001", and the OUT output frequency is 1 / 2. 4 ×(CLK); The above structure allows for adjustment of the operating frequency. That is, the Hall circuit's operating time remains constant while the standby time is adjusted. To reduce static power consumption, simply lower the OUT signal frequency, decreasing the operating / standby duty cycle and increasing the standby time. Conversely, to achieve a higher detection frequency, select a higher OUT signal frequency, increasing the operating / standby duty cycle and decreasing the standby time.

[0081] The method for controlling and adjusting the accuracy of Hall effect detection using the circuit structure described above includes the following steps:

[0082] (1) Input a signal containing a power-on reset signal and a frequency signal into the circuit structure described above;

[0083] (2) The frequency divider processing module, the fuse control processing module and the fuse logic processing module receive the input signal and execute the logic processing of the corresponding modules.

[0084] (3) The combinational logic processing module performs logical combination processing on the output signal obtained after being processed by the frequency divider processing module and the fuse logic processing module to generate the total circuit output signal under the current frequency state.

[0085] In a preferred embodiment of the present invention, step (2) includes:

[0086] The frequency divider processing module simultaneously receives the power-on reset signal and the frequency signal, and performs n-fold frequency division processing on the frequency signal.

[0087] The fuse control processing module receives the power-on reset signal and generates the corresponding fuse programming logic for the current circuit structure based on the triggering changes of each Class D flip-flop in the fuse control processing module.

[0088] The fuse logic processing module receives the power-on reset signal and the output signal processed by the fuse control processing module. Based on the changes in the state of the fuse bits corresponding to each fuse structure in the fuse programming logic of the fuse logic processing module, it generates corresponding fuse logic control signals to adjust the operating frequency of the current circuit structure.

[0089] In a preferred embodiment of the present invention, step (3) includes:

[0090] The combinational logic processing module receives the frequency division signal generated by the frequency divider processing module and the fuse logic control signal generated by the fuse logic processing module, and generates the total circuit output signal at the current preset frequency through AND-NOT logic gates, NOR logic gates and transmission gate structures.

[0091] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

[0092] The circuit structure and control method for adjusting Hall effect detection accuracy adopted in this invention offer advantages over existing technologies. The Hall effect circuit's operating frequency is adjustable, and through fuse control, the fuse can be programmed during the measurement phase to adjust the duty cycle for either operation or standby, adapting to varying magnetic field detection accuracy requirements in different applications. This allows for multiple functions on a single chip. Compared to existing technologies, this method is simpler to operate, saves costs, and meets the needs of customers in various applications. The frequency of the OUT signal is adjusted via fuse control, maintaining a constant operating time while adjusting the standby time to obtain different operating-standby duty cycle signals. This avoids the need for re-fabrication, saving time and costs.

[0093] In this specification, the invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A circuit structure for adjusting the accuracy of Hall effect detection, characterized in that, The circuit structure includes: The power-on reset module is used to generate a power-on reset signal; The frequency divider processing module is connected to the power-on reset module and the oscillation module (OSC) and is used to generate the frequency division signal of the circuit structure and perform n-fold frequency division processing on the frequency division signal. The fuse control processing module is connected to the power-on reset module and includes a preset number of Class D flip-flops for receiving the power-on reset signal and controlling the fuse programming logic of the circuit structure according to the triggering changes of each Class D flip-flop. A fuse logic processing module, connected to the fuse control processing module, is used to generate fuse logic signals with the required operating frequency for the circuit structure based on the changes in the fuse bit states corresponding to each fuse structure in the fuse programming logic; and The combinational logic processing module is connected to the frequency divider processing module and the fuse logic processing module. It is used to receive the frequency division signal and the fuse logic signal, and change the state of each fuse bit through logic processing to generate the total output signal of the circuit.

2. The circuit structure for adjusting the Hall detection accuracy according to claim 1, characterized in that, The aforementioned oscillation module (OSC) is: Used to generate a clock signal at a preset frequency, and the clock signal is used as the input signal of the frequency divider processing module.

3. The circuit structure for adjusting the Hall detection accuracy according to claim 1, characterized in that, The frequency divider processing module is as follows: The system is equipped with a preset number of Class D flip-flops, which are interconnected with each other. The set terminal of each Class D flip-flop is connected to the power-on reset module to receive the reset signal generated by the power-on reset module.

4. The circuit structure for adjusting the Hall detection accuracy according to claim 3, characterized in that, The output signal frequency of the frequency divider processing module is divided by two n times, where n is the number of the Class D flip-flops.

5. The circuit structure for adjusting the Hall detection accuracy according to claim 1, characterized in that, The combinational logic processing module includes: A preset number of logic gate processing circuits and a transmission gate structure connected to the logic gates are used to generate a group of fuse logic output signals that matches the preset number of transmission gate structures, and to obtain the output signals of the circuit structure under different frequency states by changing the state of the fuse bits.

6. The circuit structure for adjusting the Hall detection accuracy according to claim 1, characterized in that, The fuse control processing module specifically includes: Each of the Class D flip-flops is interconnected, and the input of each Class D flip-flop is connected to the power-on reset module to receive the reset signal generated by the power-on reset module.

7. The circuit structure for adjusting the Hall detection accuracy according to claim 5, characterized in that, The aforementioned fuse logic processing module: It includes a preset number of fuse logic units, and each of the fuse logic units is provided with a preset number of logic gate processing circuits and NMOS field-effect transistors, which are used to combine and output the clock signal required by the transmission gate structure.

8. The circuit structure for adjusting the Hall detection accuracy according to claim 7, characterized in that, The fuse logic processing module further includes a preset number of fuse structures, wherein the fuse structures are configured as resistors matching the number of fuse logic units, and each resistor is connected to the NMOS field-effect transistor.

9. A method for controlling and adjusting the accuracy of Hall effect detection using the circuit structure described in any one of claims 1 to 8, characterized in that, Includes the following steps: (1) Input a signal containing a power-on reset signal and a frequency signal to the circuit structure described above; (2) The frequency divider processing module, the fuse control processing module and the fuse logic processing module receive the input signal and execute the logic processing of the corresponding modules; (3) The combinational logic processing module performs logic combination processing on the output signal obtained after processing by the frequency divider processing module and the fuse logic processing module to generate the total circuit output signal under the current frequency state. Step (2) includes: The frequency divider processing module simultaneously receives the power-on reset signal and the frequency signal, and performs n-fold frequency division processing on the frequency signal. The fuse control processing module receives the power-on reset signal and generates the corresponding fuse programming logic for the current circuit structure based on the triggering changes of each Class D flip-flop in the fuse control processing module. The fuse logic processing module receives the power-on reset signal and the output signal processed by the fuse control processing module. Based on the changes in the state of the fuse bits corresponding to each fuse structure in the fuse programming logic of the fuse logic processing module, it generates corresponding fuse logic control signals to adjust the operating frequency of the current circuit structure. The combinational logic processing module changes the state of each fuse bit through logic processing, thereby generating the total output signal of the circuit.

10. The method for controlling and adjusting the accuracy of Hall effect detection according to claim 9, characterized in that, Step (3) includes: The combinational logic processing module receives the frequency division signal generated by the frequency divider processing module and the fuse logic control signal generated by the fuse logic processing module, and generates the total circuit output signal at the current preset frequency through AND-NOT logic gates, NOR logic gates and transmission gate structures.

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