Analog-to-digital converters and chips

Abstract

This invention relates to the field of integrated circuit technology and discloses an analog-to-digital converter (ADC) and chip. The ADC includes: first and second passive switched-capacitor integrators; two capacitive ADC arrays; a control logic circuit for closing the first and second switch groups in the first passive switched-capacitor integrator to output a first residual voltage and closing the third and fourth switch groups in the second passive switched-capacitor integrator to output a second residual voltage when the capacitors in the arrays are reset; and a dual differential input comparator for receiving the sum of the first residual voltage and the input voltage of the current preset period as a first differential input signal, receiving the second residual voltage as a second differential input signal, and outputting a comparison result. The control logic circuit is also used to output multiple switch control signals to the capacitive ADC arrays according to the comparison result to output digital data of the current preset period, thereby effectively suppressing quantization noise in the signal band.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to an analog-to-digital converter and chip. Background Technology

[0002] Successive approximation analog-to-digital converters (ADCs) are widely used in various scenarios due to their low power consumption and high energy efficiency. However, various internal non-ideal factors and noises limit their achievable signal-to-noise ratio (SNR), with quantization noise being the most prominent. Oversampling and noise shaping techniques can effectively improve the in-band SNR of ADCs by constructing appropriate high-pass or band-pass noise transfer functions to shape quantization noise and comparator noise. However, to achieve good suppression of in-band noise, it is often necessary to use high-power active circuit modules in the noise shaping loop, which is not conducive to the implementation of low-power systems. Summary of the Invention

[0003] The purpose of this invention is to provide an analog-to-digital converter and chip that employs a second-order passive hybrid noise shaping technique. This technique uses two sets of passive switched-capacitor integrators to sample and integrate the residual voltage of the previous preset cycle. The outputs of the two integrators are fed into the input sampled signal of the current cycle through error feedback and forward addition, respectively, and then converted. This modulates the in-band quantization noise and comparator noise of the analog-to-digital converter to the high-frequency band, achieving a second-order high-pass noise shaping effect and suppressing correlated noise in the signal band.

[0004] To achieve the above objectives, a first aspect of the present invention provides an analog-to-digital converter (ADC), comprising: a first passive switched-capacitor integrator, comprising: 2Q first capacitors, a first switch group connected in series with Q of the 2Q first capacitors, and a second switch group connected in series with the remaining Q of the 2Q first capacitors; a second passive switched-capacitor integrator, comprising: 2Q second capacitors, a third switch group connected in series with Q of the 2Q second capacitors, and a fourth switch group connected in series with the remaining Q of the 2Q second capacitors; two capacitive analog-to-digital converter arrays; and a control logic circuit for closing the first switch group and the second switch group when the capacitors in the two capacitive analog-to-digital converter arrays are reset to their initial state, so that the first passive switched-capacitor integrator outputs a first... A residual voltage, and closing the third switch group and the fourth switch group to make the second passive switched capacitor integrator output a second residual voltage, wherein the first residual voltage is the sum of the first sub-residual voltages of the 2Q first capacitors in the previous preset period, and the second residual voltage is the sum of the second sub-residual voltages of the 2Q second capacitors in the previous preset period; and a dual differential input comparator, used to receive the sum of the first residual voltage and the input voltage of the current preset period as a first differential input signal, receive the second residual voltage as a second differential input signal, and output a comparison result; the control logic circuit is further used to output multiple switch control signals to the two capacitive analog-to-digital converter arrays according to the comparison result, so as to output digital data of the current preset period corresponding to the input voltage of the current preset period.

[0005] Preferably, the first passive switched capacitor integrator further includes a fifth switch group connected in parallel with the 2Q first capacitors. Accordingly, after outputting digital data of the previous preset period corresponding to the input voltage of the previous preset period, the control logic circuit is further configured to distribute the residual voltage of the upper plates of the two capacitive analog-to-digital converter arrays to the 2Q first capacitors by closing the fifth switch group, so that the voltage of the first capacitor is the first sub-residual voltage.

[0006] Preferably, the second passive switched capacitor integrator further includes a sixth switch group connected in parallel to the 2Q second capacitors. Accordingly, after performing the step of distributing the residual voltage of the upper plates of the two capacitive analog-to-digital converter arrays to the 2Q first capacitors by closing the fifth switch group, the control logic circuit is further configured to disconnect the fifth switch group and distribute the updated residual voltage of the upper plates of the two capacitive analog-to-digital converter arrays to the 2Q second capacitors by closing the sixth switch group, so that the voltage of the second capacitor is the second sub-residual voltage.

[0007] Preferably, the digital data is N-bit data, and the analog-to-digital converter further includes: a sampling switch circuit. Before the capacitors in the two capacitive analog-to-digital converter arrays are reset to their initial states, the control logic circuit is further configured to perform the following operations: according to a predicted value for the current preset period, connect the lower plates of the highest-order capacitors on the positive and negative sides of the two capacitive analog-to-digital converter arrays to different reference voltages; turn on the sampling switch circuit to sample the input voltage of the current preset period to the capacitive analog-to-digital converter arrays; and turn off the sampling switch circuit and reset each capacitor in the capacitive analog-to-digital converter arrays to their initial states to feed in a pre-offset compensation amount corresponding to the reference voltage and the lower N-1 bits of data from the N-bit data output in the previous preset period.

[0008] Preferably, after executing the step of outputting digital data for the current preset period corresponding to the input voltage of the current preset period, the control logic circuit is further configured to perform the following operations: subtracting the lower N-1 bits of the N-bit data output in the previous preset period from the N-bit data output in the current preset period to obtain an N-bit difference; and subtracting the value corresponding to the pre-offset compensation amount from the N-bit difference to output the compensated N-bit data for the current preset period corresponding to the input voltage of the current preset period.

[0009] Preferably, the control logic circuit is further configured to add the compensated N-bit data of the current preset period to the lower N-1 bits of the N-bit data output in the current preset period to obtain a predicted value for the next preset period.

[0010] Preferably, the control logic circuit for connecting the lower plates of the highest-order capacitors on the positive and negative sides of the two capacitive analog-to-digital converter arrays to different reference voltages includes: when the predicted value for the current preset period is 1, connecting the lower plates of the highest-order capacitors on the positive and negative sides of the capacitive analog-to-digital converter array located at the positive input terminal to a positive reference voltage, and connecting the lower plates of the highest-order capacitors on the positive and negative sides of the capacitive analog-to-digital converter array located at the negative input terminal to a negative reference voltage; or when the predicted value for the current preset period is 0, connecting the lower plates of the highest-order capacitors on the positive and negative sides of the capacitive analog-to-digital converter array located at the positive input terminal to a negative reference voltage, and connecting the lower plates of the highest-order capacitors on the positive and negative sides of the capacitive analog-to-digital converter array located at the negative input terminal to a positive reference voltage.

[0011] Preferably, the control logic circuit for resetting each capacitor in the capacitive analog-to-digital converter array to its initial state includes: connecting the lower plate of the capacitor on the positive side of the capacitive analog-to-digital converter array to a positive reference voltage, and grounding the lower plate of the capacitor on the negative side of the capacitive analog-to-digital converter array.

[0012] Preferably, the first passive switched capacitor integrator includes four first capacitors; and the second passive switched capacitor integrator includes four second capacitors, wherein the capacitance values ​​of the first capacitors and the second capacitors are equal to half the total capacitance value of the capacitive analog-to-digital converter array.

[0013] Through the above technical solution, the present invention creatively achieves the following: when the capacitors in the two capacitive analog-to-digital converter arrays are reset to their initial state, the first switch group and the second switch group are closed by the control logic circuit to cause the first passive switched capacitor integrator to output a first residual voltage; and the third switch group and the fourth switch group are closed by the control logic circuit to cause the second passive switched capacitor integrator to output a second residual voltage. A dual differential input comparator receives the sum of the first residual voltage and the input voltage of the current preset period as a first differential input signal, receives the second residual voltage as a second differential input signal, and outputs a comparison result. Then, based on the comparison result, the control logic circuit outputs multiple switch control signals to the two capacitive analog-to-digital converter arrays to output digital data of the current preset period corresponding to the input voltage of the current preset period. Therefore, this invention employs a second-order passive hybrid noise shaping technique. Two sets of passive switched-capacitor integrators sample and integrate the residual voltage of the previous preset cycle, respectively. The outputs of the two integrators are fed into the input sampling signal of the current cycle through error feedback and forward addition, respectively, and then converted. This modulates the in-band quantization noise and comparator noise of the analog-to-digital converter to the high-frequency band, achieving a second-order high-pass noise shaping effect and suppressing correlated noise in the signal band.

[0014] A second aspect of the present invention provides a chip, the chip comprising the aforementioned analog-to-digital converter.

[0015] For specific details and benefits of the chip provided in the embodiments of the present invention, please refer to the above description of the analog-to-digital converter, which will not be repeated here.

[0016] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0018] Figure 1 This is a structural diagram of a successive approximation analog-to-digital converter provided in an embodiment of the present invention;

[0019] Figure 2 This is a structural diagram of a first passive switched capacitor integrator provided in an embodiment of the present invention;

[0020] Figure 3 This is a structural diagram of a second passive switched capacitor integrator provided in an embodiment of the present invention;

[0021] Figure 4 These are two configuration diagrams of a first passive switched capacitor integrator and a second passive switched capacitor integrator provided in an embodiment of the present invention at different times.

[0022] Figure 5 This is a timing diagram of a successive approximation analog-to-digital converter provided in an embodiment of the present invention; and

[0023] Figure 6 This is a flowchart illustrating the working mechanism of an analog-to-digital converter provided in an embodiment of the present invention. Detailed Implementation

[0024] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0025] Figure 1 This is a structural diagram of an analog-to-digital converter (ADC) according to an embodiment of the present invention. The ADC may include: a first passive switched-capacitor integrator 10; a second passive switched-capacitor integrator 20; two capacitive analog-to-digital converter arrays (i.e., CDACs) 30; control logic circuitry 40; and a dual differential input comparator 50, such as... Figure 1 As shown.

[0026] The first passive switched capacitor integrator 10 may include: 2Q first capacitors, a first switch group connected in series with Q of the 2Q first capacitors, and a second switch group connected in series with the remaining Q of the 2Q first capacitors.

[0027] Where Q is a positive integer. For example, the first passive switched-capacitor integrator may include four first capacitors (i.e., C... A1 -C A4 First switch group S A9 S A10; and the second switch group S A11 S A12 ,like Figure 2 As shown. The capacitance value of the first capacitor (e.g., 1 / 2C) is... DAC The capacitance is equal to the total capacitance of the capacitive analog-to-digital converter array 30 (e.g., C). DAC 1 / 2 times.

[0028] The second passive switched capacitor integrator 20 may include: 2Q second capacitors, a third switch group connected in series with Q of the 2Q second capacitors, and a fourth switch group connected in series with the remaining Q of the 2Q second capacitors.

[0029] For example, the second passive switched capacitor integrator may include four second capacitors (i.e., C). B1 –C B4 Third switch group S B9 S B10 ; and the fourth switch group S B11 S B12 ,like Figure 3 As shown. The capacitance value of the second capacitor (e.g., 1 / 2C) is... DAC The capacitance is equal to the total capacitance of the capacitive analog-to-digital converter array 30 (e.g., C). DAC 1 / 2 times.

[0030] The control logic circuit 40 is used to close the first switch group and the second switch group when the capacitor in the capacitive analog-to-digital converter array 30 is reset to the initial state, so that the first passive switched capacitor integrator outputs a first residual voltage, and to close the third switch group and the fourth switch group so that the second passive switched capacitor integrator outputs a second residual voltage.

[0031] Specifically, the first residual voltage is the sum of the first sub-residual voltages of the 2Q first capacitors in the previous preset period, and the second residual voltage is the sum of the second sub-residual voltages of the 2Q second capacitors in the previous preset period.

[0032] For example, when the start signal (ΦRST signal) returns to high (i.e., the capacitors in the capacitive analog-to-digital converter array 30 are reset to their initial state) and the conversion control signal (ΦCNV signal) is pulled high (as... Figure 5 (As shown) After that, the first and second switch groups (i.e., switch S) in the passive switched capacitor integrator 10 are connected. A9 -S A12 ) and the third and fourth switch groups (i.e., switch S) in the passive switched capacitor integrator 20 B9 -S B12When closed, the configurations of passive switched capacitor integrator 10 and passive switched capacitor integrator 20 are as follows: Figure 4 The content on the right is shown. The sub-residual voltage V of the previous preset cycle after passive integration in the passive switched capacitor integrator 10 is... EF After performing a 2x passive multiplication (i.e., the first residual voltage is 2V), EF The input voltage is connected in series and applied to the first differential input terminal of the dual differential input comparator 50; simultaneously, the sub-residual voltage V of the previous preset cycle, which has been passively integrated in the passive switched capacitor integrator 20, is... CIFF After performing a 2x passive multiplication (i.e., the second residual voltage is 2V), CIFF Add to the second differential input, such as Figure 1 As shown.

[0033] The dual differential input comparator 50 is used to receive the sum of the first residual voltage and the input voltage of the current preset period as a first differential input signal, receive the second residual voltage as a second differential input signal, and output a comparison result.

[0034] For example, the amplification factor of the first differential input terminal of the dual differential input comparator is 1; and the amplification factor of the second differential input terminal of the dual differential input comparator is 5.

[0035] Specifically, during the time when signal ΦCNV is high, when comparator control signal ΦCLKC is high, the dual differential input comparator 50 will convert the 2V output from the passive switched capacitor integrator 10 into a high signal. EF The sum of the input voltage and the input voltage is used as the first differential input signal; simultaneously, the 2V output from the passive switched capacitor integrator 10 is used as the first differential input signal. CIFF As the second differential input signal, the corresponding comparison result is output according to the signal represented by the above formula: when the sum of the signals received by the two positive differential terminals of the comparator is greater than the sum of the signals received by the two negative differential terminals of the comparator, the comparison result is positive, otherwise it is negative.

[0036] When the dual differential input comparator outputs a comparison result, the control logic circuit 40 is further configured to output multiple switching control signals to the two capacitive analog-to-digital converter arrays based on the comparison result, so as to output digital data of the current preset period corresponding to the input voltage of the current preset period.

[0037] Specifically, the control logic circuit 40 can switch the capacitors at corresponding positions in the two capacitive analog-to-digital converter arrays 30 according to the comparison result output by the dual differential input comparator 50 and the switching scheme of the split switched capacitor array.

[0038] For example, when the comparison result is positive, the comparison (conversion) result of the k-th bit is 1. The successive approximation control circuit 41 in the control logic circuit 40 controls the corresponding switch to change the lower plate of the P-side capacitor corresponding to the k-th bit in the capacitive analog-to-digital converter array 30 located at the positive input terminal from the positive reference voltage V. REFP Change to negative reference voltage V REFN This causes the voltage V on the upper plate of the capacitor in the capacitive analog-to-digital converter array 30 at the positive input terminal to be... DACP Reduce (1 / 4) k (V REFP -V REFN The successive approximation control circuit 41 controls the corresponding switch to change the lower plate of the N-side capacitor in the capacitive analog-to-digital converter array 30 located at the negative input terminal from the negative reference voltage V. REFN Change to positive reference voltage V REFP This causes the voltage V on the upper plate of the capacitor in the capacitive analog-to-digital converter array 30 at the negative input terminal to be... DACN Increase (1 / 4) k (V REFP -V REFN Conversely, when the comparison result is negative, the comparison (conversion) result of the k-th bit is 0, and the lower plate of the N-side capacitor corresponding to the k-th bit in the capacitive analog-to-digital converter array 30 located at the positive input terminal is switched from the negative reference voltage V. REFN Change to positive reference voltage V REFP This causes the voltage V on the upper plate of the capacitor in the capacitive analog-to-digital converter array 30 at the positive input terminal to be... DACP Increase (1 / 4) k (V REFP -V REFN Meanwhile, the lower plate of the P-side capacitor in the capacitive analog-to-digital converter array 30 located at the negative input terminal is subjected to a positive reference voltage V. REFP Change to negative reference voltage V REFN This causes the voltage V on the upper plate of the capacitor in the capacitive analog-to-digital converter array 30 at the negative input terminal to be... DACN Reduce (1 / 4) k (V REFP -V REFN This is used to achieve binary successive approximation with the common-mode level remaining unchanged.

[0039] The entire successive approximation process is shown in the following equation, where N is the number of bits in the analog-to-digital converter, and D... k V represents the conversion result of the k-th bit. IP With V IN V represents the voltage values ​​sampled at the positive input terminal and the negative input terminal of the capacitive analog-to-digital converter array (CDAC) 30, respectively, during the sampling phase. REFPV REFN These represent the positive reference voltage / level and the negative reference voltage / level, respectively, V DACP V DACN These represent the voltage values ​​of the capacitive analog-to-digital converter array (CDAC) 30 located at the positive input terminal and the voltage values ​​of the capacitive analog-to-digital converter array 30 located at the negative input terminal, respectively.

[0040]

[0041]

[0042]

[0043] When the comparison reaches the last bit, if the comparison result is positive, the lower plate of the lowest positive (P) side capacitor in the capacitive analog-to-digital converter array (CDAC) 30 located at the positive input terminal is changed from the positive reference voltage to the negative reference voltage, so as to generate the correct residual voltage (V) on the upper plate of the capacitor in the differential capacitive analog-to-digital converter array (CDAC) 30. RES If the input is positive, the lower plate of the capacitor on the positive (P) side of the least significant bit of the capacitive analog-to-digital converter array (CDAC) 30 located at the negative input terminal is changed from the positive reference voltage to the negative reference voltage, and the successive approximation conversion is completed.

[0044] The first sub-residual voltage of the first capacitor in the previous preset period and the second sub-residual voltage of the second capacitor in the previous preset period in the above embodiments will be described below.

[0045] The first passive switched capacitor integrator 10 may further include a fifth switch group connected in parallel with the 2Q first capacitors. Accordingly, after outputting digital data of the previous preset period corresponding to the input voltage of the previous preset period, the control logic circuit is further configured to distribute the residual voltage of the upper plates of the two capacitive analog-to-digital converter arrays to the 2Q first capacitors by closing the fifth switch group, so that the voltage of the first capacitor is the first sub-residual voltage.

[0046] For example, the first passive switched capacitor integrator 10 may further include: a fifth switch group (e.g., connecting four first capacitors in parallel) Figure 2 The switch S shown A1 -S A8 ).

[0047] The second passive switched capacitor integrator 20 may further include a sixth switch group connected in parallel to the 2Q second capacitors. Accordingly, after performing the step of distributing the residual voltage of the upper plates of the two capacitive analog-to-digital converter arrays to the 2Q first capacitors by closing the fifth switch group, the control logic circuit is further configured to disconnect the fifth switch group and distribute the updated residual voltage of the upper plates of the two capacitive analog-to-digital converter arrays to the 2Q second capacitors by closing the sixth switch group, so that the voltage of the second capacitor is the second sub-residual voltage.

[0048] For example, the second passive switched capacitor integrator 20 may further include: a sixth switch group (e.g., connecting four second capacitors in parallel) Figure 2 The switch S shown B1 -S B8 ).

[0049] Specifically, after obtaining the corresponding digital data in the previous preset cycle, in the analog domain, the control signal ΦEF of the control logic circuit 40 is pulled high to turn on the fifth switch group (i.e., switch S) in the passive switched capacitor integrator 10. A1 -S A8 At this time, the configuration of the passive switched capacitor integrator 10 is as follows: Figure 4 (As shown in the left-hand side content), thus the residual voltages on the upper plates of all capacitors in the capacitive analog-to-digital converter array 30 can be sampled differentially to the integrating capacitor C through charge redistribution between capacitors. A1 -C A4 The above is used to achieve a first-order source-free integral. This process satisfies the following equation, where V EF The first sub-residual voltage of the first capacitor in the previous preset cycle:

[0050]

[0051] When ΦEF returns to low (disconnect switch S) A1 -S A8 After that, the control signal ΦCIFF of the control logic circuit 40 is pulled high to turn on the sixth switch group (i.e., switch S) in the passive switched capacitor integrator 20. B1 -S B8 At this time, the configuration of the passive switched capacitor integrator 20 is as follows: Figure 4 (As shown in the left-hand side) The updated residual voltage on the upper plate of all capacitors in the capacitive analog-to-digital converter array 30 (i.e., the residual voltage of the capacitive analog-to-digital converter array 30 after sampling by the passive switched capacitor integrator 10, the value of which is equal to the capacitance C) A1 -C A4 The voltage V across each capacitor in the middle EF The sample is collected by differential sampling using charge redistribution to the integrating capacitor C.B1 -C B4 Above, a second-order source-free integral is achieved. This process satisfies the following equation, where V CIFF The second residual voltage of the second capacitor in the previous preset cycle:

[0052]

[0053] The 2V output from the passive switched capacitor integrator 10 EF The sum of the input voltage and the input voltage is used as the first differential input signal of the dual differential input comparator 50; simultaneously, the 2V output from the passive switched capacitor integrator 10 is used as the first differential input signal. CIFF As the second differential input signal, the successive approximation control circuit 41 outputs a signal represented by the following equation (the system signal transfer function in the discrete domain):

[0054] D OUT (z)=V INPUT (z)+4V EF (z)+5×4V CIFF (z)=V INPUT (z)+(1-0.8z -1 ) 2 Q(z),

[0055] Where z is a variable in the discrete domain, V CIFF The corresponding 5x additional gain is achieved by making the size of the transistor at the second differential input of the comparator a multiple of the size of the transistor at the first differential input.

[0056] The aforementioned second-order passive hybrid noise shaping technique uses two sets of passive switched-capacitor integrators to sample and integrate the converted residual voltage. Then, the outputs of the two integrators are fed into the input sampling signal of the next cycle via error feedback and forward addition, respectively, for conversion. This modulates the in-band quantization noise and comparator noise of the analog-to-digital converter to the high-frequency band, achieving a second-order high-pass noise shaping effect. This scheme can more effectively reduce quantization noise and comparator noise within the signal bandwidth, and can further improve the in-band signal-to-noise ratio of the analog-to-digital converter while maintaining a small chip area.

[0057] The capacitive analog-to-digital converter array (CDAC) 30 includes N pairs of capacitors and corresponding N pairs of switches. Each pair of capacitors corresponds to one data bit. Specifically, the N pairs of capacitors include one pair of highest-order bit capacitors (including the highest-order bit capacitor on the positive side and the highest-order bit capacitor on the negative side) and N-1 pairs of other low-order bit capacitors (including N-2 intermediate low-order bit capacitors on the positive side, N-2 intermediate low-order bit capacitors on the negative side, and one lowest-order bit capacitor and one filler capacitor on the positive side), which correspond to the highest-order bit data and the lower N-1 bits of data, respectively.

[0058] Although oversampling and noise shaping techniques can effectively improve the in-band signal-to-noise ratio of analog-to-digital converters (ADCs), they cannot reduce the impact of harmonic distortion introduced by capacitor array mismatch on ADCs, which often has a greater impact on the signal-to-noise ratio of high-resolution ADCs.

[0059] To address the aforementioned technical issues, this embodiment employs a prediction-based input signal pre-offset technique. This technique addresses the mechanism of error feedback-based mismatch error shaping, which requires feeding the low-order conversion result of the previous preset cycle into the current conversion. Utilizing oversampling characteristics, it predicts the range of the "to-be-converted voltage value" after the low-order result is fed into the next cycle based on the conversion result of the previous preset cycle. Based on this prediction, it uses the high-order capacitors of the capacitor array for pre-switching to achieve input pre-offset, ensuring that the to-be-converted voltage does not exceed the full swing of the input signal range, thus guaranteeing that the dynamic range of the input remains unaffected. It is worth noting that because this solution uses a two-point prediction technique, it effectively avoids introducing new harmonics.

[0060] In one embodiment, the digital data may be N-bit data, and the analog-to-digital converter may further include: a sampling switch circuit 60, such as... Figure 1 As shown.

[0061] Before the capacitors in the two capacitive analog-to-digital converter arrays are reset to their initial states, the control logic circuit 40 is further configured to perform the following operations: connect the lower plates of the highest-order capacitors on the positive and negative sides of the two capacitive analog-to-digital converter arrays to different reference voltages based on a predicted value for the current preset period; turn on the sampling switch circuit to sample the input voltage of the current preset period to the capacitive analog-to-digital converter arrays; and turn off the sampling switch circuit and reset each capacitor in the capacitive analog-to-digital converter arrays to its initial state to feed in a pre-offset compensation amount corresponding to the reference voltage and the lower N-1 bits of data from the N-bit data output in the previous preset period.

[0062] The control logic circuit 40 for connecting the lower plates of the highest-order capacitors on the positive and negative sides of the two capacitive analog-to-digital converter arrays to different reference voltages may include: when the predicted value for the current preset period is 1, connecting the lower plates of the highest-order capacitors on the positive and negative sides of the capacitive analog-to-digital converter array located at the positive input terminal to a positive reference voltage, and connecting the lower plates of the highest-order capacitors on the positive and negative sides of the capacitive analog-to-digital converter array located at the negative input terminal to a negative reference voltage; or when the predicted value for the current preset period is 0, connecting the lower plates of the highest-order capacitors on the positive and negative sides of the capacitive analog-to-digital converter array located at the positive input terminal to a negative reference voltage, and connecting the lower plates of the highest-order capacitors on the positive and negative sides of the capacitive analog-to-digital converter array located at the negative input terminal to a positive reference voltage.

[0063] The control logic circuit 40 for resetting each capacitor in the capacitive analog-to-digital converter array to its initial state may include: connecting the lower plate of the capacitor on the positive side of the capacitive analog-to-digital converter array to a positive reference voltage, and grounding the lower plate of the capacitor on the negative side of the capacitive analog-to-digital converter array.

[0064] Specifically, after obtaining the predicted value for the current preset period, the lower plates of the two highest-order capacitors of the capacitive analog-to-digital converter arrays 30 are controlled to be reconnected to a positive reference voltage (predicted result is positive) or a negative reference voltage (result is negative) input pre-offset according to the corresponding prediction result, in preparation for the input pre-offset: when the result is positive, the lower plates of the highest-order capacitors on the positive (P) side are reconnected to the positive reference voltage, and the lower plates of the highest-order capacitors on the negative (N) side are reconnected to the negative reference voltage; and when the prediction result is negative, the opposite is true.

[0065] At the start of a preset cycle, the control logic circuit 40 pulls the sampling control signal ΦCLKS high and holds it for 4 clock cycles to turn on the sampling switch, thereby differentially sampling the input signal onto the capacitive analog-to-digital converter array 30 at both positive and negative ends; the switches connected to the lower plates of the remaining low-order capacitors remain unchanged from the previous preset cycle, keeping the low-order conversion result of the previous preset cycle in the corresponding bit, so as to achieve mismatch error shaping (between the low-order capacitor and the highest-order capacitor).

[0066] After the control signal ΦCLKS goes low (i.e., the sampling switch circuit 60 is disconnected), after a short delay, the start signal ΦRST is pulled low for one clock cycle to reset all capacitors in the capacitive analog-to-digital converter array 30 to their initial state: the lower plates of all capacitors on the P side are reconnected to the positive reference voltage, while the lower plates of all capacitors on the N side are reconnected to ground. During the reset, the low-order conversion result of the previous preset cycle required for mismatch error shaping is simultaneously fed in, and the input pre-offset compensation amount ±1 / 2 (V) required to eliminate the influence of mismatch error shaping is also completed. REFP -V REFN (When the predicted value for the current preset period is 1, the lower plate of the highest-order capacitor on both the positive and negative sides of the capacitive analog-to-digital converter array located at the positive input terminal is connected to a positive reference voltage, and the lower plate of the highest-order capacitor on both the positive and negative sides of the capacitive analog-to-digital converter array located at the negative input terminal is connected to a negative reference voltage. In this case, the compensation amount introduced during the reset phase is negative, i.e., -1 / 2 (V REFP -V REFN Conversely, the compensation introduced during the reset phase is a positive value, i.e., +1 / 2(V). REFP -V REFN The introduction of this scheme involves two operations. The pre-offset operation cancels out the input signal overload caused by feeding in the previous low-bit conversion result, ensuring that the signal to be converted after feeding remains within the normal input range of the analog-to-digital converter, thus avoiding the input dynamic range loss caused by mismatch error shaping. Since this scheme only requires adding an array adder and does not require additional dynamic element matching circuitry, it also eliminates the impact of the original mismatch error shaping scheme on the input dynamic range, making it simple to implement and possessing good robustness.

[0067] Because the lower N-1 bits of data from the previous preset cycle output are introduced into the DAC before conversion (i.e., in the analog domain). LSB (n-1) and pre-offset compensation amount DAC PRE (n), such as Figure 6 As shown, the N-bit data of the current preset period after conversion can be corrected accordingly.

[0068] After executing the step of outputting digital data for the current preset period corresponding to the input voltage of the current preset period, the control logic circuit 40 is further configured to perform the following operations: subtracting the lower N-1 bits of the N-bit data output in the previous preset period from the N-bit data output in the current preset period to obtain an N-bit difference; and subtracting the value corresponding to the pre-offset compensation amount from the N-bit difference to output the compensated N-bit data for the current preset period corresponding to the input voltage of the current preset period.

[0069] Specifically, because the low-order bit signal of the previous preset period is added to the input signal in the analog domain, after the conversion, in the digital domain, the 10-bit data D<1:10> (the low 9 bits of the current preset period n) output by the analog-to-digital converter is... LSB (n) and the highest bit data D of the current preset period n MSB The sum of (n) is fed into the subtractor, and D<1:10> is used to subtract the lower 9 bits of the conversion result of the previous preset cycle n-1 stored in the corresponding register (i.e., D). LSB (n-1)), such as Figure 6 As shown, a corresponding high-pass shaping transfer function (1-z) is constructed for the mismatch E(n) of the low-order capacitor relative to the highest-order capacitor. -1 This enables first-order high-pass mismatch error shaping.

[0070] The reason is as follows: Due to the mismatch between the actual low-order capacitor and the highest-order capacitor, the low-order conversion result of the mode converter (DAC) will carry a corresponding mismatch error E(n) (where DAC... LSB (n) represents the low-order conversion result remaining on the lower plate of the corresponding capacitor in the CDAC, D LSB (n) represents the lower 9 bits of the output numeric code excluding the most significant bit.

[0071] DAC LSB (n)=D LSB (n)+E(n);

[0072] Mismatch shaping (MES) technology relies on returning the least significant bit (LSB) of the previous cycle's conversion result, carrying the mismatch error E(n), to the current cycle, constructing a high-pass shaping function for E(n). In the analog domain, it is only necessary to retain the least significant bit (LSB) of the previous conversion result on the lower plate of the corresponding capacitor during sampling, and then reset it after sampling is completed to achieve the desired input signal and DAC signal. LSB Addition of (n):

[0073] V INPUT (n)+DAC LSB (n-1)-DAC MSB (n)-DAC LSB (n) = 0;

[0074] Because the low-order bits of the previous cycle are added to the input signal in the analog domain, after the conversion, in the digital domain, the 10-bit output D<1:10> of the analog-to-digital converter enters the subtractor to subtract the low-order 9 bits of the previous cycle's conversion result stored in the corresponding register, thus subtracting the low-order bit result from the previous cycle. The corresponding high-pass shaping transfer function (1-z) is constructed based on the mismatch E(n) between the low-order capacitor and the highest-order bit. -1 To achieve first-order high-pass mismatch error shaping:

[0075] D OUT (n)=D MSB (n)+D LSB (n)-D LSB (n-1).

[0076] Substituting the first two formulas into the third formula, we get:

[0077] D OUT (n)=V INPUT (n)+E(n-1)-E(n),

[0078] That is:

[0079] D OUT (z)=V INPUT (z)+(1-z -1 E(z),

[0080] It is equivalent to performing a first-order high-pass shaping on the mismatch error in the output.

[0081] Then, the result of the above subtraction is fed into an adder / subtractor to subtract the value corresponding to the pre-offset compensation amount (i.e., Figure 6 D shown PRE (n)), the output result is used as the compensated output digital quantity S<1:10> with the current preset period. Specifically, based on the predicted value of the current preset period, when the predicted value of the current preset period is 1, the compensation amount introduced in the reset phase is negative (i.e., -1 / 2(V)). REFP -V REFN Then add 1 / 2 (V) to the result of the above subtraction. REFP -V REFN Conversely, when the predicted value for the preset period is 0, the compensation introduced during the reset phase is positive (i.e., +1 / 2(V)). REFP -V REFN Then subtract 1 / 2 (V) from the result of the above subtraction. REFP -V REFN ).

[0082] After obtaining the compensated N-bit data for the current preset period, the control logic circuit 40 is further configured to add the compensated N-bit data for the current preset period to the lower N-1 bits of the N-bit data output for the current preset period to obtain a predicted value for the next preset period.

[0083] Specifically, the output processing and prediction circuit 42 in the control logic circuit 40 compares the compensated N-bit data S<1:10> of the current preset period with the lower N-1 bits D of the N-bit data output in the current preset period. LSB (n) are added together to obtain a prediction value for the next preset period.

[0084] Based on the sign of the predicted value for the next preset period, the output processing and prediction circuit 42 sets the corresponding control bit to 0 (predicted value is positive) or 1 (predicted value is negative). Then, at the last rising edge of the current preset period and when the ΦSET signal is high, the value of the control bit is sent to the control switch of the highest bit capacitor. The input signal pre-offset based on the input signal range prediction is achieved by reconnecting the lower plate of the highest bit capacitor.

[0085] Since the analog-to-digital conversion process requires the corresponding results of the previous preset period, the above embodiments define a corresponding preset period. However, it should be noted that each step in the analog-to-digital conversion process in the above embodiments is not limited to the corresponding preset period (e.g., the current preset period), and can be similarly applied to each preset period (e.g., the previous preset period or the next preset period).

[0086] The following describes the analog-to-digital conversion process in the current preset cycle, which mainly includes the following steps S1-S8.

[0087] S1: At the last rising edge of the previous preset cycle, the ΦSET signal is high. Based on the prediction result of the previous preset cycle for the current preset cycle, the lower plate of the highest-order capacitor on both the positive and negative sides of the capacitive analog-to-digital converter array 30 can be switched to a positive reference voltage (predicted result is positive) or a negative reference voltage (result is negative) to prepare for the input pre-offset.

[0088] S2: At the start of the current preset cycle, the sampling control signal ΦCLKS is pulled high and held for 4 clock cycles to turn on the sampling switch, thereby differentially sampling the input signal onto the two capacitive analog-to-digital converter arrays 30; the switches connected to the lower plates of the remaining low-order capacitors remain unchanged from the previous preset cycle to keep the low-order conversion results of the previous preset cycle in the corresponding bits, thereby achieving mismatch error shaping (between the low-order capacitor and the highest-order capacitor).

[0089] S3: After the control signal ΦCLKS goes low, after a short delay, the start signal ΦRST is pulled low for one clock cycle to reset all the capacitors in the two capacitive analog-to-digital converter arrays 30 to their initial state.

[0090] S4: After the ΦRST signal returns to high, the ΦCNV signal is pulled high to switch S in the passive switched capacitor integrator 10.A9 -S A12 With the passive switched capacitor integrator 20, the switch S B9 -S B12 Closing the circuit will cause the residual voltage V in the passive switched capacitor integrator 10, which has undergone passive integration in the previous preset cycle, to be closed. EF After performing a 2x passive multiplication (i.e., the first residual voltage is 2V), EF The input voltage is connected in series and applied to the first differential input terminal of the dual differential input comparator 50; simultaneously, the sub-residual voltage V of the previous preset cycle, which has been passively integrated in the passive switched capacitor integrator 20, is... CIFF After performing a 2x passive multiplication (i.e., the second residual voltage is 2V), CIFF Add it to the second differential input.

[0091] S5: During the time when the control signal ΦCNV is high, when the comparator control signal ΦCLKC is high, the dual differential input comparator 50 will convert the 2V output from the passive switched capacitor integrator 10 into a voltage level of 10. EF The sum of the input voltage and the input voltage is used as the first differential input signal; simultaneously, the 2V output from the passive switched capacitor integrator 10 is used as the first differential input signal. CIFF The signal is used as the second differential input signal, and the comparison result is output. Based on the comparator output, the capacitors at corresponding positions in the two capacitive analog-to-digital converter arrays 30 are switched according to the switching scheme of the split switched capacitor array.

[0092] S6: After the conversion is complete, in the analog domain, the control signal ΦEF is pulled high to turn on the switch S in the passive switched capacitor integrator 10. A1 -S A8 The residual voltage on the upper plate of the capacitive analog-to-digital converter array 30 is sampled differentially to the integrating capacitor C through charge redistribution between capacitors. A1 -C A4 The first-order passive integration is achieved by raising the control signal ΦCIFF high after ΦEF returns to low to turn on the switch S in the passive switched capacitor integrator 20. B1 -S B8 The residual voltage on the upper plate of the capacitive analog-to-digital converter array 30 is sampled differentially to the integrating capacitor C using charge redistribution. B1 -C B4 Above, a second-order passive integral is achieved.

[0093] S7: Because the low-order signal of the previous preset cycle is added to the input signal in the analog domain, after the conversion, the 10-bit data D<1:10> output by the analog-to-digital converter enters the subtractor in the digital domain, and D<1:10> is subtracted from the D stored in the corresponding register. LSB (n-1), such as Figure 6As shown, first-order high-pass mismatch error shaping is achieved. Then, the subtraction result is fed into an adder / subtractor, which subtracts the value D corresponding to the pre-offset compensation amount from the predicted value of the current preset period. PRE (n) will be the output result as the output digital quantity S<1:10> after compensation with the current preset period.

[0094] S8: The output processing and prediction circuit 42 combines the compensated N-bit data S<1:10> of the current preset period with the lower N-1 bits D of the N-bit data output in the current preset period. LSB (n) are added together to obtain a predicted value for the next preset period. Based on the sign of the predicted value for the next preset period, the output processing and prediction circuit 42 then sets the corresponding control bit to 0 (predicted value is positive) or 1 (predicted value is negative). Then, at the last rising edge of the current preset period and when the ΦSET signal is high, the value of the control bit is sent to the control switch of the highest bit capacitor. By changing the lower plate of the highest bit capacitor, the input signal pre-offset based on the input signal range prediction is achieved.

[0095] The above embodiments primarily employ two techniques: passive hybrid noise shaping and prediction-based input signal pre-offset technology, to further improve the in-band signal-to-noise ratio (SNR) of the analog-to-digital converter (ADC). This achieves high SNR and spurious-free dynamic range (SFDR) with low system complexity, small chip area, and low power consumption. This approach can be applied to low-power sensor systems, effectively reducing quantization noise within the signal bandwidth, improving the ADC's in-band SNR, and eliminating the impact of mismatch error shaping on the ADC's input dynamic range while maintaining good mismatch error shaping (elimination) performance. This effectively improves the ADC's resolution and linearity within the system.

[0096] In summary, this invention creatively achieves the following: when the capacitors in the two capacitive analog-to-digital converter arrays are reset to their initial state, the first and second switch groups are closed by a control logic circuit to cause the first passive switched-capacitor integrator to output a first residual voltage; the third and fourth switch groups are closed by a control logic circuit to cause the second passive switched-capacitor integrator to output a second residual voltage; a dual differential input comparator receives the sum of the first residual voltage and the input voltage of the current preset period as a first differential input signal, receives the second residual voltage as a second differential input signal, and outputs a comparison result; then, based on the comparison result, the control logic circuit outputs multiple switch control signals to the two capacitive analog-to-digital converter arrays to output digital data of the current preset period corresponding to the input voltage of the current preset period. Therefore, this invention employs a second-order passive hybrid noise shaping technique. Two sets of passive switched-capacitor integrators sample and integrate the residual voltage of the previous preset cycle, respectively. The outputs of the two integrators are fed into the input sampling signal of the current cycle through error feedback and forward addition, respectively, and then converted. This modulates the in-band quantization noise and comparator noise of the analog-to-digital converter to the high-frequency band, achieving a second-order high-pass noise shaping effect and suppressing correlated noise in the signal band.

[0097] An embodiment of the present invention also provides a chip, the chip including the aforementioned analog-to-digital converter.

[0098] For specific details and benefits of the chip provided in the embodiments of the present invention, please refer to the above description of the analog-to-digital converter, which will not be repeated here.

[0099] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0100] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0101] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a microcontroller, chip, or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0102] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. An analog-to-digital converter, characterized in that, The analog-to-digital converter includes: A first passive switched capacitor integrator includes: 2Q first capacitors, a first switch group connected in series with Q of the 2Q first capacitors, and a second switch group connected in series with the remaining Q of the 2Q first capacitors. The second passive switched capacitor integrator includes: 2Q second capacitors, a third switch group connected in series with Q of the 2Q second capacitors, and a fourth switch group connected in series with the remaining Q of the 2Q second capacitors. Two capacitive analog-to-digital converter arrays; A control logic circuit is configured to, when the capacitors in the two capacitive analog-to-digital converter arrays are reset to their initial states, close the first switch group and the second switch group to cause the first passive switched-capacitor integrator to output a first residual voltage, and close the third switch group and the fourth switch group to cause the second passive switched-capacitor integrator to output a second residual voltage, wherein the first residual voltage is the sum of the first sub-residual voltages of the 2Q first capacitors in the previous preset period, and the second residual voltage is the sum of the second sub-residual voltages of the 2Q second capacitors in the previous preset period; and A dual differential input comparator is used to receive the sum of the first residual voltage and the input voltage of the current preset period as a first differential input signal, receive the second residual voltage as a second differential input signal, and output the comparison result. The control logic circuit is further configured to output multiple switching control signals to the two capacitive analog-to-digital converter arrays based on the comparison result, so as to output digital data of the current preset period corresponding to the input voltage of the current preset period.

2. The analog-to-digital converter according to claim 1, characterized in that, The first passive switched capacitor integrator further includes: a fifth switch group connected in parallel to the 2Q first capacitors. Accordingly, after outputting the digital data of the previous preset period corresponding to the input voltage of the previous preset period, the control logic circuit is further configured to distribute the residual voltage of the upper plate of the two capacitive analog-to-digital converter arrays to the 2Q first capacitors by closing the fifth switch group, so that the voltage of the first capacitor is the first sub-residual voltage.

3. The analog-to-digital converter according to claim 2, characterized in that, The second passive switched capacitor integrator further includes: a sixth switch group connected in parallel to the 2Q second capacitors. Accordingly, after performing the step of distributing the residual voltage of the upper plates of the two capacitive analog-to-digital converter arrays to the 2Q first capacitors by closing the fifth switch group, the control logic circuit is further configured to open the fifth switch group and distribute the updated residual voltage of the upper plates of the two capacitive analog-to-digital converter arrays to the 2Q second capacitors by closing the sixth switch group, so that the voltage of the second capacitor is the second sub-residual voltage.

4. The analog-to-digital converter according to claim 1, characterized in that, The digital data is N-bit data, and the analog-to-digital converter further includes a sampling switch circuit. Before the capacitors in the two capacitive analog-to-digital converter arrays are reset to their initial state, the control logic circuit is also configured to perform the following operations: Based on the predicted value for the current preset period, the lower plates of the highest-order capacitors on the positive and negative sides of the two capacitive analog-to-digital converter arrays are connected to different reference voltages. Turn on the sampling switch circuit to sample the input voltage of the current preset period onto the capacitive analog-to-digital converter array; and Disconnect the sampling switch circuit and reset each capacitor in the capacitive analog-to-digital converter array to its initial state to feed in the pre-offset compensation amount corresponding to the reference voltage and the lower N-1 bits of the N-bit data output in the previous preset cycle.

5. The analog-to-digital converter according to claim 4, characterized in that, After executing the step of outputting digital data for the current preset period corresponding to the input voltage of the current preset period, the control logic circuit is further configured to perform the following operations: Subtract the lower N-1 bits of the N-bit data output in the previous preset period from the N-bit data output in the current preset period to obtain an N-bit difference. as well as Subtract the value corresponding to the pre-offset compensation from the N-bit difference to output the compensated N-bit data corresponding to the input voltage of the current preset period.

6. The analog-to-digital converter according to claim 5, characterized in that, The control logic circuit is further configured to add the compensated N-bit data of the current preset period to the lower N-1 bits of the N-bit data output in the current preset period to obtain a predicted value for the next preset period.

7. The analog-to-digital converter according to claim 4, characterized in that, The control logic circuit is used to connect the lower plates of the highest-order capacitors on the positive and negative sides of the two capacitive analog-to-digital converter arrays to different reference voltages, including: When the predicted value for the current preset period is 1, the lower plate of the highest-order capacitor on both the positive and negative sides of the capacitive analog-to-digital converter array located at the positive input terminal is connected to a positive reference voltage, and the lower plate of the highest-order capacitor on both the positive and negative sides of the capacitive analog-to-digital converter array located at the negative input terminal is connected to a negative reference voltage; or When the predicted value for the current preset period is 0, the lower plate of the highest-order capacitor on the positive and negative sides of the capacitive analog-to-digital converter array located at the positive input terminal is connected to the negative reference voltage, and the lower plate of the highest-order capacitor on the positive and negative sides of the capacitive analog-to-digital converter array located at the negative input terminal is connected to the positive reference voltage.

8. The analog-to-digital converter according to claim 4, characterized in that, The control logic circuit is used to reset each capacitor in the capacitive analog-to-digital converter array to its initial state, including: The lower plate of the capacitor on the positive side of the capacitive analog-to-digital converter array is connected to a positive reference voltage, and the lower plate of the capacitor on the negative side of the capacitive analog-to-digital converter array is grounded.

9. The analog-to-digital converter according to claim 1, characterized in that, The first passive switched-capacitor integrator includes four first capacitors; and the second passive switched-capacitor integrator includes four second capacitors. The capacitance values ​​of the first capacitor and the second capacitor are equal to half the total capacitance value of the capacitive analog-to-digital converter array.

10. A chip, characterized in that, The chip includes an analog-to-digital converter according to any one of claims 1-9.

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