A high-precision low-overhead two-stage differential TDC circuit based on a self-timing ring

Abstract

The application discloses a high-precision low-overhead two-stage differential TDC circuit based on a self-timing ring, and the overall structure is divided into a coarse measurement part and a fine measurement part; wherein the coarse measurement part is composed of a fast self-timing ring, a slow self-timing ring, a fast ring counter, a slow ring counter, a D flip-flop D1, an edge coincidence detection unit and a latch unit; the fine measurement part is composed of two delay chains which are the same in structure, position symmetric but different in delay unit delay. The application can reduce measurement error, thereby reducing hardware resource overhead, reducing power consumption, and improving measurement precision under the premise of ensuring high resolution.

Description

Technical Field

[0001] This invention relates to the fields of laser ranging, time-of-flight measurement, and integrated circuit small delay measurement. It describes a method for measuring small delays by designing a high-precision, low-overhead two-stage differential TDC circuit based on a self-timing loop in an FPGA. The purpose of this method is for on-chip delay measurement. Background Technology

[0002] Throughout history, humankind has always been measuring time, and with the advancement of technology, the precision of time measurement has continuously improved. In everyday timekeeping, a precision of seconds is sufficient, but for time measurement devices in fields such as physics experiments, smart homes, and integrated circuits, a precision of picoseconds is often required.

[0003] A time-to-digital converter (TDC) is a circuit that measures the time difference between two input events or pulse widths. In today's industry and academia, TDCs are the primary means of measuring time intervals, especially for measuring minute time intervals.

[0004] Currently, TDC implementations are mainly based on full-custom ASIC-TDC design and FPGA-TDC design. Compared with ASIC-based TDCs, FPGA-based TDCs offer advantages such as shorter design cycles, lower development costs, higher flexibility, and adaptability to different measurement fields.

[0005] With the development of integrated circuit technology and the increase in integration density, circuit delay has been significantly reduced. Furthermore, in recent years, Moore's Law has gradually become less effective, and lightweight, miniaturized, and low-power edge devices have developed rapidly in the context of the Internet of Things (IoT). Therefore, the research focus of time-to-digital converters has gradually shifted from circuit designs that combine high resolution and high precision to high-precision, low-overhead circuit designs.

[0006] Resolution, accuracy, integral-major linearity, differential-major nonlinearity, and resource overhead are important indicators for evaluating the performance of time-to-digital converters (TD-SCDMA). Traditional TD-SCDMA designs emphasize high resolution and high accuracy, inevitably requiring more resources. Traditional time interval measurement techniques are implemented using direct counting methods based on the system reference clock. Because time measurement techniques are highly dependent on the reference clock of the system, their measurement resolution is limited by the system clock. As resolution increases, the system clock frequency needs to be increased. If the time measurement resolution is increased to 100 ps, ​​the corresponding clock frequency needs to reach the 10 GHz standard, which poses a significant challenge to hardware design. Furthermore, in high-resolution engineering applications, the measurement value obtained by the direct counting method has an error of 1 to 2 clock cycles compared to the actual value, and the nonlinearity of the system itself becomes increasingly apparent.

[0007] Therefore, in order to improve the resolution of the time-to-digital converter, a system clock is used in the coarse measurement stage to expand the measurement range, and time interpolation technology is used in the fine measurement stage to improve the resolution, which can improve the measurement resolution to the tens of picosecond level.

[0008] In past designs of time-to-digital converter (TDC) circuits, various TDC design schemes based on FPGA platforms have been proposed. Some researchers use direct counting methods in the coarse measurement stage and tapped delay chain structures or vernier delay chain structures in the fine measurement stage. Other researchers design TDCs based on ring oscillators or vernier ring oscillators. The resolution of the design combining direct counting methods with tapped delay chains is limited by the minimum delay time of a single logic gate and the uneven distribution of the logic gate delay times. In the design combining direct counting methods with vernier delay chains, the vernier delay chain is much longer than the tapped delay chain for the same measurement range, requiring a large amount of on-chip FPGA resources and consuming more power. Compared with the direct counting method and delay chain structure, the TDC design based on ring oscillators has a larger measurement range, but requires a high-precision and stable oscillator. The resolution of the TDC based on vernier ring oscillators is the period difference between the fast and slow ring oscillators, which is higher than the resolution of the design based on ring oscillators. However, the timing of the fast ring catching up with the edge of the slow ring is not actually when the edges coincide, introducing measurement errors. Past FPGA-based TDC designs did not handle this error. Summary of the Invention

[0009] The present invention addresses the shortcomings of the prior art by proposing a high-precision, low-overhead two-stage differential TDC circuit based on a self-timing loop. This circuit aims to ensure measurement range while achieving higher resolution and accuracy, better circuit robustness, better portability, and lower power consumption.

[0010] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0011] The present invention discloses a high-precision, low-overhead two-stage differential TDC circuit based on a self-timing loop, characterized in that it includes a coarse measurement section and a fine measurement section; wherein, the coarse measurement section consists of a fast self-timing loop, a slow self-timing loop, a fast loop counter, a slow loop counter, a D flip-flop D1, an edge coincidence detection unit, and a latching unit, wherein the fast self-timing loop and the slow self-timing loop are two fourth-order self-timing loops STR with identical structures but different frequencies;

[0012] The fine measurement section consists of two delay chains with identical structures and symmetrical positions, but with different delay units.

[0013] The output of the slow self-timed loop serves as the D terminal of the D flip-flop D1 and the input terminal of the slow loop counter.

[0014] The output of the fast self-timing loop serves as the clock terminal of the D flip-flop D1 and the input terminal of the fast loop counter.

[0015] The clock terminal of the D flip-flop D1 is the output terminal of the fast self-timer loop, and the D terminal of the D flip-flop D1 is the output terminal of the slow self-timer loop.

[0016] The inputs of the two symmetrical delay chains in the fine measurement section are respectively connected to the outputs of the fast self-timing loop and the slow self-timing loop.

[0017] The time interval between the Start signal and the Stop signal is set, and the Start signal and Stop signal are generated by an external clock module; a vernier structure composed of two fourth-order self-timing loops STR divides the time interval between the Start signal and the Stop signal into two time segments, and the two time segments are tested in parallel.

[0018] The Start signal is input into the slow self-timer to cause the slow self-timer loop to oscillate, and the slow loop counter receives the output of the slow self-timer loop.

[0019] The Stop signal is input into the fast self-timing loop to cause it to oscillate; the fast loop counter receives the output of the fast self-timing loop.

[0020] The slow-loop counter counts the number of oscillations of the slow self-timer loop before the edges coincide, and obtains the count value n1.

[0021] The fast-loop counter counts the number of oscillations of the fast self-timer loop before the edges coincide, and obtains the count value n2;

[0022] The fast self-timing loop samples the slow self-timing loop. When the sampling result changes from high level to low level, it indicates that the fast self-timing loop has caught up with the slow self-timing loop. The D flip-flop D1 then sends the sampling result to the edge coincidence detection unit.

[0023] The edge coincidence detection unit processes the sampling results and generates a high-level narrow pulse output to the latch unit;

[0024] The latch unit receives the high-level narrow pulse and, after processing, generates a high-level pulse signal that lasts for a period of time, which serves as a flag signal for the coarse measurement section to stop counting. Thus, the coarse measurement section uses the product of the slow loop counter's count value n1 and the period of the slow self-timing loop, and the product of the fast loop counter's count value n2 and the period of the fast self-timing loop, and the difference between the two as the coarse measurement result.

[0025] The inputs of the two delay chains are the output signals of the fast and slow self-timing loops, respectively. The enable signals of the D flip-flops corresponding to the two delay chains are the high-level pulse signals output by the latch unit. These signals are used to control the D flip-flops corresponding to the two delay chains to stop coarse measurement and latch the current state of their own delay chains when the rising edge of the fast self-timing loop catches up with the rising edge of the slow self-timing loop, thereby obtaining the results of the fine measurement.

[0026] The high-precision, low-overhead two-stage differential TDC circuit based on a self-timing loop described in this invention is also characterized in that the latch unit is composed of an inverter W1 and a C unit.

[0027] The input of inverter W1 in the latch unit is connected to the output of the edge coincidence detection unit. The output of inverter W1 is connected to the input of unit C. The output of unit C is connected to the enable terminals of the D flip-flops corresponding to the two delay chains, respectively, to control the timing of the latching delay chain states of the D flip-flops corresponding to the two delay chains. The output of unit C is also connected to the fast-loop counter and the slow-loop counter, to stop the fast-loop counter and the slow-loop counter from counting at the edge coincidence time.

[0028] The edge coincidence detection unit consists of an inverter W2, a NAND gate, and a D flip-flop D2.

[0029] The input of inverter W2 is connected to the output of D flip-flop D1, and the output of inverter W2 is connected to one of the inputs of a two-input NAND gate. The D terminal of flip-flop D2 is connected to the output of D flip-flop D1.

[0030] Compared with existing technologies, the beneficial effects of this invention are reflected in:

[0031] 1. This invention utilizes a circuit structure consisting of a vernier STR ring composed of eight LUT6s in an FPGA and two symmetrical delay chains. While ensuring high resolution (14.8ps), the accuracy reaches 12.9ps, which is about 10ps higher than that of traditional circuits. The power consumption is only 0.068W, while the power consumption of traditional TDC circuits is 6 to 9 times that of this design.

[0032] 2. This invention overcomes the problem of large measurement error of the direct counting method by using a vernier self-timer loop (STR) instead of the direct counting method in the traditional coarse measurement stage, reduces the measurement time interval in the fine measurement stage, saves resource consumption, and reduces power consumption. The TDC structure in this invention is only 0.068W.

[0033] 3. This invention overcomes the problem of small measurement range of delay chain by adopting a combination of "coarse" and "fine" methods of vernier self-timing loop (STR) and delay chain. The measurement range of TDC structure in this invention can reach 491ns.

[0034] 4. This invention improves accuracy by further processing the time difference between the rising edges when the fast and slow STR edges coincide. The accuracy of the TDC structure in this invention can reach 12.8ps. Attached Figure Description

[0035] Figure 1 This is a structural diagram of the invented fourth-order self-timing loop (STR);

[0036] Figure 2 This is a schematic diagram of the invention's coarse measurement module;

[0037] Figure 3 This is a structural diagram of the edge coincidence detection module of the invention;

[0038] Figure 4 This is a structural diagram of the latch unit of the invention;

[0039] Figure 5 This is a schematic diagram of the delay chain in the fine testing phase of the invention. Detailed Implementation

[0040] In this embodiment, a high-precision, low-overhead two-stage differential TDC circuit based on a self-timing loop includes a coarse measurement section and a fine measurement section; such as Figure 2 As shown, the coarse measurement section consists of a fast self-timing loop, a slow self-timing loop, a fast loop counter, a slow loop counter, a D flip-flop D1, an edge coincidence detection unit, and a latching unit, as follows. Figure 1 As shown, the fast self-timing loop and the slow self-timing loop are two fourth-order self-timing loops STR with identical structures but different frequencies.

[0041] The structure of a self-timed loop is as follows: Figure 1As shown, when the inputs are the same, the output C retains the previous output value. When the inputs are different, the output C outputs a value opposite to that of the F terminal. The inverting input Bi of each Si is connected to the output Ci+1 of the next order, forming a feedback interconnected oscillation structure. Its truth table is shown in Table 1. This self-timing loop structure is implemented based on the six-input lookup table LUT6 in the Virtex-6 FPGA. A fourth-order self-timing loop requires four LUT6s. The initial value of LUT6 is set to 64'hBB00FFBB2200FF22. The positive input of the first lookup table LUT6-1 is connected to the output of LUT6-4, and the inverting input of LUT6-1 is connected to the output of LUT6-4. The positive input terminal of LUT6-2 is connected to the output terminal of LUT6-1; the negative input terminal of LUT6-2 is connected to the output terminal of LUT6-3; the positive input terminal of LUT6-3 is connected to the output terminal of LUT6-2; the negative input terminal of LUT6-3 is connected to the output terminal of LUT6-4; the positive input terminal of LUT6-4 is connected to the output terminal of LUT6-3; the negative input terminal of LUT6-4 is connected to the output terminal of LUT6-1, forming a feedback interconnection structure. The self-timing loop structure makes the circuit more robust, with a lower probability of jitter, thus resulting in more accurate measurement results.

[0042] Table 1

[0043] 0 0 HOLD 0 1 1 1 0 0 1 1 HOLD

[0044] Detailed measurement parts such as Figure 5 As shown, it consists of two delay chains with the same structure and symmetrical positions but different delay units. The inputs of the two delay chains are connected to the outputs of the fast self-timing loop and the slow self-timing loop, respectively.

[0045] The time interval between the Start signal and the Stop signal is set, and the Start signal and Stop signal are generated by an external clock module; a vernier structure composed of two fourth-order self-timing loops STR divides the time interval between the Start signal and the Stop signal into two time segments, and the two time segments are tested in parallel.

[0046] The Start signal is input into the slow self-timer loop to start the slow self-timer loop oscillation, and the slow loop counter receives the output of the slow self-timer loop.

[0047] The Stop signal is input into the fast self-timing loop to start the fast self-timing loop oscillation; the fast loop counter receives the output of the fast self-timing loop.

[0048] Slow-loop counters, such as Figure 2 As shown, before the edges coincide, the number of oscillations of the slow self-timer loop is counted to obtain the count value n1;

[0049] Fast-loop counters, such as Figure 2 As shown, before the edges coincide, the number of oscillations of the fast self-timing loop is counted to obtain the count value n2;

[0050] The output of the slow self-timer loop is as follows Figure 2 As shown, the output of the fast self-timer loop is as follows, serving as the D terminal of the D flip-flop D1 and the input terminal of the slow loop counter. Figure 2 As shown, it serves as the clock input of D flip-flop D1 and the input of the fast-loop counter;

[0051] The clock input of D1 in the D flip-flop is the output of the fast self-timer loop, and the D input of D1 is the output of the slow self-timer loop. Figure 2 As shown, this enables the fast self-timing loop to sample the slow self-timing loop. The sampling result Q has four possible states: several consecutive high levels, several consecutive low levels, a transition from low to high level, and a transition from high to low level. Only when the sampling result Q transitions from high to low level does it indicate that the fast self-timing loop has caught up with the slow self-timing loop. The D flip-flop D1 then sends the sampling result to the edge coincidence detection unit.

[0052] Edge coincidence detection unit, such as Figure 3 As shown, the device consists of an inverter W2, a NAND gate, and a D flip-flop D2. The input of inverter W2 is connected to the output Q of D flip-flop D1, and the output of inverter W2 is connected to one of the inputs of the two-input NAND gate. The D terminal of flip-flop D2 is connected to the output of D flip-flop D1. Therefore, when the input Q of the edge-coinciding detection unit is high, the output K of the edge-coinciding detection unit is low. When the input Q of the edge-coinciding detection unit changes from low to high, the output K of the edge-coinciding detection unit is low. Only when the input Q of the edge-coinciding detection unit changes from high to low does the edge-coinciding detection unit output a high-level narrow pulse signal, accurately locating the edge-coinciding moment, indicating that at this moment the fast self-timing loop catches up with the slow self-timing loop.

[0053] After processing the sampling result Q, the edge coincidence detection unit generates a high-level narrow pulse output to the latch unit. The output K of the edge coincidence detection unit is a high-level narrow pulse. After the edge coincidence moment, K will become low again. The high level has a short duration, so K cannot be directly used as a control signal and needs to be input to the latch unit for processing.

[0054] latch unit such as Figure 4As shown, the latch unit consists of an inverter W1 and a C unit. The input of the inverter W1 is connected to the output of the edge coincidence detection unit, and the output of the inverter W1 is connected to the input of the C unit. The output of the C unit is connected to the enable terminals of the D flip-flops corresponding to the two delay chains, respectively, to control the timing of the latching delay chain states of the D flip-flops. The output of the C unit is also connected to both the fast-loop counter and the slow-loop counter, used to stop the fast-loop counter and the slow-loop counter from counting at the edge coincidence moment. Figure 4 As shown, the input of the latch unit is the output K of the edge coincidence detection unit, and the B input of the C unit is set to 1. Only when K is a high-level narrow pulse signal will the output DETECT signal of the latch unit output a high-level pulse signal for a period of time, as shown in Table 2, indicating that the edge coincides at this moment. Figure 2 and Figure 5 The DETECT signal serves as a feedback signal to stop the slow-loop counter and the fast-loop counter from counting, preventing the two counters from continuing to count after the edges coincide, which would cause measurement errors. At the same time, it latches the state of the two delay chains in the fine measurement section at this moment.

[0055] The latch unit receives a narrow high-level pulse, processes it to generate a high-level pulse signal that lasts for a period of time, and uses this as a flag signal for the coarse measurement section to stop counting. The coarse measurement section then uses the count value n1 of the slow-loop counter and the period T of the slow self-timing loop to determine the starting point. s The product of the count value n2 of the fast-loop counter and the period T of the fast self-timer loop. f The product of the two is used as the rough measurement result, and the rough measurement result is shown in equation (1).

[0056] T coarse =(n1-n2)T s +n2(T s -T f (1)

[0057] Table 2

[0058] 0 0 0 1 0 0 0 1 0 1 1 1

[0059] The inputs to the two delay chains are the output signals of the fast and slow self-timing loops, respectively. The enable signals of the D flip-flops corresponding to the two delay chains are high-level pulse signals output by the latch unit. These pulses control the D flip-flops of the two delay chains to stop coarse measurement and latch the current state of their respective delay chains when the rising edge of the fast self-timing loop catches up with the rising edge of the slow self-timing loop, thereby obtaining the results of the fine measurement section. Figure 5 As shown, by symmetrical placement and routing of the two delay chains, the effects of temperature, voltage, etc., on them are approximately equal. At the moment of edge coincidence, the DETECT signal controls the D flip-flop to latch the state of the delay chain and output. The detailed measurement result T is obtained through differential grading. fineThe present invention utilizes a delay chain to process the time deviation at the moment of edge coincidence, thereby improving the measurement accuracy. The measurement result of the time interval to be measured is shown in Equation (2).

[0060] T = T coarse -T fine (2) The basic steps for designing a time-to-digital converter on a Virtex-6 FPGA using this invention are as follows:

[0061] Step 1: Taking into account the application scenario requirements, determine the system architecture framework of the time-to-digital converter;

[0062] Step 2: Using a top-down design approach, the entire system is divided into a coarse measurement section and a fine measurement section. The coarse measurement section is further divided into a vernier self-timing loop, an edge coincidence detection unit, and a latching unit. The fine measurement section includes two symmetrical delay chains.

[0063] Step 3: Design the corresponding RTL circuit on ISE14.7 and configure the initial value of STR to be 64'hBB00FFBB2200FF22;

[0064] Step 4: Interconnect the corresponding input and output ports of each module; the basic circuit structure is now complete.

[0065] Step 5: Create a new .ucf file and constrain the two delay chains from the fine testing phase to symmetrical positions;

[0066] Step 6: Download the program, send the output of the time-to-digital converter via serial port, and calculate the measurement result;

[0067] Step 7: Repeat the measurement multiple times at a fixed time interval to obtain a set of data, and perform multiple measurements at different time intervals to obtain multiple sets of data, and analyze the various performance indicators of the time-to-digital converter of the present invention.

[0068] To illustrate the positive effects of the present invention, the proposed high-precision, low-overhead two-stage differential TDC circuit based on a self-timing loop was designed and implemented using the Xilinx Virtex-6 platform.

[0069] Table 3 Truth table of the fourth-order self-timed loop (STR) of the invention.

[0070]

[0071] Table 3 shows a comparison of various indicators. The power consumption of this invention is only 0.068W, requiring only 259 LUTS, which greatly reduces resource consumption. Moreover, compared with other structures, this invention also has advantages in resolution and accuracy, with a resolution of 14.8ps and an accuracy of 12.9ps, indicating that the structure of this invention can simultaneously achieve high accuracy and low power consumption.

[0072] In summary, this invention proposes a high-precision, low-overhead two-stage differential TDC circuit structure based on a self-timing loop. In the coarse measurement stage, a vernier self-timing loop (STR) replaces the direct counting method, reducing the processing time interval in the fine measurement stage, thereby reducing resource consumption and power consumption. Furthermore, compared to a ring oscillator, the self-timing loop circuit exhibits better robustness. In the fine measurement stage, two symmetrical delay chains are used to process the error in the timing of the fast STR catching up with the slow STR in the vernier self-timing loop, resulting in higher measurement accuracy. The entire TDC circuit structure can be used in various integrated circuit testers.

Claims

1. A high-precision, low-overhead two-stage differential TDC circuit based on a self-timing loop, characterized in that, include: The measurement section consists of a coarse measurement section and a fine measurement section. The coarse measurement section comprises a fast self-timing loop, a slow self-timing loop, a fast loop counter, a slow loop counter, a D flip-flop D1, an edge coincidence detection unit, and a latching unit. The fast self-timing loop and the slow self-timing loop are two identical fourth-order self-timing loops STR with different frequencies. The fine measurement section consists of two delay chains with identical structures and symmetrical positions, but with different delay units. The output of the slow self-timed loop serves as the D terminal of the D flip-flop D1 and the input terminal of the slow loop counter. The output of the fast self-timing loop serves as the clock terminal of the D flip-flop D1 and the input terminal of the fast loop counter. The clock terminal of the D flip-flop D1 is the output terminal of the fast self-timer loop, and the D terminal of the D flip-flop D1 is the output terminal of the slow self-timer loop. The inputs of the two symmetrical delay chains in the fine measurement section are respectively connected to the outputs of the fast self-timing loop and the slow self-timing loop. The time interval between the Start signal and the Stop signal is set, and the Start signal and Stop signal are generated by an external clock module; a vernier structure composed of two fourth-order self-timing loops STR divides the time interval between the Start signal and the Stop signal into two time segments, and the two time segments are tested in parallel. The Start signal is input into the slow self-timer to cause the slow self-timer loop to oscillate, and the slow loop counter receives the output of the slow self-timer loop. The Stop signal is input into the fast self-timing loop to cause it to oscillate; the fast loop counter receives the output of the fast self-timing loop. The slow-loop counter counts the number of oscillations of the slow self-timer loop before the edges coincide, and obtains the count value n1. The fast-loop counter counts the number of oscillations of the fast self-timer loop before the edges coincide, and obtains the count value n2; The fast self-timing loop samples the slow self-timing loop. When the sampling result changes from high level to low level, it indicates that the fast self-timing loop has caught up with the slow self-timing loop. The D flip-flop D1 then sends the sampling result to the edge coincidence detection unit. The edge coincidence detection unit processes the sampling results and generates a high-level narrow pulse output to the latch unit; The latch unit receives the high-level narrow pulse and, after processing, generates a high-level pulse signal that lasts for a period of time, which serves as a flag signal for the coarse measurement section to stop counting. Thus, the coarse measurement section uses the product of the slow loop counter's count value n1 and the period of the slow self-timing loop, and the product of the fast loop counter's count value n2 and the period of the fast self-timing loop, and the difference between the two as the coarse measurement result. The inputs of the two delay chains are the output signals of the fast and slow self-timing loops, respectively. The enable signals of the D flip-flops corresponding to the two delay chains are the high-level pulse signals output by the latch unit. These signals are used to control the D flip-flops corresponding to the two delay chains to stop coarse measurement and latch the current state of their own delay chains when the rising edge of the fast self-timing loop catches up with the rising edge of the slow self-timing loop, thereby obtaining the results of the fine measurement.

2. The high-precision, low-overhead two-stage differential TDC circuit based on a self-timing loop according to claim 1, characterized in that, The latch unit consists of an inverter W1 and a C unit; The input of inverter W1 in the latch unit is connected to the output of the edge coincidence detection unit. The output of inverter W1 is connected to the input of unit C. The output of unit C is connected to the enable terminals of the D flip-flops corresponding to the two delay chains, respectively, to control the timing of the latching delay chain states of the D flip-flops corresponding to the two delay chains. The output of unit C is also connected to the fast-loop counter and the slow-loop counter, to stop the fast-loop counter and the slow-loop counter from counting at the edge coincidence time.

3. The high-precision, low-overhead two-stage differential TDC circuit based on a self-timing loop according to claim 1, characterized in that, The edge coincidence detection unit consists of an inverter W2, a NAND gate, and a D flip-flop D2. The input of inverter W2 is connected to the output of D flip-flop D1, and the output of inverter W2 is connected to one of the inputs of a two-input NAND gate. The D terminal of flip-flop D2 is connected to the output of D flip-flop D1.

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