一种兼容多码长码率的Polar码译码器及译码方法
By designing a Polar code decoder compatible with multiple code lengths and rates, and employing parallel and pipelining computing arrays and linked list storage schemes, hardware resource utilization is optimized, solving the problem of high hardware resource consumption in Polar code implementation on FPGA, and improving the decoder's throughput and code rate configuration flexibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIHANG UNIV
- Filing Date
- 2022-12-12
- Publication Date
- 2026-07-17
AI Technical Summary
In existing technologies, Polar codes can only be implemented at a single code rate in FPGA implementations, which consumes huge hardware resources. Furthermore, the computational complexity of the serial list cancellation decoding algorithm is high, making it difficult to meet the needs of multiple code lengths and rates.
A Polar code decoder compatible with multiple code lengths and rates was designed. It adopts a parallel and pipelined switchable computing array, a log-likelihood ratio storage structure, a hybrid expansion and folding partial and update circuit, and a linked list decoding path storage scheme, which optimizes the utilization of computing units and storage resource consumption.
It improves the decoder's throughput rate with the same hardware resource consumption, supports arbitrary code length and code rate configuration, and reduces hardware resource consumption and computational complexity.
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Figure CN116405039B_ABST