Display panel, preparation method thereof and display device

Abstract

The application provides a display panel, a preparation method thereof and a display device. The display panel comprises a display area, and comprises: a substrate; a metal wiring layer located on one side of the substrate, the metal wiring layer comprising a first reference voltage signal line, the first reference voltage signal line having a mesh structure, and the first reference voltage signal line comprising a plurality of first access holes; and a light emitting device layer located on the side of the metal wiring layer away from the substrate, the light emitting device layer comprising sub-pixels of multiple colors; wherein the first reference voltage signal line is electrically connected to the sub-pixels of multiple colors through the plurality of first access holes, so that at least part of the first reference voltage signal line is arranged in a non-periodic manner in the display area, which is beneficial to improving the low gray scale display effect, avoiding the problems of low gray scale display color deviation and low gray scale brightness unevenness caused by the first reference voltage signal line accessing the sub-pixels of a fixed color, and further improving the performance of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and its manufacturing method, and a display device. Background Technology

[0002] Active-matrix organic light-emitting diodes (AMOLEDs) offer advantages such as wide viewing angles, ultra-high contrast ratios, low power consumption, and fast response times due to their relatively complex circuit architecture. However, the insufficient electrical uniformity of low-grayscale thin-film transistors (TFTs) leads to uneven brightness (mura) and color shift in AMOLED displays at low brightness levels. Inside the AMOLED panel, the sub-pixel circuitry primarily compensates for the operating threshold voltage (Vth) characteristics of the driving TFTs. However, this compensation method cannot completely compensate for brightness unevenness. Therefore, the display panel suffers from low-grayscale display unevenness and low-grayscale color shift issues. Summary of the Invention

[0003] In view of this, this application provides a display panel and its manufacturing method, as well as a display device, to solve the problems of uneven low grayscale display and low grayscale color deviation in display panels.

[0004] A first aspect of this application provides a display panel including a display area. The display panel includes: a substrate; a metal wiring layer located on one side of the substrate, the metal wiring layer including first reference voltage signal lines having a mesh structure and including a plurality of first access holes; and a light-emitting device layer located on the side of the metal wiring layer opposite to the substrate, the light-emitting device layer including sub-pixels of multiple colors; wherein the first reference voltage signal lines are randomly electrically connected to the sub-pixels of multiple colors through the plurality of first access holes, so that at least a portion of the first reference voltage signal lines are arranged in a non-periodic regular pattern in the display area.

[0005] In one specific embodiment of the first aspect of this application, the first reference voltage signal line includes multiple first vertical traces, and the first vertical traces are connected to the sub-pixel through a first access hole;

[0006] Preferably, the sub-pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and multiple first vertical traces are respectively connected to the first sub-pixel, the second sub-pixel, and the third sub-pixel through multiple first access holes.

[0007] In a specific embodiment of the first aspect of this application, the first reference voltage signal line includes a plurality of first lateral traces, which extend along a first direction and are spaced apart along a second direction, and a plurality of first longitudinal traces extend along the second direction and are spaced apart along the first direction; a first access hole is provided at the intersection of the projections of the first lateral traces and the first longitudinal traces on the substrate, wherein the first direction and the second direction intersect.

[0008] In one specific embodiment of the first aspect of this application, the metal wiring layer further includes a second reference voltage signal line, the second reference voltage signal line including a plurality of second access holes, the second reference voltage signal line being randomly electrically connected to sub-pixels of various colors through the plurality of second access holes, so that at least a portion of the second reference voltage signal lines are arranged in a non-periodic regular pattern in the display area.

[0009] In one specific embodiment of the first aspect of this application, the orthographic projection of sub-pixels of the same color onto the metal wiring layer respectively covers any one or a combination of the first access hole and the second access hole.

[0010] In a specific embodiment of the first aspect of this application, the second reference voltage signal line includes multiple second vertical traces, and the access structure between the second vertical traces and the sub-pixel is a second access hole; preferably, the second reference voltage signal line includes multiple second horizontal traces and multiple second vertical traces, the multiple second horizontal traces extend along a first direction and are spaced apart along a second direction, and the multiple second vertical traces extend along a second direction and are spaced apart along the first direction; a second access hole is provided at the intersection of the projections of the second horizontal traces and the second vertical traces on the substrate, wherein the first direction and the second direction intersect.

[0011] A second aspect of this application provides a method for manufacturing a display panel. The method includes: providing a substrate; forming a metal wiring layer on one side of the substrate, the metal wiring layer including reference voltage signal lines arranged in a mesh structure; forming a light-emitting device layer on the side of the metal wiring layer away from the substrate, the light-emitting device layer including sub-pixels of multiple colors, and electrically connecting the reference voltage signal lines to the sub-pixels of multiple colors according to a predetermined random access scheme, so that at least a portion of the reference voltage signal lines are arranged in a non-periodic regular pattern in the display area of ​​the display panel.

[0012] In a specific embodiment of the second aspect of this application, the method for determining a predetermined random access scheme includes: acquiring a simulation image, the simulation image including a predetermined sub-pixel array and reference voltage signal lines arranged on the predetermined sub-pixel array, the reference voltage signal lines including multiple transverse traces extending along a first direction and spaced apart along a second direction; determining a target base block corresponding to each sub-pixel in the predetermined sub-pixel array according to a predetermined strategy, the target base block being selected from any of a variety of preset base blocks corresponding to the color of a pre-stored sub-pixel, the criteria for dividing the preset base blocks including whether the reference voltage signal lines contain longitudinal traces extending along the second direction and spaced apart along the first direction, and the signal type of the reference voltage signal lines; arranging the target base blocks at the corresponding sub-pixels to obtain a wiring diagram of the reference voltage signal lines; preferably, determining the target base block corresponding to each sub-pixel in the predetermined sub-pixel array according to a predetermined strategy includes: generating a predetermined number of random numbers, the number of random numbers depending on the number of sub-pixels in the simulation image; sequentially assigning the predetermined number of random numbers to each sub-pixel in the simulation image; establishing a correspondence between multiple random numbers and preset base blocks according to predetermined rules; for each sub-pixel, selecting a base block that matches the random number corresponding to the sub-pixel as the target base block.

[0013] In a specific embodiment of the second aspect of this application, establishing a correspondence between multiple random numbers and a preset basic block according to a predetermined rule includes: dividing the numerical range of the multiple random numbers into multiple sub-ranges; and mapping the multiple sub-ranges to the preset basic block one by one.

[0014] A third aspect of this application provides a display device that includes the display panel mentioned in the first aspect.

[0015] In the display panel provided in this application embodiment, the first reference voltage signal line presents a mesh structure. The first reference voltage signal line includes multiple first access holes. The first reference voltage signal line is randomly electrically connected to sub-pixels of various colors through the multiple first access holes, so that at least some of the first reference voltage signal lines present a non-periodic regular arrangement in the display area. This is beneficial to improve the low grayscale display effect and avoid the problems of low grayscale color deviation and low grayscale brightness unevenness caused by the first reference voltage signal line being connected to a fixed color sub-pixel during the initialization stage, thereby further improving the performance of the display panel. Attached Figure Description

[0016] Figure 1a This is a schematic diagram of the planar structure of a display panel provided in one embodiment of this application.

[0017] Figure 1b This is a schematic diagram of the cross-sectional structure of a display panel along the thickness direction provided in one embodiment of this application.

[0018] Figure 2This is a partial structural diagram of the display area provided in one embodiment of this application.

[0019] Figure 3 This is a schematic diagram of the planar structure of a display panel provided in another embodiment of this application.

[0020] Figure 4 This is a partial structural diagram of a dual-reference voltage network structure provided in one embodiment of this application.

[0021] Figure 5 This is a partial structural diagram of a dual-reference voltage network structure in the prior art.

[0022] Figure 6a This is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application.

[0023] Figure 6b This is a schematic flowchart illustrating a method for manufacturing a display panel according to another embodiment of this application.

[0024] Figure 7 This is a schematic flowchart illustrating a method for manufacturing a display panel according to another embodiment of this application.

[0025] Figure 8 This is a schematic flowchart illustrating a method for manufacturing a display panel according to another embodiment of this application.

[0026] Figure 9 The diagram shown is a structural schematic of a display device provided in an embodiment of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] With the continuous development of display technology, AMOLED display panels are becoming increasingly common. AMOLED boasts advantages such as low manufacturing cost, high response speed, energy saving, DC drive capability for portable devices, and a wide operating temperature range, making it a promising next-generation flat panel display to replace LCD (Liquid Crystal Display). Flexible AMOLED, in particular, is gaining increasing market attention due to its advantages of being thin, flexible, foldable, and capable of being arbitrarily shaped.

[0029] However, AMOLED display technology still has significant drawbacks. During the manufacturing process, due to factors such as materials and processes, AMOLED panels are not uniformly manufactured, and differences in individual driving TFTs and components can lead to uneven brightness distribution in some products, a phenomenon known as mura. Although various brightness compensation algorithms exist to compensate for the uniformity of display devices, various errors still exist; for example, the compensation circuit may not fully compensate at low grayscale levels.

[0030] Furthermore, these uneven brightness spots can cause visual discomfort, and products with such defects cannot meet the specifications of end customers, generally requiring scrapping or downgrading. External compensation systems for AMOLED manufacturing processes use advanced sub-pixel-level optical imaging technology and software algorithms to eliminate Mura patterns (i.e., demura, essentially beautifying the display), ensuring the display quality meets the panel manufacturer's shipping specifications and improving the yield rate of mass production.

[0031] The Demura algorithm works by either darkening overly bright areas, brightening overly dark areas, or eliminating areas with color casts, ultimately aiming to make the brightness and color of different areas of the panel roughly the same. While performing Demura processing on every pixel in principle could yield good results, its efficiency is low due to limitations. It cannot compensate for pixel work, which is a major reason for color casts and uneven brightness in low-grayscale displays.

[0032] In addition, as display panels move towards higher resolutions and higher refresh rates, many high refresh rate applications, whether in computers or mobile phones, lead to limited storage capacity and increasingly serious charging problems. Insufficient charging time significantly impacts the normal display of LCD panels, causing many adverse phenomena, such as color shift issues.

[0033] In view of this, this application provides a display panel and its manufacturing method, as well as a display device, to solve the problems of uneven low grayscale display and low grayscale color deviation in existing display panels.

[0034] Figure 1a This is a schematic diagram of the planar structure of a display panel provided in one embodiment of this application. Figure 1b This is a schematic diagram of the cross-sectional structure of a display panel along the thickness direction provided in one embodiment of this application. Figure 2 This is a partial structural diagram of the display area provided in one embodiment of this application. Figure 3 This is a schematic diagram of the planar structure of a display panel provided in another embodiment of this application. Figure 1aAs shown, the display panel 1 includes a display area 10 and a non-display area 20, with the non-display area 20 surrounding the display area 10. The display area 10 can be used for image display, while the non-display area 20 is an area where images are not displayed. Figures 1b to 3 As shown, the display panel 1 includes: a substrate 30; a metal wiring layer 11 located on one side of the substrate 30, the metal wiring layer 11 including a first reference voltage signal line 100, the first reference voltage signal line 100 having a mesh structure, the first reference voltage signal line 100 including a plurality of first access holes 101; a light-emitting device layer 13 located on the side of the metal wiring layer 11 opposite to the substrate 30, the light-emitting device layer 13 being stacked with the metal wiring layer 11; the light-emitting device layer 13 including sub-pixels 12 of various colors; wherein, the first reference voltage signal line 100 is randomly electrically connected to the sub-pixels 12 of various colors through the plurality of first access holes 101, so that at least a portion of the first reference voltage signal line 100 is arranged in a non-periodic regular pattern in the display area 10. Specifically, as reflected in the figure, at least a portion of the first access holes 101 may be arranged in a non-periodic regular pattern in the display area 10.

[0035] The metal wiring layer 11 is used to provide driving signals to the display panel 1 so that the display panel 1 can realize the display function. In the prior art, the electrical connection between the first reference voltage signal line 100 and the sub-pixel 12 through multiple first access holes 101 is connected in a fixed color. The regularization of the reference voltage connection will result in the initialization effect of the fixed color sub-pixel 12 being good or bad, thus causing problems such as low grayscale color spots and color shift. For example, the first access hole 101 of the first reference voltage signal line 100 is fixed in a sub-pixel (R) of a certain color, resulting in the strongest driving force on the sub-pixel (R) of the fixed color. Sub-pixels (G / B) of other colors need to be connected to the reference voltage signal by winding, which is equivalent to weakening the driving force of the reference voltage signal. The regularization of the access of the first reference voltage signal line 100 results in a good initialization effect for the fixed color sub-pixel (R) and a poor initialization effect for other sub-pixels (G / B), resulting in problems such as low grayscale color spots and color shift. For example, if the brightness of the sub-pixel of color R is too strong, it will result in a low grayscale pinkish mura, and if the brightness of the sub-pixel of color G / B is too strong, it will result in a low grayscale greenish / cyanish mura, etc.

[0036] The display panel provided in this application embodiment has a first reference voltage signal line 100 with a mesh structure. The first reference voltage signal line 100 includes a plurality of first access holes 101. The first reference voltage signal line 100 is randomly electrically connected to sub-pixels 12 of various colors through the plurality of first access holes 101, so that at least some of the first reference voltage signal lines 100 are arranged in a non-periodic regular pattern in the display area 10, thereby improving the low grayscale display effect and avoiding the problems of low grayscale color deviation and low grayscale brightness unevenness caused by the first reference voltage signal line 100 being connected to a fixed color sub-pixel during the initialization stage, thereby further improving the performance of the display panel.

[0037] In some embodiments, combined with Figure 2 and Figure 3 As shown, the first reference voltage signal line 100 includes multiple first vertical traces 1002. The connection structure between the first vertical traces 1002 and the sub-pixel 12 is a first access hole 101, as shown below. Figure 3 As shown, sub-pixel 12 includes a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B. Multiple first vertical lines 1002 are connected to the first sub-pixel R, the second sub-pixel G, and the third color sub-pixel B respectively through multiple first access holes 101.

[0038] The first access hole 101 is the access structure between the first vertical trace 1002 of the first reference voltage signal line 100 and the sub-pixel 12, and the access structure between the first vertical trace 1002 and the sub-pixel 12 is arranged in a non-periodic, regular pattern. The orthographic projection of multiple first access holes 101 on the light-emitting device layer 13 falls within a portion of the sub-pixels, which includes sub-pixels of various colors. That is, the orthographic projection of the access structure between the first vertical trace 1002 and the sub-pixel 12 on the light-emitting device layer 13 can fall within the first sub-pixel R, or within the second sub-pixel G, and / or within the third sub-pixel B.

[0039] like Figure 3 As shown, the light-emitting device layer 13 includes multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel R emitting a first color light, a second sub-pixel G emitting a second color light, and a third sub-pixel B emitting a third color light. Each sub-pixel 12 includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit includes a thin-film transistor, a storage capacitor Cst, and an initialization signal input terminal Vref. The initialization signal input terminal Vref is electrically connected to the output terminal of the initialization module of the display panel. The initialization signal input terminal Vref corresponds to a first reference voltage signal line 100, which is used to provide an initialization signal to the sub-pixel driving circuit. The light-emitting element in each sub-pixel 12 is connected to the sub-pixel driving circuit of its respective sub-pixel 12. The light-emitting element is configured to emit light of corresponding brightness in response to the current output by the sub-pixel driving circuit of its respective sub-pixel 12. The sub-pixels 12 of various colors included in the pixel unit P are arranged according to a predetermined rule. The arrangement of the sub-pixels 12 includes RGBG, GGRB, RGB, etc.

[0040] In some embodiments, the first sub-pixel R is a red sub-pixel (R) that emits red light, and the sub-pixel driving circuit of the first sub-pixel R is electrically connected to the anode of the light-emitting element that emits red light. The second sub-pixel G can be a green sub-pixel (G) that emits green light, and the sub-pixel driving circuit of the second sub-pixel G is electrically connected to the anode of the light-emitting element that emits green light. The third sub-pixel B is a blue sub-pixel (B) that emits blue light, and the sub-pixel driving circuit of the third sub-pixel B is electrically connected to the anode of the light-emitting element that emits blue light. The first sub-pixel R, the second sub-pixel G, and the third sub-pixel B can also be other colors, and this application does not specifically limit them.

[0041] In some embodiments, a pixel unit P may include four sub-pixels, which may be arranged in a horizontal or vertical manner, etc., and this application does not limit the arrangement.

[0042] The display panel provided in this application embodiment includes a first reference voltage signal line 100 comprising multiple first vertical traces 1002. The connection structure between the first vertical traces 1002 and the sub-pixels 12 is a first access hole 101. By randomly connecting the first vertical traces 1002 to sub-pixels 12 of various colors in the Y direction, the spatial periodicity is disrupted, avoiding the problem of exacerbating color shift and low grayscale mura in the original regularized access scheme.

[0043] Sub-pixel 12 includes a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B. Multiple first vertical lines 1002 are connected to the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B. By randomly connecting multiple first vertical lines 1002 of the first reference voltage signal line 100 to sub-pixels 12 of various colors, the initial brightness distribution of sub-pixels 12 is disrupted, thus avoiding the problems of uneven low-grayscale display and low-grayscale color shift.

[0044] Continue as Figure 2 As shown, the first reference voltage signal line 100 includes multiple first lateral traces 1001, which extend along a first direction X and are spaced apart along a second direction Y. Multiple first longitudinal traces 1002 extend along the second direction Y and are spaced apart along the first direction X. A first access hole 101 is provided at the intersection of the projections of the first lateral traces 1001 and the first longitudinal traces 1002 on the substrate 30, wherein the first direction X and the second direction Y intersect. Further, the first direction X and the second direction Y are perpendicular.

[0045] The display panel provided in this application embodiment has a first access hole 101 at the intersection of the projections of the first horizontal trace 1001 and the first vertical trace 1002 on the substrate 30. This makes at least some of the first access holes 101 appear in a non-periodic regular arrangement in the display area 10, thereby disrupting the regular distribution of the initial brightness of the sub-pixels 12, improving the low grayscale display effect, and avoiding low grayscale mura or color shift problems caused by the regularization of reference voltage access.

[0046] Currently, LTPS-AMOLED displays are exhibiting dual-reference voltage network structures. By optimizing the traditional single Vref trace into two independent Vref traces, the display performance of the product is significantly improved. Specifically, TFTs are used to reset the anode of the light-emitting element. Different TFTs can be connected to the same reference voltage signal, which is a single-reference voltage network structure. Alternatively, different TFTs can be connected to different reference voltage signals, in which case the two TFTs are connected to two different reference voltage signals, which is a dual-reference voltage network structure.

[0047] Figure 4 This is a partial structural diagram of a dual-reference voltage network structure provided in another embodiment of this application. For example... Figure 4 As shown, the metal wiring layer 11 includes a first reference voltage signal line 100 and a second reference voltage signal line 102. The first reference voltage signal line 100 and the second reference voltage signal line 102 form a mesh structure in the metal wiring layer 11, constituting a dual reference voltage network structure. The second reference voltage signal line 102 includes a plurality of second access holes 103. The second reference voltage signal line 102 is randomly electrically connected to sub-pixels 12 of various colors through the plurality of second access holes 103, so that at least a portion of the second reference voltage signal lines 102 are arranged in a non-periodic regular pattern in the display area 10. Specifically, the non-periodic regular pattern can be manifested as a non-periodic regular pattern of the second access holes 103 in the display area 10.

[0048] The orthographic projection of the multiple second access holes 103 onto the light-emitting device layer 13 can fall within the first color sub-pixel R, the second color sub-pixel G, or the third color sub-pixel B.

[0049] Specifically, the first reference voltage signal line 100 and the second reference voltage signal line 102 represent different reference voltage signals. The first reference voltage signal line 100 is used to initialize the storage capacitor in the sub-pixel driving circuit. The second reference voltage signal line 102 is used to initialize the anode of the sub-pixel.

[0050] In addition, the specific values ​​of the reference voltage signals represented by the first reference voltage signal line 100 and the second reference voltage signal line 102 can be determined according to the voltage range of the display drive signal. The range of the display drive signal is 0 to 6V, and the value of the reference voltage signal can be set to about 0V. Of course, it can also be set to other values ​​according to the actual situation.

[0051] The display panel provided in this application embodiment comprises a first reference voltage signal line 100 and a second reference voltage signal line 102 forming a dual reference voltage network structure. The second reference voltage signal line 102 includes a plurality of second access holes 103. The second reference voltage signal line 102 is randomly electrically connected to sub-pixels 12 of various colors through the plurality of second access holes 103, so that at least some of the second reference voltage signal lines 1023 are arranged in a non-periodic regular pattern in the display area 10, thereby improving the low grayscale display effect and avoiding the problems of color shift and uneven brightness in low grayscale display caused by the fixed access of the second reference voltage signal line 102 to the sub-pixels, further improving the performance of the display panel.

[0052] In some embodiments, continue to refer to Figure 4 As shown, the orthographic projections of sub-pixels 12 of the same color onto the metal wiring layer 11 respectively cover any one or a combination of the first access hole 101 and the second access hole 103. For example, Figure 4 All sub-pixels 12 are arranged in RGBRGBRGB. From left to right, the orthographic projection of the first column of sub-pixels R onto the metal wiring layer 11 does not cover any access holes. The orthographic projection of the second column of sub-pixels G onto the metal wiring layer 11 covers the first access hole 101, and the orthographic projection of the second column of sub-pixels G onto the metal wiring layer 11 covers both the first access hole 101 and the second access hole 103.

[0053] In some embodiments, for a dual-reference voltage mesh structure, the connection method of the first reference voltage signal line 100 and the second reference voltage signal line 102 in the Y direction on the metal wiring layer 11 of the display panel 1 can be changed from fixed-color sub-pixel access to random-color sub-pixel access. The conventional solution in the prior art is as follows: Figure 5As shown, all sub-pixels 12 are arranged in RGBRGBRGB. In the Y direction, sub-pixels of a fixed color (RG) are connected to the first reference voltage signal line 100, and other sub-pixels of fixed colors (B) are connected to the second reference voltage signal line 102. Of course, other connection methods are also possible, such as sub-pixels (RG) being connected to the second reference voltage signal line 102 and sub-pixels (B) being connected to the first reference voltage signal line 100. This application randomly connects the first reference voltage signal line 100 and the second reference voltage signal line 102 to the R / G / B sub-pixels, so that the orthographic projection of sub-pixels 12 of the same color on the metal wiring layer 11 can cover any one or a combination of the first access hole 101 and the second access hole 103. This method can eliminate the mura / color shift problem caused by the layout design determining that the sub-pixels of fixed colors are well charged or poorly charged during the initialization period.

[0054] In some embodiments, such as Figure 4 As shown, the second reference voltage signal line 102 includes multiple second vertical traces 1022, and the second vertical traces 1022 correspond to the access structure of the sub-pixel 12 with the second access hole 103.

[0055] Preferably, the second reference voltage signal line 102 includes multiple second lateral traces 1021 and multiple second longitudinal traces 1022. The multiple second lateral traces 1021 extend along the first direction X and are spaced apart along the second direction Y. The multiple second longitudinal traces 1022 extend along the second direction Y and are spaced apart along the first direction X. A second access hole 103 is provided at the intersection of the projections of the second lateral traces 1021 and the second longitudinal traces 1022 on the substrate 30, wherein the first direction X and the second direction Y intersect.

[0056] In some embodiments, continue as follows Figure 4 As shown, the first horizontal trace 1001 and the second horizontal trace 1021 are electrically connected to the sub-pixel 12, respectively. By changing the connection method of multiple first vertical traces 1002 and multiple second vertical traces 1022 in the Y direction from fixed-color sub-pixel access to random-color sub-pixel access, the reference voltage signal can be randomly accessed, so that the multiple first access holes 101 and second access holes 103 present a non-periodic regular arrangement. Specifically, for the sub-pixel 12 of the same color, its wiring method in the Y direction includes: no vertical signal line is connected to the first horizontal trace 1001 and the second horizontal trace 1021 (e.g., Figure 4 In the middle, the orthographic projection of the sub-pixel 12 in the first row and first column from left to right on the metal wiring layer 11 does not cover the access hole), the first vertical trace 1002 is connected to the first horizontal trace 1001 (e.g. Figure 4In the middle, the orthographic projection of the sub-pixel 12 in the first row and fourth column from left to right onto the metal wiring layer 11 can cover the first access hole 101), the second vertical trace 1022 and the second horizontal trace 1021 are connected (e.g. Figure 4 In the middle, the orthographic projection of the sub-pixel 12 in the first row and seventh column from left to right on the metal wiring layer 11 can cover the second access hole 103), and the first vertical trace 1002 is connected to the first horizontal trace 1001, while the second vertical trace 1022 is connected to the second horizontal trace 1021 (e.g. Figure 4 In the middle, the orthographic projection of sub-pixel 12 in the third row and tenth column from left to right onto the metal wiring layer 11 simultaneously covers the first access hole 101 and the second access hole 103.

[0057] The display panel provided in this application embodiment includes a second reference voltage signal line 102 comprising multiple second vertical traces 1022. The connection structure between the second vertical traces 1022 and the sub-pixels 12 is a second access hole 103. By randomly connecting the second vertical traces 1022 to sub-pixels 12 of various colors in the Y direction, the spatial periodicity is disrupted, avoiding the problem of exacerbating color shift and low grayscale mura in the original regularized access scheme.

[0058] In some embodiments, the sum of the number of horizontal and vertical traces in a single-reference voltage mesh structure / dual-reference voltage mesh structure is equal to the number of traces in a conventional mesh structure, or meets the product's electrical design requirements, thereby ensuring that the local electrical properties of the display panel remain unchanged.

[0059] In some embodiments, the reference voltage signal is randomly accessed to the sub-pixel 12, either randomly based on the entire display area 10 or by dividing the display area 10 into multiple blocks, with each block randomly accessed with the reference voltage signal. The block size can be the number of rows M * the number of columns N, where M and N can be the maximum number of rows and columns of the sub-pixel 12.

[0060] Figure 6a This is a schematic flowchart illustrating a method for fabricating a display panel according to an embodiment of this application. Figure 6a As shown, the preparation method includes the following steps.

[0061] Step 610: Provide a substrate.

[0062] Step 620: A metal wiring layer is formed on one side of the substrate.

[0063] The metal wiring layer includes reference voltage signal lines arranged in a mesh structure. Each reference voltage signal line includes multiple access holes.

[0064] Step 630: A light-emitting device layer is formed on the side of the metal wiring layer away from the substrate.

[0065] The light-emitting device layer includes sub-pixels of various colors, and reference voltage signal lines are electrically connected to the sub-pixels of various colors according to a predetermined random access scheme, so that at least some of the reference voltage signal lines are arranged in a non-periodic regular pattern in the display area of ​​the display panel. Specifically, at least some of the access holes are arranged in a non-periodic pattern in the display area of ​​the display panel.

[0066] The method for manufacturing a display panel provided in this application involves electrically connecting reference voltage signal lines to sub-pixels of various colors according to a predetermined random access scheme. This allows at least some reference voltage signal lines to be arranged in a non-periodic, regular pattern in the display area of ​​the display panel, improving the low grayscale display effect and avoiding the problems of color shift and uneven brightness in low grayscale display caused by fixed-color access of reference voltage signal lines to sub-pixels, thereby further improving the performance of the display panel.

[0067] Figure 6b This is a schematic flowchart illustrating a method for manufacturing a display panel according to another embodiment of this application. Figure 6b As shown, the method for determining the predetermined random access scheme includes the following steps.

[0068] Step 600: Obtain the simulation diagram.

[0069] The simulation diagram includes a predetermined sub-pixel array and reference voltage signal lines arranged on the predetermined sub-pixel array. The reference voltage signal lines include multiple transverse traces extending along a first direction and spaced apart along a second direction.

[0070] Step 601: Determine the target base block corresponding to each sub-pixel in the predetermined sub-pixel array according to a predetermined strategy.

[0071] The target base block is selected from any of the preset base blocks corresponding to the color of the pre-stored sub-pixel. The criteria for dividing the preset base blocks include whether the reference voltage signal line contains longitudinal traces that extend along the second direction and are spaced apart along the first direction, and the signal type of the reference voltage signal line.

[0072] Specifically, for a dual-reference voltage mesh structure composed of a first reference voltage signal line and a second reference voltage signal line, while maintaining the horizontal routing of the original reference voltage signal to the sub-pixel, the type of the preset base block can include the following four types: the first type has no vertical routing in the preset base block; the second type includes the first vertical routing of the first reference voltage signal line in the preset base block; the third type includes the second vertical routing of the second reference voltage signal line in the preset base block; and the fourth type includes the first vertical routing of the first reference voltage signal line and the second vertical routing of the second reference voltage signal line in the preset base block. For a single-reference voltage mesh structure, while maintaining the horizontal routing of the original reference voltage signal to the sub-pixel, the type of the preset base block can include the following two types: the first type has no vertical routing; and the second type includes vertical routing.

[0073] Step 602: Arrange the target base block at the corresponding sub-pixel to obtain the wiring diagram of the reference voltage signal line.

[0074] The display panel fabrication method provided in this application embodiment determines the target base block corresponding to each sub-pixel in the simulation diagram according to a predetermined strategy; the target base block is arranged at the corresponding sub-pixel to obtain the wiring diagram of the reference voltage signal line, thereby realizing the randomization of the access of the reference voltage signal line within the sub-pixel. This avoids the problem of regular distribution of storage capacitors or display panels during initialization caused by the fixed access scheme of sub-pixels in the prior art (e.g., strong R brightness leads to low grayscale pinkish mura; strong G / B color leads to low grayscale greenish / cyanish mura, etc.), thereby aggravating the problems of low grayscale display color shift and low grayscale mura.

[0075] Figure 7 This is a schematic flowchart illustrating a method for fabricating a display panel according to another embodiment of this application. Figure 7 As shown, the target base block corresponding to each sub-pixel in the simulation diagram is determined according to a predetermined strategy (step 601), including the following steps.

[0076] Step 700: Generate a predetermined number of random numbers, the number of which depends on the number of sub-pixels in the simulation image.

[0077] Step 701: A predetermined number of random numbers are sequentially assigned to each sub-pixel in the simulation image.

[0078] For example, generate M*N random numbers and assign them to the corresponding M*N sub-pixels in order, where M and N are both positive integers.

[0079] Step 702: Establish a correspondence between multiple random numbers and preset base blocks according to predetermined rules.

[0080] Step 703: For each sub-pixel, select a base block that matches the random number corresponding to the sub-pixel as the target base block.

[0081] The display panel manufacturing method provided in this application generates a predetermined number of random numbers and sequentially assigns these random numbers to each sub-pixel in the simulation diagram; establishes a correspondence between multiple random numbers and preset base blocks according to predetermined rules; and selects a base block that matches the random number corresponding to each sub-pixel as the target base block. This achieves the goal of determining the target base block corresponding to each sub-pixel in the simulation diagram, providing a prerequisite for the subsequent random access of reference voltage signal lines to sub-pixels.

[0082] Figure 8 This is a schematic flowchart illustrating a method for fabricating a display panel according to another embodiment of this application. Figure 8 As shown, the correspondence between multiple random numbers and preset base blocks is established according to predetermined rules (step 702), including the following steps.

[0083] Step 801: Divide the numerical range containing multiple random numbers into multiple sub-ranges.

[0084] Step 802: Match the multiple sub-intervals with the preset base blocks one by one.

[0085] For a dual-reference voltage mesh structure, multiple random numbers can be divided into four intervals, each interval matching a corresponding preset base block. The four intervals can be set as follows: MIN~(Max-MIN) / 4; (Max-MIN) / 4~(Max-MIN)*2 / 4; (Max-MIN)*2 / 4~(Max-MIN)*3 / 4; (Max-MIN)*3 / 4–MAX.

[0086] For a single-reference voltage mesh structure, multiple random numbers can be divided into two intervals, each interval matching a preset base block. The two intervals can be set as: MIN to (Max-MIN) / 2; (Max-MIN) / 2 to MAX. Here, MAX is the maximum value of the random number, and MIN is the minimum value.

[0087] The method for manufacturing a display panel provided in this application divides the numerical range of multiple random numbers into multiple sub-ranges; and maps each sub-range to a preset base block, thereby achieving the purpose of establishing a correspondence between multiple random numbers and preset base blocks according to a predetermined rule. This ensures that the base blocks corresponding to sub-pixels are randomly generated, which is beneficial for realizing the irregular access of reference voltage signal lines to sub-pixel distribution and further solving the problems of color shift and uneven brightness in the display panel.

[0088] Figure 9The diagram shown is a structural schematic of a display device provided in an embodiment of this application. Figure 9 As shown, one embodiment of this application also provides a display device 9. It is understood that the display panel 1 can be applied to the display device 9, which can be, for example, any product or component with display functionality such as a mobile terminal, tablet computer, computer monitor, television, wearable device, or information kiosks. The display device 9 includes the display panel 1 as in any embodiment of this application, and its technical principles and effects are similar, so they will not be described again here.

[0089] The display device provided according to any embodiment of this application and the display panel provided in the embodiments of this application belong to the same inventive concept, and have corresponding film layer structures and beneficial effects. Details not described in detail in the embodiments of the display device can be found in the embodiments section of the display panel, and will not be repeated here.

[0090] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0091] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0092] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0093] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0094] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A display panel, characterized in that, The display panel has a display area, and the display panel includes: substrate; A metal wiring layer is located on one side of the substrate. The metal wiring layer includes a first reference voltage signal line and a second reference voltage signal line. The first reference voltage signal line and the second reference voltage signal line are respectively in a mesh structure. The first reference voltage signal line includes a plurality of first access holes, and the second reference voltage signal line includes a plurality of second access holes. A light-emitting device layer is located on the side of the metal wiring layer opposite to the substrate, and the light-emitting device layer includes sub-pixels of multiple colors; Wherein, the first reference voltage signal line is randomly electrically connected to the sub-pixels of the various colors through a plurality of first access holes, so that at least a portion of the first reference voltage signal lines are arranged in a non-periodic regular pattern in the display area; the second reference voltage signal line is randomly electrically connected to the sub-pixels of the various colors through a plurality of second access holes, so that at least a portion of the second reference voltage signal lines are arranged in a non-periodic regular pattern in the display area; the orthographic projection of the sub-pixels of the same color on the metal wiring layer respectively covers any one or a combination of the first access hole and the second access hole.

2. The display panel according to claim 1, characterized in that, The first reference voltage signal line includes multiple first vertical traces, which are connected to the sub-pixel through the first access hole.

3. The display panel according to claim 2, characterized in that, The sub-pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. Multiple first vertical traces are connected to the first sub-pixel, the second sub-pixel, and the third sub-pixel respectively through multiple first access holes.

4. The display panel according to claim 2, characterized in that, The first reference voltage signal line includes multiple first lateral traces, which extend along a first direction and are spaced apart along a second direction. Multiple first longitudinal traces extend along the second direction and are spaced apart along the first direction. The first access hole is provided at the intersection of the projections of the first lateral traces and the first longitudinal traces on the substrate, wherein the first direction and the second direction intersect.

5. The display panel according to claim 1, characterized in that, The second reference voltage signal line includes multiple second vertical traces, which are connected to the sub-pixel through the second access hole.

6. The display panel according to claim 1, characterized in that, The second reference voltage signal line includes multiple second horizontal traces and multiple second vertical traces. The multiple second horizontal traces extend along a first direction and are spaced apart along a second direction. The multiple second vertical traces extend along the second direction and are spaced apart along the first direction. A second access hole is provided at the intersection of the projections of the second horizontal traces and the second vertical traces on the substrate, wherein the first direction and the second direction intersect.

7. A method for manufacturing a display panel, characterized in that, include: Provide substrate; A metal wiring layer is formed on one side of the substrate, the metal wiring layer including reference voltage signal lines arranged in a mesh structure; A light-emitting device layer is formed on the side of the metal wiring layer away from the substrate. The light-emitting device layer includes sub-pixels of multiple colors, and the reference voltage signal lines are electrically connected to the sub-pixels of multiple colors according to a predetermined random access scheme, so that at least a portion of the reference voltage signal lines are arranged in a non-periodic regular pattern in the display area of ​​the display panel. The method for determining the predetermined random access scheme includes: Obtain a simulation image, the simulation image including a predetermined sub-pixel array and a reference voltage signal line laid on the predetermined sub-pixel array, the reference voltage signal line including a plurality of transverse traces extending along a first direction and spaced apart along a second direction; The target base block corresponding to each sub-pixel in the predetermined sub-pixel array is determined according to a predetermined strategy. The target base block is selected from any one of a variety of preset base blocks corresponding to the color of the sub-pixel. The division criteria of the preset base block include whether the reference voltage signal line contains longitudinal traces that extend along the second direction and are spaced apart along the first direction, and the signal type of the reference voltage signal line. The target base block is arranged at the corresponding sub-pixel to obtain the wiring diagram of the reference voltage signal line.

8. The method for manufacturing a display panel according to claim 7, characterized in that, The step of determining the target base block corresponding to each sub-pixel in the predetermined sub-pixel array according to a predetermined strategy includes: Generate a predetermined number of random numbers, the number of which depends on the number of sub-pixels in the simulation image; The predetermined number of random numbers are sequentially assigned to each sub-pixel in the simulation image; Establish a correspondence between multiple random numbers and the preset basic blocks according to predetermined rules; For each sub-pixel, a base block that matches the random number corresponding to the sub-pixel is selected as the target base block.

9. The method for manufacturing a display panel according to claim 8, characterized in that, The step of establishing a correspondence between multiple random numbers and the preset base block according to a predetermined rule includes: Divide the numerical interval containing the multiple random numbers into multiple sub-intervals; Each of the multiple sub-intervals is mapped to a preset basic block.

10. A display device, characterized in that, The display panel includes any one of claims 1 to 6.

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