Packet pointer management device, packet pointer management method, and chip

Abstract

The application provides a message pointer management device, a message pointer management method and a chip, which are applied to message transmission of multiple channels. The message includes multiple data blocks with equal bus width. The message pointer management device includes: a message pointer cache, configured with a storage space for each channel, used for storing message pointers and tail data block flags of the message; multiple channel state storage memories, corresponding to the multiple channels, storing read addresses and write addresses of the storage space of the corresponding channel; and a tail data information FIFO, used for storing error information flags of the message. The message pointer management device is configured to: when reading the message pointer, in response to the error information flag being 1, release the message pointer stored in the message pointer cache. The application adopts a method of caching all pointers of a single message of each channel, so that when the message pointer is recycled, it is not necessary to read the pointer storage memory recording the data cache address, and only the message pointer cache needs to be read to obtain all pointers of a message.

Description

Technical Field

[0001] This invention relates to the field of network communication technology, and in particular to a message pointer management device, a message pointer management method, and a chip. Background Technology

[0002] With the development of cutting-edge technologies such as 5G, artificial intelligence, virtual reality, and network switching, the core processing chips are becoming increasingly larger, and the amount of data they need to process is also growing exponentially. This data is typically divided into multiple channels, requiring large buffer memories for storage. To ensure fairness and flexibility in data storage across channels, the addresses of these buffer memories are often managed using linked lists. Taking network switching chips as an example, the data in each channel is called a packet.

[0003] The bus width for transmitting messages in the chip is fixed. Because message sizes vary, messages from each channel are stored sequentially in the data buffer as multiple data blocks of equal bus width. The storage addresses of all data blocks of a message in the data buffer form a linked list; each address is called a pointer, hereinafter referred to as a message pointer. Simultaneously, pointer memory is needed to store the link relationships between these pointers. For example... Figure 1 As shown, assume that the data blocks of a message are stored in addresses 0, 3, 5, 7, and 9 of the data buffer. The linking relationship of these addresses is 0 <- 3 <- 5 <- 9 <- 7. Here, 0 is the start pointer of the message, and 7 is the tail pointer. The above linking relationship is stored in the pointer memory as follows: address 0 has a value of 3, address 3 has a value of 5, ..., and the value stored at the tail address 7 can be ignored. When a message data block is stored in the data buffer, the message pointer memory is written to establish a linked list; when reading a message from the data buffer, the message pointer memory is read to obtain the linked list pointer.

[0004] If an error occurs before the last data in a message arrives, the message must be discarded in the switching chip, and subsequent data will not be buffered. All pointers to this message's data block must be reclaimed. How to reasonably reclaim these pointers without affecting message read / write speed is a problem that must be solved in the design of this type of chip. Furthermore, the pointer reclamation design method directly affects the chip's timing and area.

[0005] Because the flag message linked list is characterized by its head pointer, existing technologies typically use a method of reading the pointer memory from the head pointer to the tail pointer to release all pointers and achieve pointer reclamation. This method requires one read interface of the pointer memory, and with the normal message reading operation, the message pointer memory needs to be designed with two read ports. Since pointer memory, like data buffer, is very deep, designing two read ports doubles the area compared to a read-write memory, which is a significant waste of resources for chip implementation. If the pointer memory is designed for a read-write configuration, both retrieving the next pointer linked to the current pointer from the data buffer and retrieving the next pointer after the currently released pointer require reading operations from the pointer memory. A single read port cannot support two read operations simultaneously. This results in insufficient read bandwidth for the pointer memory, ultimately affecting the message processing speed.

[0006] Therefore, it is necessary to improve the existing message pointer management methods and devices. Summary of the Invention

[0007] In view of the above-mentioned technical problems existing in the prior art, this application provides a message pointer management device for transmitting multiple messages across multiple channels. Each message is divided into multiple data blocks of equal bus width and stored in a data buffer. The storage addresses of each data block in the data buffer form a linked list, and each storage address is called a message pointer. The device includes: a message pointer buffer, which is configured with a storage space for each channel to store the message pointer and the tail data block flag of the message; multiple channel status memories, which are configured corresponding to the multiple channels and store the read address and write address of the storage space for the corresponding channel; and a tail data information FIFO for storing the error information flag of the message. The message pointer management device is configured to: when reading the message pointer, release the message pointer stored in the message pointer buffer in response to the error information flag being 1.

[0008] Optionally, it further includes: a plurality of channel configuration memories, configured corresponding to the plurality of channels, storing the start address and end address of the storage space of the message pointer of the corresponding channel, so as to define the storage space of each of the channels for the message pointer cache.

[0009] Optionally, the number of addresses in the storage space of each channel is equal to the number of data blocks in the message with the most data blocks among the plurality of messages.

[0010] Optionally, it further includes: a channel linked list memory, the number of which is equal to the number of entries in the message pointer cache, which stores a linked list composed of the addresses of the message pointer caches of each channel; the channel state memory stores the head pointer and tail pointer of each channel linked list in the channel linked list memory, and when reading the message pointer, the storage address of the next message pointer of the channel in the message pointer cache can be obtained by reading the channel linked list memory.

[0011] To achieve the aforementioned objectives, this application also provides a message pointer management method, which uses the message pointer management device described above to reclaim message pointers, including:

[0012] Message pointer storage steps: Store the message pointer, read the channel state memory using the channel number as the address, obtain the write address of the channel, use the obtained write address of the channel as the address, write the message pointer as data into the message pointer buffer, increment the write address by 1, keep the read address unchanged, use the channel number as the address, and write the read and write addresses as data into the channel state memory.

[0013] Optionally, the message pointer storage step further includes: when storing the last data block of the message or the data block in which the message encountered an error, when writing to the message pointer buffer, setting the tail data block flag to 1, and simultaneously pushing the channel number and the error information flag into the tail data information FIFO; if no error occurred while storing the message pointer, the error information flag is 0; otherwise, the error information flag is 1.

[0014] Optionally, the process includes a message pointer retrieval step: when reading the data block of the message, if the tail data information FIFO is not empty, read the channel number at the top of the data block, use the channel number as the address to read the channel state memory, obtain the read address of the channel corresponding to the channel number, use the obtained read address as the address to read the message pointer buffer, obtain the message pointer, and if the error information flag obtained from the tail data information FIFO is 1, then release the obtained message pointer.

[0015] Optionally, the message pointer recycling step further includes: if the error information flag is not 1, incrementing the read address by 1, keeping the write address unchanged, and writing the read and write addresses as data into the channel status memory, using the channel number as the address.

[0016] Optionally, the message reading step further includes: repeatedly performing the operations of reading the message pointer buffer and accumulating the read address in the message reading step until the tail data block flag obtained from the message pointer buffer is 1, then stopping the reading of the message pointer buffer and popping the data at the top of the tail data information FIFO.

[0017] To achieve the above-mentioned objectives, this application provides a message pointer management method, which uses the message pointer management device described above to reclaim message pointers, including the steps of: storing the message pointer in a message pointer buffer; storing the message error information flag in the tail data information FIFO; and when reading the message pointer, releasing the message pointer stored in the message pointer buffer in response to the error information flag being 1.

[0018] To achieve the above-mentioned objectives, this application also provides a chip that uses the message pointer management device or message pointer management method described above to reclaim message pointers.

[0019] This application adopts a method of caching all pointers of a single message in each channel. Therefore, when recycling message pointers, it is not necessary to read the pointer memory of the record data cache address. It is only necessary to read the message pointer cache to obtain all pointers of a message. This simplifies the pointer recycling logic without affecting the pointer recycling speed.

[0020] Since each channel begins reading the first pointer of a message based on the read address stored in the channel state memory when storing the last data block, thus freeing up space in the message pointer buffer, as long as the depth of the tail data information FIFO is designed reasonably (the depth of the tail data information FIFO is related to the specific chip architecture and is not within the scope of this invention, so it will not be described here), the number of addresses occupied by the storage space for each channel only needs to be equal to the number of data blocks in the longest message. Therefore, the depth of the message pointer buffer can be much smaller than that of the pointer memory. This method saves chip area and does not affect the chip's message read / write bandwidth, so it does not affect the message processing speed. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a message data caching method;

[0022] Figure 2 This is a schematic diagram of the message pointer management device provided in Embodiment 1 of this application;

[0023] Figure 3 This is a schematic diagram of the message pointer management device provided in Embodiment 2 of this application;

[0024] Figure 4 This is a flowchart illustrating the message pointer management method provided in Embodiment 1 of this application. Detailed Implementation

[0025] In the following, exemplary embodiments will be described in detail with reference to the accompanying drawings. However, this application is not limited to the embodiments described below, but includes various changes, substitutions, and modifications within the technical scope of this disclosure. The terms "first," "second," etc., can be used to interpret various elements, and the number of elements is not limited by such terms. These terms are only used to distinguish one element from another. Therefore, an element referred to as a first element in one embodiment may be referred to as a second element in another embodiment. Unless the context requires otherwise, the singular form does not exclude the plural form. The following specific embodiments illustrate the implementation of this application, and those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.

[0026] This embodiment provides a message pointer management device and method applicable to multi-channel message pointer recycling, which not only saves chip area but also does not affect the chip's message read / write bandwidth, and therefore does not affect the message processing speed.

[0027] Example 1

[0028] The message pointer management device provided in this embodiment is used to reclaim multiple message pointers across multiple channels. A message includes multiple data blocks of equal bus width, and the message pointer is the address of the data block in the data buffer. For example... Figure 2 As shown, taking a total of x+1 channels as an example, the message pointer management device includes: a message pointer buffer 10, which can allocate a storage space for each channel, i.e., a total of x+1 storage spaces, for storing message pointers and message tail data block flags; multiple channel status memories 20, configured corresponding to multiple channels, each channel device memory 20 storing the read address and write address of the corresponding channel's storage space; multiple channel configuration memories 30, configured corresponding to multiple channels, each channel configuration memory 30 storing the start address and end address of the corresponding channel's storage space to define the storage space for each channel; and a tail data information FIFO, used to store message error information flags and channel numbers for each channel in the message pointer buffer 10.

[0029] Optionally, the number of addresses in the storage space of each channel is equal to the number of data blocks in the message with the most data blocks among multiple messages.

[0030] The message pointer management method of this message pointer management device is described below.

[0031] The message pointer storage method is as follows:

[0032] Step 1: Store the pointers of each data block message. Using the channel number as the address, read the channel state memory 20 to obtain the write address of the channel. Then store the message pointer: using the obtained write address of the channel as the address, write the message pointer as data into the message pointer buffer 10. Increment the write address by 1, keep the read address unchanged, and using the channel number as the address, write the read and write addresses as data into the channel state memory 20.

[0033] Step 2: When storing the last data block of a message, or the data block where an error occurred, in addition to performing the above operations for storing message data blocks, when writing to the message pointer buffer, the tail data block flag is set to 1, and the channel number and error information flag are pushed into the tail data information FIFO. If no error occurred while storing the message, the error information flag is 0; otherwise, the error information flag is 1, thus realizing the storage of the message pointer.

[0034] The method for reclaiming message pointers is as follows:

[0035] Step 3: When the tail data information FIFO is not empty, read the channel number at its top. Using this channel number as the address, read the channel status memory 20 to obtain the read address of the channel corresponding to that channel number. Using the obtained read address as the address, read the message pointer buffer to obtain the message pointer. If the error information flag obtained from the tail data information FIFO is 1, release the obtained message pointer; otherwise, since no error has occurred in the message pointer, the message pointer can only be released after the message is read, and cannot be released in advance, so no operation is performed on the obtained message pointer. Increment the read address by 1, keep the write address unchanged, and use the channel number as the address, write the read and write addresses as data into the channel status memory 20.

[0036] Step 4: If the error message flag is not 1, repeat the operation of reading the message pointer buffer and accumulating the read address in step 3 until the tail data block flag obtained from the message pointer buffer is 1. Then stop reading the message pointer buffer 10 and pop the data at the top of the tail data information FIFO.

[0037] Repeat steps 3 and 4 until the tail data information FIFO is empty, so as to reclaim the message pointer.

[0038] Optionally, such as Figure 4 As shown, this application provides a message pointer management method, which uses the message pointer management device described above to reclaim message pointers, including the following steps:

[0039] Store the message pointer in message pointer buffer 10;

[0040] Store the error message flag of the message in the tail data information FIFO;

[0041] When reading the message pointer, in response to the error message flag being 1, the message pointer stored in the message pointer buffer 10 is released.

[0042] It should be noted that the "message pointer" mentioned here refers to all pointers to a single message.

[0043] This application employs a cache for all pointers to a single message in each channel. When reclaiming message pointers, it is not necessary to read the pointer memory that records the data cache address; only the message pointer cache 10 needs to be read to obtain all pointers for a message. Since each channel begins reading the first pointer of a message based on the read address stored in the channel state memory 20 when storing the last data block, thus releasing the space of the message pointer cache, as long as the depth design of the tail data information FIFO is reasonable (the depth of the tail data information FIFO is related to the specific chip architecture and is not within the scope of this invention, so it will not be described here), the number of addresses occupied by the storage space for each channel only needs to be equal to the number of data blocks of the longest message. Therefore, the depth of the message pointer cache can be much smaller than that of the pointer memory. This method saves chip area and does not affect the chip's message read / write bandwidth, so it does not affect the message processing speed.

[0044] Example 2

[0045] The difference between Embodiment 2 and Embodiment 1 is that, instead of configuring a channel configuration memory 30, a channel linked list memory 40 is used, with the number of entries equal to that of the message pointer buffer 10. The channel state memory 20 stores the head and tail pointers of each channel linked list. When reading a message pointer, the storage address of the next message pointer in the message pointer buffer for that channel needs to be obtained from the channel linked list memory 40.

[0046] This configuration uses a linked list to manage the storage space allocated to each channel in the message pointer buffer 10, eliminating the need for fixed storage space and making more efficient use of the space in the message pointer buffer 10.

[0047] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A message pointer management device, applied to the transmission of multiple messages across multiple channels, wherein each message is divided into multiple data blocks of equal bus width and stored in a data buffer, the storage addresses of each data block in the data buffer form a linked list, and each storage address is called a message pointer, characterized in that, include: A message pointer buffer is configured with a storage space for each channel to store the message pointer and the tail data block flag of the message; wherein the number of addresses of the storage space is equal to the number of data blocks of the message with the most data blocks among the multiple messages; Multiple channel status memories, corresponding to the multiple channels, store the read address and write address of the corresponding channel's storage space; and Tail data information FIFO is used to store error information flags of the message; The message pointer management device is configured to: when reading a message pointer, read the corresponding channel status memory using the channel number as the address to obtain the channel read address, read the message pointer from the message pointer buffer according to the read address, and release the message pointer stored in the message pointer buffer when the error information flag is 1 obtained from the tail data information FIFO.

2. The message pointer management device as described in claim 1, characterized in that, Also includes: Multiple channel configuration memories are configured to correspond to the multiple channels, storing the start and end addresses of the storage space for the corresponding channel, so as to define the storage space of each channel for the message pointer cache.

3. The message pointer management device as described in claim 1, characterized in that, Also includes: The channel linked list memory has the same number of entries as the message pointer cache and stores a linked list composed of the addresses of each channel message pointer cache. The channel state memory stores the head and tail pointers of a linked list composed of the cached addresses of the message pointers of each channel in the channel linked list memory. When reading the message pointer, the storage address of the next message pointer of the channel in the message pointer cache can be obtained by reading the channel linked list memory.

4. A message pointer management method, comprising using the message pointer management device according to any one of claims 1-3 to reclaim message pointers, characterized in that, include: Message pointer storage steps: Store the message pointer, read the channel state memory using the channel number as the address, obtain the write address of the channel, use the obtained write address of the channel as the address, write the message pointer as data into the message pointer buffer, increment the write address by 1, keep the read address unchanged, use the channel number as the address, and write the read and write addresses as data into the channel state memory.

5. The message pointer management method as described in claim 4, characterized in that, The message pointer storage step further includes: when storing the last data block of the message or storing the data block of the message where an error occurred, when writing the message pointer buffer, setting the tail data block flag of the data to 1, and simultaneously pushing the channel number and the error information flag into the tail data information FIFO. If no error occurred when storing the message pointer, the error information flag is 0; otherwise, the error information flag is 1.

6. The message pointer management method as described in claim 5, characterized in that, include: Message pointer retrieval steps: When the tail data information FIFO is not empty, read the channel number at the top of it, use the channel number as the address to read the channel status memory, obtain the read address of the channel corresponding to the channel number, use the obtained read address as the address to read the message pointer buffer, obtain the message pointer, and if the error information flag obtained from the tail data information FIFO is 1, then release the obtained message pointer.

7. The message pointer management method as described in claim 6, characterized in that, The message pointer recovery step also includes: If the error message flag is not 1, increment the read address by 1, keep the write address unchanged, use the channel number as the address, and write the read and write addresses as data into the channel status memory.

8. A message pointer management method, comprising using the message pointer management device according to any one of claims 1-3 to reclaim message pointers, characterized in that, Including the following steps: Store the message pointer in the message pointer buffer; Store the error message flag of the message in the tail data information FIFO; When reading the message pointer, in response to the error information flag being 1, the message pointer stored in the message pointer buffer is released.

9. A chip, characterized in that, The message pointer management device according to any one of claims 1-3 or the message pointer management method according to any one of claims 4-7 can be used to recover the message pointer, or the message pointer management method according to claim 8 can be used to recover the message pointer.

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