Method, device, processor and computer device for processing multiple-input floating-point numbers

Abstract

The application relates to a multiple-input floating-point number processing method and device, computer equipment and a storage medium. The method comprises the following steps: obtaining multiple floating-point numbers to be processed corresponding to a target task, and extracting an exponent value of an exponent part and a mantissa value of a mantissa part in each floating-point number; sorting the multiple floating-point numbers according to the sizes of the exponent values of the floating-point numbers, and respectively assigning a corresponding shifter to each floating-point number from multiple shifters with different preset bit numbers based on a sorting result; for each floating-point number, the mantissa value of the corresponding floating-point number is subjected to a shift processing through the shifter assigned to the floating-point number, so as to obtain a shift result; and a floating-point number processing result corresponding to the target task is determined based on the shift results. The method can significantly reduce the hardware resource overhead.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a method, apparatus, processor, computer device, and storage medium for processing multi-input floating-point numbers. Background Technology

[0002] With the development of computer technology, AI (Artificial Intelligence) technology is also advancing rapidly. In the field of AI technology, AI algorithms are typically implemented through AI processing. In an AI processor, the matrix operation unit is the core data processing device, and its performance and computing power directly determine the processor's performance metrics. Within the matrix operation unit, the multi-input floating-point operation unit is crucial in determining performance.

[0003] In traditional multi-input floating-point arithmetic, achieving zero intermediate precision requires a very wide data bit width after shifting. Therefore, multiple high-bit shifters are typically needed to ensure lossless intermediate precision. However, this excessively large shift range results in significant hardware overhead, requiring the processor to consume more hardware resources. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, processor, computer device, and storage medium for multi-input floating-point number processing that can significantly reduce hardware resource overhead, in order to address the aforementioned technical problems.

[0005] Firstly, this application provides a method for processing multi-input floating-point numbers. The method includes:

[0006] Obtain multiple floating-point numbers to be processed corresponding to the target task, and extract the exponent value of the exponent part and the mantissa value of the mantissa part of each floating-point number respectively.

[0007] The multiple floating-point numbers are sorted according to the magnitude of their exponent values, and a corresponding shifter is assigned to each floating-point number from multiple shifters with different preset bit lengths based on the sorting results.

[0008] For each floating-point number, the mantissa of the corresponding floating-point number is shifted using a shifter allocated to that floating-point number to obtain the shift result;

[0009] The floating-point processing result corresponding to the target task is determined based on each of the shift results.

[0010] Secondly, this application also provides a multi-input floating-point number processing apparatus. The apparatus includes:

[0011] The acquisition module is used to acquire multiple floating-point numbers to be processed corresponding to the target task, and extract the exponent value of the exponent part and the mantissa value of the mantissa part of each floating-point number respectively.

[0012] The allocation module is used to sort the multiple floating-point numbers according to the magnitude of the exponent value of each floating-point number, and allocate a corresponding shifter for each floating-point number from multiple shifters with different preset bit lengths based on the sorting result.

[0013] The shift module is used to shift the mantissa of each floating-point number by means of a shifter corresponding to the floating-point number, so as to obtain the shift result.

[0014] The determination module is used to determine the floating-point processing result corresponding to the target task based on each of the shift results.

[0015] In one embodiment, the different preset bit numbers of the plurality of shifters are within a first preset range, and the preset bit numbers of each shifter are uniformly distributed within the first preset range.

[0016] In one embodiment, the number of the plurality of shifters is the same as the number of the plurality of floating-point numbers; the allocation module is further configured to determine the sorting number corresponding to each floating-point number in the sorting result; determine the preset number of bits corresponding to each sorting number, and allocate the plurality of shifters to the floating-point numbers specified by the sorting number corresponding to the preset number of bits, according to the preset number of bits they have.

[0017] In one embodiment, the shift module is further configured to determine the number of shift bits corresponding to the mantissa of each floating-point number based on the difference between the exponent values ​​of each floating-point number and the maximum exponent value, wherein the maximum exponent value is the maximum value among the exponent values ​​of multiple floating-point numbers; for each floating-point number, the corresponding mantissa is shifted based on the number of shift bits corresponding to the mantissa of the corresponding floating-point number by a shifter allocated to the floating-point number to obtain the shift result.

[0018] In one embodiment, the shift module is further configured to, for each floating-point number, determine whether the number of shift bits corresponding to the mantissa of the floating-point number is within the shift range corresponding to the preset number of bits of the shifter allocated to the floating-point number; if the number of shift bits is within the shift range, then, through the shifter allocated to the floating-point number, each mantissa member constituting the mantissa in the floating-point number is shifted in the same shift direction within the corresponding shift range; wherein, the shift direction includes left shift or right shift; if the number of shift bits is outside the shift range, then, through the shifter allocated to the floating-point number, each mantissa member constituting the mantissa in the floating-point number is shifted in the same shift direction by the preset number of bits; the mantissa obtained after shifting each floating-point number is taken as its respective shift result.

[0019] In one embodiment, the determining module further includes a compression unit, which is used to divide the shifters of different preset bit lengths into multiple domain segments based on a first preset range, and determine compressors corresponding to the multiple domain segments respectively, wherein different compressors have different preset compression ratios; for each domain segment, determine multiple intra-domain shift results within the corresponding domain segment, wherein a single intra-domain shift result is the intra-domain portion of the shift result corresponding to a single floating-point number; through each compressor, perform segmented compression processing on the multiple intra-domain shift results within the domain segment corresponding to the corresponding compressor to obtain multiple segmented compression results; based on the multiple segmented compression results, determine the floating-point number processing result corresponding to the target task.

[0020] In one embodiment, the values ​​of the different preset compression ratios of the plurality of compressors are within a second preset range, and the values ​​of the preset compression ratios of each compressor are uniformly distributed within the second preset range.

[0021] In one embodiment, the compression unit is further configured to use multiple intra-domain shift results within their respective domain segments as inputs to each compressor; each compressor performs segmented compression processing on its respective inputs according to its corresponding preset compression ratio to obtain the local result and the carry result, wherein the local result and the carry result constitute the segmented compression result corresponding to the corresponding segmenter.

[0022] In one embodiment, the determining module further includes an addition unit, which is used to select a first domain segment (which has not undergone compression and corresponds to only a single intra-domain shift result) as the selection result of the first domain segment; for a second domain segment (which has not undergone compression and corresponds to more than one intra-domain shift result) based on the more than one intra-domain shift result within the second domain segment, generate a true value result and a pseudo-value result for the second domain segment; for a third domain segment (which has undergone compression) based on the segmented compression result corresponding to each third domain segment, generate a true value result and a pseudo-value result for the corresponding third domain segment; determine the selection result corresponding to each domain segment sequentially from the lowest bit domain segment according to the bit height of the domain segment until the selection result of the highest bit domain segment is obtained, wherein the selection result of the other domain segments besides the first domain segment is one of the true value result and the pseudo-value result of the corresponding domain segment; and determine the floating-point processing result corresponding to the target task based on the selection results of each domain segment.

[0023] In one embodiment, the determining module further includes a splicing unit, which splices the selection results of each domain segment in descending order of bit segment height to obtain a floating-point processing result corresponding to the target task.

[0024] In one embodiment, the apparatus further includes a post-processing module for normalizing the floating-point number processing result so that the floating-point number processing result conforms to a preset floating-point number standard.

[0025] In one embodiment, the post-processing module is further configured to determine a first symbol identifier and a second symbol identifier in the floating-point number processing result; if the first symbol identifier is the same as the second symbol identifier, then the mantissa in the floating-point number processing result is shifted according to a first shift direction; if the first symbol identifier is different from the second symbol identifier, then the mantissa in the floating-point number processing result is shifted according to a second shift direction; wherein the second shift direction is opposite to the first shift direction.

[0026] In one embodiment, the target task is a subtask in a neural network processing task. The neural network task includes at least one of a convolution processing task and a similarity processing task. The device further includes a task module, which is used to execute subsequent subtasks in the neural network processing task based on the floating-point number processing result to obtain the neural network processing result.

[0027] Thirdly, this application also provides a processor. The processor includes:

[0028] At least one shifter with a different preset number of bits, each shifter being assigned to shift the mantissa of one of a plurality of floating-point numbers to be processed; wherein the shifter assigned to each floating-point number is determined by sorting the exponents of the exponents of each floating-point number.

[0029] The logic processing unit is used to perform logical processing on the multiple shift results obtained by each of the shifters to obtain floating-point processing results.

[0030] Fourthly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the following steps:

[0031] Obtain multiple floating-point numbers to be processed corresponding to the target task, and extract the exponent value of the exponent part and the mantissa value of the mantissa part of each floating-point number respectively.

[0032] The multiple floating-point numbers are sorted according to the magnitude of their exponent values, and a corresponding shifter is assigned to each floating-point number from multiple shifters with different preset bit lengths based on the sorting results.

[0033] For each floating-point number, the mantissa of the corresponding floating-point number is shifted using a shifter allocated to that floating-point number to obtain the shift result;

[0034] The floating-point processing result corresponding to the target task is determined based on each of the shift results.

[0035] Fifthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the following steps:

[0036] Obtain multiple floating-point numbers to be processed corresponding to the target task, and extract the exponent value of the exponent part and the mantissa value of the mantissa part of each floating-point number respectively.

[0037] The multiple floating-point numbers are sorted according to the magnitude of their exponent values, and a corresponding shifter is assigned to each floating-point number from multiple shifters with different preset bit lengths based on the sorting results.

[0038] For each floating-point number, the mantissa of the corresponding floating-point number is shifted using a shifter allocated to that floating-point number to obtain the shift result;

[0039] The floating-point processing result corresponding to the target task is determined based on each of the shift results.

[0040] Sixthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, performs the following steps:

[0041] Obtain multiple floating-point numbers to be processed corresponding to the target task, and extract the exponent value of the exponent part and the mantissa value of the mantissa part of each floating-point number respectively.

[0042] The multiple floating-point numbers are sorted according to the magnitude of their exponent values, and a corresponding shifter is assigned to each floating-point number from multiple shifters with different preset bit lengths based on the sorting results.

[0043] For each floating-point number, the mantissa of the corresponding floating-point number is shifted using a shifter allocated to that floating-point number to obtain the shift result;

[0044] The floating-point processing result corresponding to the target task is determined based on each of the shift results.

[0045] The aforementioned multi-input floating-point number processing method, apparatus, processor, computer device, and storage medium pre-design multiple shifters with different preset bit widths. When processing multiple floating-point numbers, the numbers can be sorted according to their exponent values. Based on the sorting result, a corresponding shifter is allocated to each floating-point number from the multiple shifters with different preset bit widths. The allocated shifters are then used to perform shifting operations on the multiple floating-point numbers, and the floating-point number processing result corresponding to the target task is obtained based on the shifting results. In this way, the concept of effective shifting is introduced, effectively shifting the last digits in the sorted sequence while the shifting range of the first digits is small (or even unnecessary). While ensuring no intermediate precision loss, the area overhead of the shifters is greatly reduced, thereby saving processor hardware overhead. Under the premise of limited hardware resources, it can well balance the efficiency and accuracy of floating-point number processing. Attached Figure Description

[0046] Figure 1 This is a flowchart illustrating a multi-input floating-point number processing method in one embodiment;

[0047] Figure 2 This is a schematic diagram of the format of a floating-point number in one embodiment;

[0048] Figure 3 This is a flowchart illustrating the steps of allocating a shifter in one embodiment;

[0049] Figure 4 This is a flowchart illustrating the shifting process in one embodiment;

[0050] Figure 5This is a flowchart illustrating the shifting process in another embodiment;

[0051] Figure 6 This is a flowchart illustrating the steps of determining the floating-point processing result corresponding to the target task based on each shift result in one embodiment.

[0052] Figure 7 This is a flowchart illustrating the steps of segmented compression processing in one embodiment;

[0053] Figure 8 This is a schematic diagram illustrating the principle of segmented compression processing in one embodiment;

[0054] Figure 9 This is a flowchart illustrating how, in one embodiment, the floating-point processing result corresponding to the target task is determined based on multiple segmented compression results.

[0055] Figure 10 This is a flowchart illustrating the steps of the selector outputting the selection result in one embodiment;

[0056] Figure 11 This is a flowchart illustrating the steps for normalizing floating-point number processing results in one embodiment.

[0057] Figure 12 This is a schematic diagram of a conventional multi-floating-point addition calculation process in one embodiment;

[0058] Figure 13 This is a schematic diagram illustrating the data bit width in one embodiment;

[0059] Figure 14 This is a schematic diagram of the process of applying the present application to multi-floating-point addition calculation in one embodiment;

[0060] Figure 15 This is a structural block diagram of a multi-input floating-point processing device in one embodiment;

[0061] Figure 16 This is a block diagram of the processor in one embodiment;

[0062] Figure 17 This is a block diagram of the logic processing unit in one embodiment;

[0063] Figure 18 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0065] Artificial Intelligence (AI) is the theory, methods, technology, and application systems that use digital computers or computers-controlled machines to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. AI technology is a comprehensive discipline involving a wide range of fields, encompassing both hardware and software technologies. Fundamental AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interactive systems, and mechatronics.

[0066] The realization of fundamental artificial intelligence technologies relies on the support of underlying technologies. The development of AI processors is currently a key focus and a crucial factor in improving the performance of devices and software applications using AI technology. Within AI processors, the matrix operation unit is key to effectively increasing the processor's clock speed. And within the matrix operation unit, the efficiency of floating-point operations determines the computing power of the AI ​​processor.

[0067] In view of this, this application provides a multi-input floating-point number processing method, apparatus, processor, computer device, storage medium, and computer program product. By optimizing the floating-point number operation method and corresponding processing logic, it can not only efficiently process multiple floating-point number operations, but also effectively reduce the area of ​​the AI ​​processor by reducing the area of ​​the shifter, reduce the critical path in timing, and increase the clock frequency of the AI ​​processor, so that a single chip using the AI ​​processor can provide higher computing power.

[0068] In some embodiments, such as Figure 1 As shown, a multi-input floating-point number processing method is provided. This embodiment illustrates the application of this method to a computer device. It is understood that the computer device can be a terminal or a server. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. The terminal can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can be smart speakers, smart TVs, smart air conditioners, and smart vehicle devices. Portable wearable devices can be smartwatches, smart bracelets, and head-mounted devices. Exemplarily, the multi-input floating-point number processing method provided in this embodiment can be applied to data processing devices in a computer device, such as processors and sensors.

[0069] In this embodiment, the method includes the following steps:

[0070] Step S102: Obtain multiple floating-point numbers to be processed corresponding to the target task, and extract the exponent value of the exponent part and the mantissa value of the mantissa part of each floating-point number respectively.

[0071] In this context, a target task refers to the computational processing task performed by a computer device to achieve a specific goal. This computational processing includes, but is not limited to, mathematical operations such as addition, subtraction, multiplication, and division. For example, a target task can be a computational processing task during the training of a neural network, including but not limited to convolution summation tasks and similarity calculation tasks. Alternatively, a target task can also be a cloud computing or distributed computing task, involving computation on multiple datasets.

[0072] Floating-point numbers are numerical representations of numbers belonging to a specific subset of rational numbers, used in computers to approximate any real number. Taking the currently commonly used floating-point number format as an example, the format of floating-point numbers generally follows the IEEE binary floating-point arithmetic standard (ANSI / IEEE Std 754-1985, commonly referred to as IEEE 754) established by the Microprocessor Standards Committee (MSC).

[0073] The IEEE 754 standard specifies the concrete standard for storing decimal floating-point numbers in binary form in computer memory and defines four ways to represent floating-point values: single-precision floating-point numbers, double-precision floating-point numbers, extended single-precision floating-point numbers, and extended double-precision floating-point numbers.

[0074] like Figure 2 As shown, IEEE 754 represents floating-point numbers as three parts: the sign part, the exponent part, and the mantissa part. The sign part (S) occupies the highest bit and indicates whether the floating-point number is positive or negative; "0" represents a positive number, and "1" represents a negative number. The exponent value E (often called the exponent code) in the exponent part is represented by offset code (also known as increase code or bias code). For a 32-bit single-precision floating-point number, the range of the exponent value E is 8 bits, representing 0 to 255 exponent values. The exponent value indicates the position of the decimal point. The mantissa M of the floating-point number is represented by its original code. Again, using a 32-bit single-precision floating-point number as an example, the range of the mantissa M is 24 bits, determining the precision of the real numbers that the floating-point number can represent. It should be noted that since the highest bit of the original code must be a valid bit (that is, it must be 1), the computer memory usually omits (or hides) the highest bit of the mantissa to save storage space. Thus, the 23-bit mantissa in the figure can represent 24 bits of information.

[0075] For the sake of simplicity and ease of understanding, the examples listed in the following embodiments all conform to the IEEE 754 standard, and will not be repeated hereafter.

[0076] In some embodiments, the multiple floating-point numbers to be processed are stored in a memory, which may be an internal memory provided in a computer device or an external memory that is independent of the computer device but communicatively connected to it.

[0077] Specifically, the computer device retrieves at least two floating-point numbers to be processed from memory and, according to the format followed by the floating-point numbers, extracts the exponent value of the exponent part and the mantissa of the bit part of each floating-point number. The exponent value is used for subsequent sorting of the floating-point numbers to determine the size of the shifter allocated to each floating-point number; the mantissa is the part used for the actual shifting process.

[0078] Taking a 32-bit single-precision floating-point number as an example, the computer extracts the value corresponding to the 31st bit (the most significant bit) as the sign bit, the values ​​corresponding to bits 30 to 23 as the exponent value, and the values ​​corresponding to bits 22 to 0 (the least significant bit) as the mantissa value. As mentioned earlier, the computer uses a representation method that implicitly includes a 1 in the most significant bit of the mantissa to represent the mantissa value; therefore, the number of bits extracted by the computer is bits 22 to 0.

[0079] Step S104: Sort multiple floating-point numbers according to the magnitude of their exponent values, and assign a corresponding shifter to each floating-point number from multiple shifters with different preset bit lengths based on the sorting results.

[0080] Because the exponent values ​​of different floating-point numbers are different, their dimensions may not be consistent. To perform calculations on floating-point numbers, it is first necessary to unify the different floating-point numbers to the same dimension. Here, multiple shifters are used to perform shifting operations on each floating-point number, thus ensuring that all floating-point numbers are on the same dimension. The number of shifters is determined based on the number of floating-point numbers. For example, the number of shifters can be the same as the number of floating-point numbers; or, since the floating-point number corresponding to the maximum exponent value does not require shifting, the number of shifters can be the number of floating-point numbers minus 1, to reduce the hardware resources required.

[0081] Each shifter is pre-set with a different number of bits. The preset number of bits for each shifter includes the maximum range of the mantissa plus the maximum shiftable range of the shifter during the shift process. For example, a 50-bit shifter has 50 bits. Since the maximum mantissa is 24 bits, after removing the space occupied by the mantissa, the maximum shiftable range w of the shifter is 26 bits. In subsequent shifting operations, the shifter moves the mantissa within its maximum shiftable range.

[0082] To minimize hardware overhead, in some embodiments, the preset bit lengths of multiple shifters fall within a first preset range, and the preset bit lengths of each shifter are uniformly distributed within this first preset range. Specifically, the maximum value of the preset bit lengths among the multiple shifters is used as the first preset range, and the shift ranges of the remaining shifters are all within this first preset range. The uniform distribution of the preset bit lengths among the shifters includes increasing or decreasing by a certain multiple, forming an arithmetic sequence, or a geometric sequence, etc. For example, a q-bit shifters (e.g., q = 24 bits + w bits, w = 26 bits), b 2*w-bit shifters, c 3*w-bit shifters, ..., x n*w-bit shifters are pre-configured, where n is the number of floating-point numbers minus 1.

[0083] Specifically, after obtaining the exponent values ​​of each floating-point number, the computer device sorts the floating-point numbers according to the magnitude of their exponent values, obtaining a sorted result. For example, the computer device sorts the floating-point numbers in ascending (or descending) order of their exponent values. Since the floating-point number with the largest exponent value does not require shifting, except for this largest exponent value, the computer device allocates a shifter to each of the remaining floating-point numbers in turn, according to the obtained sorting result.

[0084] In the above embodiments, by assigning different shifters to different floating-point numbers, compared with the prior art which uses multiple shifters of the same bit width for shifting regardless of the size of each floating-point number, the hardware overhead is significantly reduced, and the timing characteristics are good and the efficiency is high.

[0085] In other embodiments, the different preset bit numbers of the multiple shifters may also be non-uniformly distributed within a first preset range. For example, within the first preset range, one shifter may be set to a preset bit number of q bits, while the preset bit numbers of the remaining shifters may all be n*w bits. Alternatively, within the first preset range, the preset bit numbers of each shifter may increase or decrease exponentially. Yet another example is that within the first preset range, every x shifters may have the same preset bit number, and the overall trend may be increasing or decreasing.

[0086] Step S106: For each floating-point number, the mantissa of the corresponding floating-point number is shifted using the shifter allocated to the floating-point number to obtain the shift result.

[0087] Specifically, for a floating-point number, the computer device uses a shifter allocated to that floating-point number to shift the mantissa of the floating-point number within a preset number of bits in the shifter, thus obtaining the shifted result of the floating-point number. Since the floating-point number with the largest exponent does not require shifting, the computer device performs shifting processing on each of the other floating-point numbers using their respective allocated shifters, resulting in multiple shifted results.

[0088] Shifting refers to moving the mantissa a certain distance in a specific direction. Shift directions include left and right shifts. The number of bits shifted in the shift operation is the difference between the floating-point number and its maximum value. For example, for a floating-point number A, if the difference between its exponent and the maximum exponent is b, the computer will shift the mantissa of floating-point number A to the left or right by b bits. The maximum exponent is the largest of the exponents of multiple floating-point numbers.

[0089] Step S108: Determine the floating-point processing result corresponding to the target task based on each shift result.

[0090] Specifically, after the shifting is complete, the computer equipment can perform subsequent processing according to the specific target task. This can involve sequentially compressing each shift result corresponding to its respective floating-point number to obtain a compressed result; the computer equipment then performs post-processing on the compressed result to obtain the floating-point number processing result corresponding to the target task. Post-processing includes standardization and rounding.

[0091] In the aforementioned multi-input floating-point number processing method, multiple shifters with different preset bit widths are pre-designed. When processing multiple floating-point numbers, they can be sorted according to their exponent values. Based on the sorting result, a corresponding shifter is allocated to each floating-point number from the multiple shifters with different preset bit widths. The allocated shifters are then used to perform shift processing on the multiple floating-point numbers, and the floating-point number processing result corresponding to the target task is obtained based on the shift processing result. In this way, the concept of effective shifting is introduced, effectively shifting the last digits of the sorted values ​​while the shift range of the first digits is small (or even unnecessary). While ensuring no intermediate precision loss, the area overhead of the shifters is greatly reduced, thereby saving processor hardware overhead. Under the premise of limited hardware resources, it can well balance the efficiency and accuracy of floating-point number processing.

[0092] As previously mentioned, in some embodiments, the number of multiple shifters is the same as the number of multiple floating-point numbers. For example... Figure 3 As shown, based on the sorting result, a corresponding shifter is assigned to each floating-point number from multiple shifters with different preset bit lengths, including:

[0093] Step S302: Determine the sorting sequence number corresponding to each floating-point number in the sorting result.

[0094] Step S304: Determine the preset number of bits corresponding to each sorting number, and allocate the multiple shifters to the floating-point numbers specified by the sorting numbers corresponding to the respective preset number of bits, according to their preset number of bits.

[0095] Specifically, the computer device determines the sorting index of each floating-point number based on the sorting results. The sorting index indicates the position of the floating-point number in the sorting result. Each sorting index has a pre-set preset number of bits, for example, the first bit is pre-set to correspond to a shifter with x bits, the second bit to a shifter with y bits, and so on. For a floating-point number, the computer device determines the shifter with that preset number of bits based on the sorting index to which the floating-point number belongs. Thus, the association between the floating-point number and the shifter is determined, and the computer device can then allocate the shifter to process the floating-point number.

[0096] For example, the first floating-point number in the sorting result does not need to be shifted; for the second floating-point number, the computer device allocates a q-bit shifter; for the third floating-point number, the computer device allocates a 2q-bit shifter... and so on, until all other floating-point numbers except the first one have been allocated.

[0097] In this embodiment, by assigning different shifters to different floating-point numbers, the hardware overhead is significantly reduced, and the timing characteristics are good and the efficiency is high.

[0098] After allocating a corresponding shifter for each floating-point number, the computer device uses the shifter to perform shifting operations on the floating-point numbers. During the shifting process, the number of bits the shifter uses to shift the mantissa of the floating-point number can be determined based on the difference between its exponent value and the maximum exponent value. Therefore, in some embodiments, such as... Figure 4 As shown, for each floating-point number, the mantissa of the corresponding floating-point number is shifted using a shifter allocated to that number, resulting in the following shifted result:

[0099] Step S402: Based on the difference between the exponent values ​​of each floating-point number and the maximum exponent value, determine the number of shift bits corresponding to the mantissa of each floating-point number, where the maximum exponent value is the maximum value among the exponent values ​​of multiple floating-point numbers.

[0100] Step S404: For each floating-point number, the corresponding mantissa is shifted using the shifter allocated to the floating-point number, based on the number of shift bits corresponding to the mantissa of the corresponding floating-point number, to obtain the shift result.

[0101] Specifically, for a floating-point number, the computer determines the number of bits to shift for each mantissa based on the difference between the exponent and the maximum exponent. Then, using the shifter allocated to the floating-point number, the computer performs the shift operation using the determined number of bits. The difference can refer to the difference between the value and the maximum exponent, the ratio of the value to the maximum exponent, or a multiple of the difference.

[0102] For example, the exponent value E1 of the floating-point number A and the maximum exponent value E max If the difference is x, then the computer determines that the mantissa M1 of the floating-point number A corresponds to a shift of x bits. After determining the shift number, the computer uses the shifter allocated to the floating-point number to shift the mantissa of the floating-point number by x bits, obtaining the shifted result of the floating-point number. Except for the maximum exponent E... max Apart from the corresponding floating-point number (which does not need to be shifted), the computer device shifts all other floating-point numbers to obtain multiple shift results.

[0103] In this embodiment, by assigning different shifters to different floating-point numbers, the hardware overhead is significantly reduced, and the shifter resources required for shift processing are saved.

[0104] During the shifting process, it may be encountered that the determined shift number is larger than the preset number of bits of the shifter. Here, in some embodiments, such as... Figure 5 As shown, for each floating-point number, a shifter corresponding to the floating-point number is used to shift the corresponding mantissa based on the number of shift bits corresponding to the mantissa of the floating-point number, resulting in the shifted result, including:

[0105] Step S502: For each floating-point number, determine whether the number of shift bits corresponding to the mantissa of the floating-point number is within the shift range corresponding to the preset number of bits of the shifter allocated to the floating-point number.

[0106] Step S504: If the number of bits to be shifted is within the shift range, then through the shifter allocated to the floating-point number, each mantissa member constituting the mantissa value in the floating-point number is shifted by the same number of bits in the same shift direction within the corresponding shift range; wherein, the shift direction includes left shift or right shift.

[0107] Step S506: If the number of bits to be shifted is outside the shift range, then by using the shifter corresponding to the floating-point number, each mantissa member of the floating-point number is shifted in the same shift direction by a preset number of bits.

[0108] Step S508: The mantissa obtained after shifting each floating-point number is used as the shift result.

[0109] Specifically, for a floating-point number, the computer device executes step S502 above to obtain the number of shift bits corresponding to the mantissa of the floating-point number. Simultaneously, the computer device determines the shifter allocated to the floating-point number and obtains the preset number of bits for the shifter. The computer device compares the number of shift bits with the preset number of bits to determine whether the number of shift bits is within the shift range corresponding to the preset number of bits. If so, the computer device uses the shifter to shift the mantissa by the number of shift bits in the shift direction; otherwise, the computer device uses the shifter to shift the mantissa by the preset number of bits in the shift direction. After shifting the mantissa of the floating-point number, the resulting mantissa is used as the shift result of the floating-point number. Except for the floating-point number corresponding to the largest exponent (which does not require shifting), the computer device performs the same shifting process on all other floating-point numbers to obtain multiple shift results.

[0110] For example, for a floating-point number A, the computer device determines that the number of bits to be shifted corresponding to its mantissa M1 is 22 bits, and a shifter S is allocated for the floating-point number A. A The preset bit depth is 50 bits, meaning the shift range is 26 bits. Therefore, the computer device determines the shift depth of floating-point number A within the shifter S. A Within the shift range, computer equipment utilizes this shifter S A Each mantissa member of the floating-point number A is shifted 22 bits in the same shift direction, for example, shifted 22 bits to the right.

[0111] For example, for a floating-point number B, the computer device determines that the number of bits to be shifted corresponding to its mantissa M2 is 56 bits, and the shifter S allocated to the floating-point number B... B The preset bit depth is 76 bits, meaning the shift range is 52 bits. Therefore, the computer device determines the shift depth of the floating-point number B within the shifter S. B Outside the shift range, in other words, the number of bits shifted by the floating-point number B has exceeded the shifter S. B The maximum shift range that can be shifted. Therefore, computer devices utilize this shifter S. B Each mantissa member of the floating-point number B is shifted 52 bits in the same shift direction.

[0112] In this embodiment, by assigning shifters with different preset bit widths to the floating-point numbers for shift processing, it is not necessary to use shifters with larger bit widths to ensure lossless intermediate precision, thus saving hardware resources of the shifters and reducing the area overhead of the shifters.

[0113] As previously stated, after determining the shift results of multiple floating-point numbers, the computer device then compresses the floating-point numbers. To reduce the area of ​​the compressor used and to reduce timing paths, in some embodiments, such as... Figure 6 As shown, the floating-point processing result corresponding to the target task is determined based on each shift result, including:

[0114] Step S602: Based on the first preset range where the shifters with different preset bit numbers are located, multiple domain segments are divided, and compressors corresponding to the multiple domain segments are determined respectively, wherein different compressors have different preset compression ratios.

[0115] Compression ratio refers to the ratio of the number of inputs to the number of outputs of a compressor. For example, a compressor with a preset compression ratio of (n:2) has n inputs and 2 outputs; a compressor with a preset compression ratio of (n:3) has n inputs and 3 outputs.

[0116] In some embodiments, the values ​​of different preset compression ratios of the multiple compressors are within a second preset range, and the preset compression ratio values ​​of each compressor are uniformly distributed within the second preset range. The second preset range is obtained based on the number of floating-point numbers. Specifically, the preset compression ratio of the compressors is within the second preset range determined by (n:2) as the maximum value of the range. This second preset range may also include, for example, (n-1):2, (n-2):2, etc., where n is the number of floating-point numbers.

[0117] Specifically, the computer device divides the first preset range where each shifter has a different preset number of bits, resulting in multiple domain segments. For example, based on the maximum preset number of bits among the shifters, the range from the most significant bit to the maximum preset number of bits is determined, and this range is equally divided into multiple domain segments; wherein the range of each domain segment is equal.

[0118] For example, in a compression process involving four floating-point numbers, the computer device determines the compression ratio of the compressor corresponding to the most significant bit segment to be 4:2; for the next most significant bit segment, the computer device determines the compression ratio of the compressor corresponding to the next most significant bit segment to be 3:2; and for the least significant and next least significant bit segments, since no compression is required, no compressor needs to be allocated. Because the mantissa values ​​within the least significant and next least significant bit segments do not need to be compressed, the number of compressors is the number of floating-point numbers minus two.

[0119] Step S604: For each domain segment, determine the multiple intra-domain shift results within the corresponding domain segment, wherein a single intra-domain shift result is the intra-domain part of the shift result corresponding to a single floating-point number.

[0120] Specifically, for a given domain segment, the computer device determines the portion of the shift results of all floating-point numbers within that domain segment that is located within that domain segment; this portion is called the intra-domain portion. For example, if the highest bit segment is the highest w bits, then within that domain segment, the computer device obtains the value of the highest w bits of the shift results of each floating-point number. The intra-domain shift results of all the floating-point numbers obtained are the multiple intra-domain shift results within that domain segment.

[0121] Step S606: Through each compressor, the multiple intra-domain shift results within the corresponding domain segment of the compressor are segmented and compressed to obtain multiple segmented compression results.

[0122] Specifically, the computer equipment uses the compressor allocated to each domain segment to perform segmented compression processing on the multiple intra-domain shift results within each divided domain segment, resulting in multiple segmented compression results.

[0123] For example, in a compression process with n floating-point numbers, the computer device performs segmented compression processing on the highest-order segment using a compressor with a compression ratio of (n:2); on the second-highest-order segment, the computer device performs segmented compression processing on the second-highest-order segment using a compressor with a compression ratio of (n-1):2, and so on; while the lowest-order and second-lowest-order segments do not require compression processing.

[0124] Step S608: Based on multiple segmented compression results, determine the floating-point processing result corresponding to the target task.

[0125] Specifically, the computer device further processes each segmented compression result based on the segmented compression results corresponding to each domain segment, thereby determining the floating-point processing result corresponding to the target task. For example, the computer device concatenates the multiple segmented compression results after segmented compression processing according to the order of the number of bits to form a complete compression result, and then inputs the compression result into an adder for processing, finally obtaining the floating-point processing result corresponding to the target task.

[0126] In this embodiment, by dividing the domain into multiple segments and performing segmented compression, the input of the lower-order domain segment compressor is less (or even does not need to be compressed), which greatly reduces the area of ​​the compressor and reduces the timing path.

[0127] like Figure 7 As shown, in some embodiments, each compressor performs segmented compression processing on multiple intra-domain shift results within the domain segment corresponding to its respective compressor, resulting in multiple segmented compression results, including:

[0128] Step S702: For each compressor, the multiple intra-domain shift results within its corresponding domain segment are used as the input of the corresponding compressor.

[0129] In step S704, each compressor performs segmented compression processing on its own input according to its corresponding preset compression ratio to obtain the local result and the carry result. The local result and the carry result constitute the segmented compression result corresponding to the segmenter.

[0130] Specifically, for a compressor, the computer device takes multiple intra-domain shift results within the corresponding domain segment as input to the compressor, and then performs segmented compression processing on the multiple intra-domain shift results within the domain segment according to the compressor's preset compression ratio, obtaining the local result and the carry result. The local result is the sum of the compressed intra-domain shift results, and the carry result is the carry value of this sum.

[0131] For example, such as Figure 8 As shown, taking the compression process of four floating-point numbers (floating-point number A, floating-point number B, floating-point number C, and floating-point number D) as an example, for the highest w-bit segment, the computer device uses a 4:2 compressor to perform segmented compression on the four intra-domain shift results within this segment, obtaining the current bit result and the carry result. If there is a carry in the current bit result, the corresponding carry result is 1; otherwise, it is 0. For the next highest w-bit segment, the computer device uses a 3:2 compressor to perform segmented compression on the three intra-domain shift results within this segment. The lowest and next lowest bit segments do not require compression.

[0132] In this embodiment, by dividing the compression into domain segments and setting up different compressors for compression, the area of ​​the compressor is greatly reduced, thus reducing the overhead of hardware resources.

[0133] As mentioned above, after obtaining the segmented compression results corresponding to each domain segment, the computer device further processes each segmented compression result to determine the final floating-point processing result. In the prior art, after compressing to obtain carry (corresponding to the local result in the embodiments of this application) and sum (corresponding to the carry result in the embodiments of this application), the computer device uses a CPA (Carry Propagate Adder) to perform carry-passing addition on carry and sum to obtain the floating-point processing result.

[0134] However, the existing method requires carry-passing addition of two full-width inputs (carry and sum), necessitating at least one 128-bit adder, which consumes significant hardware resources and suffers from poor timing. Therefore, computer devices allocate different adders to different data segments for addition processing; since addition is performed segmentally, the carry situation of each segment must also be considered. Thus, to reduce hardware resource consumption, in some embodiments, such as... Figure 9As shown, based on multiple segmented compression results, the floating-point processing result corresponding to the target task is determined, including:

[0135] Step S902: For the first domain segment among the multiple domain segments that have not undergone compression processing and have only a single intra-domain shift result, the single intra-domain shift result is used as the selection result of the first domain segment.

[0136] Step S904: For the second domain segment among the multiple domain segments that have not undergone compression processing and have more than one intra-domain shift result, generate the true value result and the pseudo value result of the second domain segment based on the more than one intra-domain shift result within the second domain segment.

[0137] Step S906: For the third domain segment that has been compressed among the multiple domain segments obtained by division, generate the true value result and the pseudo value result of the corresponding third domain segment based on the segmented compression result of each third domain segment.

[0138] Step S908: According to the bit height of the domain segment, starting from the lowest bit domain segment, determine the selection result corresponding to each domain segment in sequence until the selection result of the highest bit domain segment is obtained. Among them, the selection result of the other domain segments except the first domain segment is one of the true value result and the pseudo value result of the corresponding domain segment.

[0139] Step S910: Based on the selection results of each domain segment, determine the floating-point processing result corresponding to the target task.

[0140] For each domain segment, the computer first performs addition on the segmented compression results within that segment to obtain a true value result and a pseudo-value result. The true value result is the actual summation obtained by adding the shifted results within the domain, while the pseudo-value result is a simulated summation calculated by adding the shifted results within the domain, assuming a carry. Then, the computer inputs the true value result and pseudo-value result for each domain segment into a selector for selection, and the selector ultimately determines which result to output.

[0141] Specifically, in the multiple domain segments divided by the computer device, the least significant domain segment (referred to as the first domain segment) does not need to be compressed, and there is only one intra-domain shift result in this domain segment. Therefore, the computer device does not need to perform addition processing on this domain segment, nor does it need to make a selection, because there is no need to allocate adders and selectors, and the intra-domain shift result can be directly used as the selection result of the first domain segment.

[0142] The second-lowest bit segment (referred to as the second segment) also does not require compression. However, this second segment contains more than one intra-domain shift result, requiring addition. The computer then performs addition on all intra-domain shift results within the second segment to calculate the true value and approximate value of the second segment.

[0143] Except for the least significant and second least significant segments, the intra-segment shift results in all other segments (referred to as the third segment) have been compressed, and there are multiple intra-segment shift results within each third segment. Therefore, for each third segment, the computer device performs addition on the segmented compressed results within the third segment to generate the true value and pseudo-value results for the third segment.

[0144] After determining the true and approximate results for each segment except the first segment, the computer device inputs each true and approximate result into a selector, which then determines whether the output result is the true or approximate result. To improve efficiency, the computer device selects the segments sequentially, starting with the least significant bit segment and proceeding up to the most significant bit segment. The selection result corresponding to the least significant bit segment is the original intra-segment shift result within that segment. Since the least significant bit segment has not undergone compression or addition, there is no carry, therefore the selection result of the second least significant bit segment is the true result. For each third segment, the selection result of the higher bit segments needs to consider whether there is a carry in the lower bit segments of adjacent segments; if there is a carry in the lower bit segments, the selector outputs the selection result of the higher bit segments as the approximate result; otherwise, the selector outputs the selection result of the higher bit segments as the true result.

[0145] For example, such as Figure 10 As shown, for the highest-order bit segment, the computer device inputs the carry through the selector of the second-highest-order bit segment, and the selector of the highest-order bit segment outputs either a true value or a pseudo-value. Similarly, the computer device performs the same processing for the second-highest-order bit segment. For the second-lowest-order bit segment, since there is no carry in the lowest-order bit segment, the selector of the second-lowest-order bit segment outputs a true value. For the lowest-order bit segment, since no compression or addition processing is required, it directly outputs the original intra-domain shift result.

[0146] Therefore, the computer device outputs the selection results corresponding to all domain segments through the selector.

[0147] In this embodiment, by adopting a segmented addition strategy, different adders are assigned to different domain segments for segmented addition processing. Then, multiple selectors are used to pass the carry according to the carry situation of each domain segment. Compared with the addition of the full bit width for carry passing in the prior art, the hardware resources required are reduced, the length of the critical path is effectively reduced, and the timing characteristics are good.

[0148] Subsequently, the computer device concatenates the selection results under each domain segment to obtain the complete floating-point processing result within the first preset range. Therefore, in some embodiments, determining the floating-point processing result corresponding to the target task based on the selection results of each domain segment includes: concatenating the selection results of each domain segment sequentially according to the bit height of each segment to obtain the floating-point processing result corresponding to the target task. Specifically, the computer device concatenates the selection results of adjacent domain segments one by one, from high to low (or from low to high), according to the bit height of each domain segment, thereby obtaining the floating-point processing result within the entire first preset range.

[0149] In this embodiment, due to the adoption of segmented compression and segmented addition strategies, the results of each domain segment are then concatenated to obtain the complete floating-point processing result. This method does not require the use of full-width compressors and adders, reduces the length of the critical path, and has good timing characteristics.

[0150] Floating-point numbers offer high effective precision, making them more suitable for scientific and engineering calculations. However, in scientific notation, if the representation of a floating-point number is not explicitly defined, its encoding in a computer is not unique, which hinders the computer's recognition and processing. For example, a decimal number can be represented as 1.11 × 10⁻¹⁰. 0 0.111×10 1 0.0111×10 2 There are multiple representations, such as floating-point numbers. However, since normalized floating-point numbers have a unique representation, they need to be normalized in floating-point arithmetic.

[0151] To ensure that the obtained floating-point number processing results conform to the normalized floating-point number standard, in some embodiments, after obtaining the floating-point number processing results, the computer device further performs normalization processing on the floating-point number processing results to make the floating-point number processing results conform to the preset floating-point number standard. By performing normalization processing on the floating-point number processing results to ensure that the obtained floating-point number processing results conform to the normalized floating-point number standard, the computer does not need to identify and convert each floating-point number processing result during processing, resulting in higher processing efficiency and avoiding the problem of inaccurate calculations caused by the non-unique encoding representation of floating-point numbers.

[0152] Normalization, also known as formatted output, refers to converting a floating-point number according to a specified format. The absolute value of the mantissa M of the normalized floating-point number should satisfy 1 / r ≤ |M| < 1, where r is the base, usually 2, 8, or 16.

[0153] Normalization refers to adjusting the mantissa and exponent of a denormalized floating-point number to ensure that the most significant bit of the mantissa is valid for a non-zero floating-point number. In some embodiments, such as... Figure 11 As shown, the normalization process for floating-point number processing results includes:

[0154] Step S1102: Determine the first symbol identifier and the second symbol identifier in the floating-point number processing result.

[0155] Step S1104: If the first symbol identifier is the same as the second symbol identifier, then the mantissa value in the floating-point number processing result is shifted according to the first shift direction.

[0156] Step S1106: If the first symbol identifier is different from the second symbol identifier, then the mantissa value in the floating-point number processing result is shifted according to the second shift direction; wherein, the second shift direction is opposite to the first shift direction.

[0157] There are two methods for normalizing floating-point numbers: left normalization and right normalization. Left normalization refers to normalizing a floating-point number when the result of the operation is denormalized by shifting the mantissa one bit to the left and decrementing the exponent by 1 (when the radix r = 2). Left normalization may be performed multiple times. Right normalization refers to normalizing a floating-point number when the mantissa overflows. This involves shifting the mantissa one bit to the right and incrementing the exponent by 1 (when the radix r = 2). Right normalization only needs to be performed once.

[0158] Specifically, the computer device acquires a first symbol identifier and a second symbol identifier from the floating-point number processing result. If the first symbol identifier and the second symbol identifier are the same (i.e., the first symbol identifier and the second symbol identifier constitute 00 or 11), the mantissa value in the floating-point number processing result is shifted according to a first shift direction. If the first symbol identifier and the second symbol identifier are different (i.e., the first symbol identifier and the second symbol identifier constitute 01 or 10), the mantissa value in the floating-point number processing result is shifted according to a second shift direction; wherein the second shift direction is opposite to the first shift direction. Taking the floating-point number normalization method under the IEEE 754 standard as an example, the first shift direction is left shift, and the second shift direction is right shift.

[0159] For example, if the computer determines that two sign identifiers are the same, it means there is no overflow. However, if the highest value bit of the floating-point processing result is the same as the sign identifier, then left-shifting is required. This involves shifting the mantissa to the left until the highest value bit is different from the sign identifier. For example, consider the following two floating-point processing results: 111××× and 000×××. Shifting 111××× left by one bit results in 11×××0; shifting 000××× left by one bit results in 00×××0. Finally, the exponent value is subtracted from the number of shifts.

[0160] If the computer determines that two sign identifiers are different, it indicates that the operation result has overflowed. In this case, right-shifting is required, which involves shifting the mantissa of the floating-point result to the right until no overflow occurs; then, the exponent value is increased by the number of shifts. For example, consider the following two floating-point results: 01×××× and 10××××. Shifting 01××× one bit to the right results in 001×××; shifting 10×××× one bit to the right results in 110×××. Finally, the exponent value is increased by 1.

[0161] In this embodiment, by normalizing the floating-point number processing results, the effective number of bits in the mantissa is fully utilized, thereby improving the accuracy of floating-point number operations.

[0162] In some embodiments, after normalizing a floating-point number, some values ​​may be added to the lower digits of the mantissa. These added values ​​need to be rounded, for example, rounding 1.2349999 down to 1.23, or rounding 1.2350001 up to 1.24. The IEEE 754 standard specifies the following rounding methods: rounding to the nearest even number, rounding up, rounding down, and rounding towards 0. However, this is not the only option; different floating-point standards may have different rounding methods. In practical applications, the appropriate rounding method can be selected according to the requirements.

[0163] This application also provides an application scenario in which the above-described multi-input floating-point number processing method is applied. In some embodiments, the multi-input floating-point number processing method is applied in this scenario, for example, to process a target task, wherein the target task is a subtask in a neural network processing task, and the neural network task includes at least one of a convolution processing task and a similarity processing task. In this application scenario, the above-described multi-input floating-point number processing method further includes: executing subsequent subtasks in the neural network processing task based on the floating-point number processing result to obtain the neural network processing result.

[0164] Specifically, in the process of training and applying neural networks, it is necessary to perform calculations on image data, audio data, and text data. The image data, audio data, and text data processed by neural networks are usually represented by floating-point numbers in computers. For example, each pixel in an image is represented by a 32-bit single-precision floating-point number between 0 and 255, where 255 represents white and 0 represents black. Similarly, the audio data read is a floating-point number within the sampling range.

[0165] In neural network processing tasks, several subtasks involve handling floating-point numbers. For example, performing convolution or deconvolution operations on input image data. Taking convolution as an example, convolution is the sum of the products of two data points within a certain range. During convolution, the computer can use its processor to execute the aforementioned multi-input floating-point processing methods to sum multiple floating-point numbers and obtain the floating-point processing result. Then, based on this result, subsequent convolution operations are performed. Therefore, in neural network processing tasks, the computer can execute subsequent subtasks based on the floating-point processing result to obtain the neural network processing result, such as outputting processed image data.

[0166] For example, the multi-input floating-point number processing method described above can also be used for similarity processing tasks in neural network processing tasks. Taking image data as an example, in a similarity processing task, it is necessary to compare the processed image data with pre-set standard image data to calculate the similarity between the two. During the similarity calculation process, the computer device can use the multi-input floating-point number processing method described above to perform difference calculations on the floating-point numbers corresponding to the image data, thereby obtaining the floating-point number processing result. Based on the obtained floating-point number processing result, the computer device can continue to execute subsequent sub-tasks in the neural network processing task, such as classifying the image data based on the difference indicated by the floating-point number processing result, and finally outputting the neural network processing result (e.g., the image classification result).

[0167] Of course, this is not the only option. Those skilled in the art will understand that, without departing from the inventive concept and ideas disclosed in this application, any computational processing task applicable to multiple floating-point numbers can be used as the aforementioned target task, such as data computation tasks in cloud computing scenarios, or computational tasks in the data processing process performed by intelligent sensors (e.g., edge sensors).

[0168] In this embodiment, by applying the above-described multi-input floating-point number processing method to tasks such as neural network processing, high-precision floating-point number processing of neural networks can be achieved, thereby improving the computational performance of neural networks.

[0169] To illustrate the inventive concept of this application as clearly as possible, an example of performing addition of multiple floating-point numbers is used here to explain the differences and advantages compared with the traditional method.

[0170] In a specific example, the traditional floating-point number processing flow is as follows: Figure 12 As shown, the computer device first obtains the exponents of n floating-point numbers and compares them using a comparator to obtain the largest exponent value. Simultaneously, the computer device obtains the mantissas of the n floating-point numbers. Then, for a given floating-point number, the computer device inputs the difference between its exponent and the largest exponent, along with the mantissa, into a fixed-size shifter to perform a shift operation on the floating-point number. The computer performs the same process for all other floating-point numbers. Since the mantissas of each floating-point number vary in size, to ensure no intermediate precision loss, the range of the shifter used needs to be the maximum value m * w bits, where m is the number of floating-point numbers minus 1.

[0171] To achieve zero intermediate precision loss during the shifting process, the width of the shifted data bit must be very wide. Taking five 32-bit single-precision floating-point numbers as an example, the width of the shifted data bit needs to reach 128 bits to guarantee zero intermediate precision (the specific 128-bit structure is as follows...). Figure 13 As shown, each floating-point number has a 24-bit extended mantissa (with 2 bits reserved for carry). Excessive shift range results in huge hardware overhead and poor timing, making it difficult for computer processors to achieve high clock speeds.

[0172] Similarly, after the shift is complete, the computer inputs the shifted result into an n:2 compressor for compression (where n is the number of inputs to the multi-input floating-point adder), resulting in two outputs: carry and sum. Then, carry and sum are added with carry-forward. The final addition result is sent to the normalize unit to perform floating-point standardization. Finally, the standardized data is rounded to obtain the final floating-point addition result. Here, the compressor uses n:2 compression for the full bit width. Taking five 32-bit single-precision floating-point numbers as an example, the compressor uses a 128-bit 5:2 compressor, resulting in a huge area overhead. In the subsequent addition stage, the two full-width inputs (carry and sum) are also added with carry-forward. Again, taking five 32-bit single-precision floating-point numbers as an example, a 128-bit adder is needed, leading to poor timing.

[0173] Compared to traditional methods, such as Figure 14As shown in the embodiments of this application, the multi-input floating-point number processing method mainly includes the following steps: First, the computer device obtains the exponents of n floating-point numbers and compares them using a comparator to obtain the largest exponent value. Simultaneously, the computer device obtains the mantissas of the n floating-point numbers. Before inputting them into the shifters for shifting, the computer device sorts the floating-point numbers according to their exponent values. That is, for the floating-point number with the largest exponent, no shifting operation is required; for the second-ranked floating-point number, only w bits need to be shifted; for the third-ranked floating-point number, only 2*w bits need to be shifted… and so on. For the floating-point number with the smallest exponent (last rank), the shift range is m*w. Taking five 32-bit single-precision floating-point numbers as an example, m = 4, w = 26. According to the sorting result, the computer dynamically allocates shifters for each floating-point number, without needing to use a shifter of the same fixed size for each floating-point number. Compared to existing technologies, this significantly reduces the area overhead of the shifters.

[0174] Then, the computer inputs the mantissa of each floating-point number into the corresponding shifter for shifting. The shifted results are then input into the corresponding compressors. Specifically, the computer assigns a compressor with a different compression ratio to each segment. That is, for the highest w bit, an n:2 compressor is used; for the second highest w bit, an (n-1):2 compressor is used, and so on. For the lowest and second lowest w bits, no compressor is needed. Therefore, no compressor needs to be allocated. Compared to existing technologies, this significantly reduces the area overhead of the compressor.

[0175] Then, for each segment, the computer device performs an addition operation using a CPA. For the lowest w bit, no addition operation is needed; the shift result of that w bit is directly obtained. For the second lowest w bit, since there are two floating-point shift results within the segment (corresponding to the intra-segment shift results in the previous embodiment), the computer device performs an addition operation using a CPA. Since there is no carry in the subsequent w bits (least lowest bit) of this w bit (second lowest bit), the actual sum result is output for this w bit. For other segments, depending on whether there is a carry in the next segment (adjacent low-order segment), the MUX (selector) selects whether to output the actual sum result (corresponding to the true result in the previous embodiment) or the sum result containing the carry (corresponding to the pseudo-value result in the previous embodiment), thus obtaining multiple selection results.

[0176] Finally, the computer concatenates the various selection results to obtain the final addition result. Post-processing is then performed to normalize the addition result to conform to the format specified by IEEE 754, followed by rounding to obtain the final result.

[0177] Compared to traditional methods, this approach introduces the concept of efficient shifting. The last few digits in the sorted sequence are shifted effectively, with the shift range for the first few digits being small (or even negligible), significantly reducing the area overhead of the shifter. Furthermore, based on this efficient shifting approach, the entire bit width is divided into segments and compressed in each segment. The lower-order segments have fewer inputs to the compressor (or even no compression at all), greatly reducing the compressor area and timing path. In the final addition stage, a segmented addition strategy is employed, effectively reducing the length of the critical path. Therefore, lossless multi-input floating-point processing can be achieved with minimal hardware area, significantly reducing the overall processor area and effectively increasing the processor's core frequency.

[0178] Taking five 32-bit single-precision floating-point numbers as an example, and using Global Foundries' (GF) 12nm process technology as the area estimation standard, the shifter resources required by this invention are compared with those of existing technologies in Table 1 below:

[0179]

[0180]

[0181] Table 1

[0182] As can be seen, the shifter resources used in this invention are only 55.6% of those in the prior art, which greatly saves the area cost of the shifter.

[0183] In the compression stage, the compressor resources used in this invention are compared with those used in the prior art, as shown in Table 2 below:

[0184]

[0185] Table 2

[0186] As can be seen, the compressor resources used in this invention are 39% of those in the prior art, which greatly saves on compressor area costs.

[0187] Furthermore, in terms of timing, the critical path from shift processing to adder output in the prior art is: 128-bit shift -> 5:2 compressor -> 128-bit adder; while in this invention, the critical path from shift processing to adder output is: 128-bit shift -> 5:2 compressor -> 24-bit adder, which effectively reduces the length of the critical path and can achieve a higher processor clock frequency.

[0188] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0189] Based on the same inventive concept, this application also provides a multi-input floating-point number processing apparatus for implementing the multi-input floating-point number processing method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more multi-input floating-point number processing apparatus embodiments provided below can be found in the limitations of the multi-input floating-point number processing method described above, and will not be repeated here.

[0190] In some embodiments, such as Figure 15 As shown, a multi-input floating-point processing device 1500 is provided. This device can be a software module, a hardware module, or a combination of both, integrated into a computer device. Specifically, the device includes: an acquisition module 1501, an allocation module 1502, a shift module 1503, and a determination module 1504, wherein:

[0191] The acquisition module 1501 is used to acquire multiple floating-point numbers to be processed corresponding to the target task, and extract the exponent value of the exponent part and the mantissa value of the mantissa part of each floating-point number respectively.

[0192] The allocation module 1502 is used to sort multiple floating-point numbers according to the magnitude of the exponent value of each floating-point number, and allocate a corresponding shifter for each floating-point number from multiple shifters with different preset bit lengths based on the sorting result.

[0193] The shift module 1503 is used to shift the mantissa of each floating-point number by means of a shifter corresponding to the floating-point number, so as to obtain the shift result.

[0194] The determination module 1504 is used to determine the floating-point processing result corresponding to the target task based on each shift result.

[0195] In some embodiments, the different preset bit numbers of the multiple shifters are within a first preset range, and the preset bit numbers of each shifter are uniformly distributed within the first preset range.

[0196] In some embodiments, the number of multiple shifters is the same as the number of multiple floating-point numbers. The allocation module is further configured to determine the sorting number corresponding to each floating-point number in the sorting result; determine the preset number of bits corresponding to each sorting number; and allocate the multiple shifters to the floating-point numbers specified by the sorting numbers corresponding to the respective preset number of bits, according to the preset number of bits they have.

[0197] In some embodiments, the shift module is further configured to determine the number of shift bits corresponding to the mantissa of each floating-point number based on the difference between the exponent values ​​of each floating-point number and the maximum exponent value, wherein the maximum exponent value is the maximum value among the exponent values ​​of multiple floating-point numbers; for each floating-point number, the corresponding mantissa value is shifted based on the number of shift bits corresponding to the mantissa value of the corresponding floating-point number by a shifter allocated to the floating-point number to obtain the shift result.

[0198] In some embodiments, the shift module is further configured to, for each floating-point number, determine whether the number of shift bits corresponding to the mantissa of the floating-point number is within the shift range corresponding to the preset number of bits of the shifter allocated to the floating-point number; if the number of shift bits is within the shift range, then, through the shifter allocated to the floating-point number, each mantissa member constituting the mantissa in the floating-point number is shifted by the same number of bits in the same shift direction within the corresponding shift range; wherein, the shift direction includes left shift or right shift; if the number of shift bits is outside the shift range, then, through the shifter allocated to the floating-point number, each mantissa member constituting the mantissa in the floating-point number is shifted by the same preset number of bits in the same shift direction; and the mantissa obtained after shifting each floating-point number is taken as the respective shift result.

[0199] In some embodiments, the determining module further includes a compression unit, which is used to divide a first preset range based on the position of shifters with different preset bit lengths into multiple domain segments, and determine compressors corresponding to the multiple domain segments respectively, wherein different compressors have different preset compression ratios; for each domain segment, determine multiple intra-domain shift results within the corresponding domain segment, wherein a single intra-domain shift result is the intra-domain portion of the shift result corresponding to a single floating-point number; through each compressor, perform segmented compression processing on the multiple intra-domain shift results within the domain segment corresponding to the corresponding compressor to obtain multiple segmented compression results; based on the multiple segmented compression results, determine the floating-point number processing result corresponding to the target task.

[0200] In some embodiments, the values ​​of different preset compression ratios of the multiple compressors are within a second preset range, and the values ​​of the preset compression ratios of each compressor are uniformly distributed within the second preset range.

[0201] In some embodiments, the compression unit is further configured to use multiple intra-domain shift results within their respective domain segments as inputs to each compressor; each compressor performs segmented compression processing on its respective input according to its respective preset compression ratio to obtain the local result and the carry result, and the local result and the carry result constitute the segmented compression result corresponding to the corresponding segmenter.

[0202] In some embodiments, the determining module further includes an addition unit, which is used to: for a first domain segment that has not undergone compression processing and corresponds to only a single intra-domain shift result among the multiple domain segments obtained by partitioning, use the single intra-domain shift result as the selection result of the first domain segment; for a second domain segment that has not undergone compression processing among the multiple domain segments obtained by partitioning and corresponds to more than one intra-domain shift result, generate a true value result and a pseudo value result of the second domain segment based on the more than one intra-domain shift result within the second domain segment; for a third domain segment that has undergone compression processing among the multiple domain segments obtained by partitioning, generate a true value result and a pseudo value result of the corresponding third domain segment based on the segmented compression result corresponding to each third domain segment; determine the selection result corresponding to each domain segment sequentially from the lowest bit domain segment according to the bit height of the domain segment, until the selection result of the highest bit domain segment is obtained, wherein the selection result of other domain segments besides the first domain segment is one of the true value result and the pseudo value result of the corresponding domain segment; and determine the floating-point processing result corresponding to the target task based on the selection results of each domain segment.

[0203] In some embodiments, the determining module further includes a splicing unit, which is used to splice the selection results of each domain segment in descending order of bit segment height to obtain the floating-point processing result corresponding to the target task.

[0204] In some embodiments, the above-described apparatus further includes a post-processing module for normalizing the floating-point processing results so that the floating-point processing results conform to a preset floating-point standard.

[0205] In some embodiments, the post-processing module is further configured to determine a first symbol identifier and a second symbol identifier in the floating-point number processing result; if the first symbol identifier and the second symbol identifier are the same, the mantissa value in the floating-point number processing result is shifted according to a first shift direction; if the first symbol identifier and the second symbol identifier are different, the mantissa value in the floating-point number processing result is shifted according to a second shift direction; wherein the second shift direction is opposite to the first shift direction.

[0206] In some embodiments, the target task is one of the subtasks in the neural network processing task, and the neural network task includes at least one of the convolution processing task and the similarity processing task; the above-mentioned apparatus further includes a task module, which is used to execute the subsequent subtasks in the neural network processing task based on the floating-point number processing result to obtain the neural network processing result.

[0207] For specific limitations regarding the multi-input floating-point processing device, please refer to the limitations on the multi-input floating-point processing method above, which will not be repeated here. Each module in the aforementioned multi-input floating-point processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0208] Based on the same inventive concept and idea, this application also provides a processor for implementing the multi-input floating-point number processing method involved in the above embodiments. In some embodiments, such as Figure 16 As shown, the processor 1600 includes at least one shifter 1601 with a different preset number of bits and a logic processing unit 1602. In different implementation scenarios, the processor can present various package structures depending on the requirements of different computer devices.

[0209] Among them, at least one shifter 1601 with a different preset number of bits is assigned to shift the mantissa of one of the multiple floating-point numbers to be processed; wherein the shifter assigned to each floating-point number is determined by sorting the exponent values ​​of the exponent parts of each floating-point number.

[0210] The logic processing unit 1602 is used to perform logical processing on the multiple shift results obtained from the shift processing of each shifter to obtain the floating-point number processing result.

[0211] In some embodiments, at least one shifter has different preset bit numbers within a first preset range, and the preset bit numbers of each shifter are uniformly distributed within the first preset range.

[0212] In some embodiments, such as Figure 17 As shown, the logic processing unit 1602 includes:

[0213] At least one compressor 16021 with a different preset compression ratio is connected to a shifter. Each compressor is assigned to perform segmented compression processing on multiple shifted results obtained by the shifting process to obtain segmented compression results.

[0214] At least one adder 16022 is connected to the compressor 16021 and is used to generate true and pseudo results of multiple domain segments based on the segmented compression results.

[0215] At least one selector 16023 is connected to adder 16022 and is used to determine the selection result of each field based on the truth value result and the pseudo value result of multiple fields; the selection result is used to concatenate to generate floating-point number processing result.

[0216] In some embodiments, the values ​​of different preset compression ratios of at least one compressor are within a second preset range, and the values ​​of the preset compression ratios of each compressor are uniformly distributed within the second preset range.

[0217] For specific limitations regarding the processor, please refer to the limitations on multi-input floating-point number processing methods mentioned above, which will not be repeated here. The various components in the processor described above can be implemented, in whole or in part, through combinations of gate circuits, switching circuits, and other circuit components. These components can be integrated and embedded within the processor of the computer device, allowing the processor to invoke and execute the operations corresponding to each component.

[0218] In some embodiments, a computer device is provided, which may be a server or terminal including the aforementioned processor. The server may be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server providing cloud computing services. The terminal may be a smartphone, tablet computer, laptop computer, desktop computer, smart speaker, smartwatch, in-vehicle terminal, smart TV, etc. The internal structure diagram of the computer device may be as follows. Figure 18As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores floating-point numbers. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements a multi-input floating-point number processing method.

[0219] Those skilled in the art will understand that Figure 18 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0220] In some embodiments, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0221] In some embodiments, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0222] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0223] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0224] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0225] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for processing multi-input floating-point numbers, characterized in that, The method includes: Obtain multiple floating-point numbers to be processed corresponding to the target task, and extract the exponent value of the exponent part and the mantissa value of the mantissa part of each floating-point number respectively. The floating-point numbers are sorted according to their exponent values. Based on the sorting results, a corresponding shifter is assigned to each floating-point number from a plurality of shifters with different preset bit lengths. The number of shifters is the same as the number of floating-point numbers. The process includes: determining the sorting number corresponding to each floating-point number in the sorting results; determining the preset bit length corresponding to each sorting number according to the preset bit length set in advance for each sorting number; and assigning the plurality of shifters to the floating-point numbers specified by the sorting numbers corresponding to the preset bit lengths, wherein the tail values ​​of the later sorted values ​​are effectively shifted, and the tail values ​​of the earlier sorted values ​​have a smaller shift range. For each floating-point number, the mantissa of the corresponding floating-point number is shifted using a shifter allocated to that floating-point number to obtain the shift result; The floating-point processing result corresponding to the target task is determined based on each of the shift results.

2. The method according to claim 1, characterized in that, The different preset number of bits of the multiple shifters are within a first preset range, and the preset number of bits of each shifter is evenly distributed within the first preset range.

3. The method according to claim 1, characterized in that, For each floating-point number, the mantissa of the corresponding floating-point number is shifted using a shifter allocated to that number to obtain the shift result, including: Based on the difference between the exponent values ​​of each floating-point number and the maximum exponent value, the number of shift bits corresponding to the mantissa of each floating-point number is determined, wherein the maximum exponent value is the maximum value among the exponent values ​​of multiple floating-point numbers. For each floating-point number, the corresponding mantissa is shifted using a shifter allocated to that floating-point number, based on the number of shift bits corresponding to the mantissa of the floating-point number, to obtain the shift result.

4. The method according to claim 3, characterized in that, For each floating-point number, a shifter corresponding to that floating-point number is used to shift the corresponding mantissa based on the number of shift bits corresponding to the mantissa of the floating-point number, to obtain the shift result, including: For each floating-point number, determine whether the number of shift bits corresponding to the mantissa of the floating-point number is within the shift range corresponding to the preset number of bits of the shifter allocated to the floating-point number; If the number of shift bits is within the shift range, then through the shifter corresponding to the floating-point number, within the corresponding shift range, each mantissa member constituting the mantissa value in the floating-point number is shifted in the same shift direction by the number of shift bits; wherein, the shift direction includes left shift or right shift; If the number of shift bits is outside the shift range, then by using the shifter corresponding to the floating-point number, each mantissa member constituting the mantissa value in the floating-point number is shifted in the same shift direction by the preset number of bits. The mantissa obtained after shifting each floating-point number is used as the shift result.

5. The method according to claim 1, characterized in that, The step of determining the floating-point processing result corresponding to the target task based on each of the shift results includes: Based on the first preset range of shifters with different preset bit numbers, multiple domain segments are obtained, and compressors corresponding to the multiple domain segments are determined respectively, wherein different compressors have different preset compression ratios. For each domain segment, determine the multiple intra-domain shift results within the corresponding domain segment. The single intra-domain shift result is the intra-domain part of the shift result corresponding to a single floating-point number. Each compressor is used to perform segmented compression on multiple intra-domain shift results within the domain segment corresponding to the respective compressor, resulting in multiple segmented compression results. Based on the multiple segmented compression results, the floating-point processing result corresponding to the target task is determined.

6. The method according to claim 5, characterized in that, The values ​​of the different preset compression ratios of the multiple compressors are within a second preset range, and the values ​​of the preset compression ratios of each compressor are evenly distributed within the second preset range.

7. The method according to claim 5, characterized in that, The process involves segmenting and compressing multiple intra-domain shift results within their respective domain segments using each compressor, resulting in multiple segmented compression results, including: For each compressor, the multiple intra-domain shift results within its corresponding domain segment are used as the input of the corresponding compressor. Each compressor performs segmented compression processing on its own input according to its corresponding preset compression ratio, and obtains the local result and the carry result. The local result and the carry result constitute the segmented compression result corresponding to the corresponding segmenter.

8. The method according to claim 5, characterized in that, The step of determining the floating-point processing result corresponding to the target task based on the multiple segmented compression results includes: For the first domain segment among the multiple domain segments that has not undergone compression processing and corresponds to only a single intra-domain shift result, the single intra-domain shift result is used as the selection result of the first domain segment; For a second domain segment that has not undergone compression processing and corresponds to more than one intra-domain shift result among the multiple domain segments obtained by division, the true value result and the pseudo value result of the second domain segment are generated based on the more than one intra-domain shift result in the second domain segment. For the third domain segment that has been compressed among the multiple domain segments obtained, the true value result and the pseudo value result of the corresponding third domain segment are generated based on the segmented compression result of each third domain segment. According to the bit height of the domain segment, starting from the lowest bit domain segment, the selection result corresponding to each domain segment is determined sequentially until the selection result of the highest bit domain segment is obtained. Among them, the selection result of the other domain segments except the first domain segment is one of the true value result and the pseudo value result of the corresponding domain segment. Based on the selection results of each domain segment, the floating-point processing result corresponding to the target task is determined.

9. The method according to claim 8, characterized in that, The determination of the floating-point processing result corresponding to the target task based on the selection results of each domain segment includes: The selection results of each domain segment are concatenated in descending order of bit height to obtain the floating-point processing result corresponding to the target task.

10. The method according to claim 1, characterized in that, The method further includes: The floating-point number processing result is normalized to make it conform to a preset floating-point number standard.

11. The method according to claim 10, characterized in that, The normalization process for the floating-point number processing result includes: Determine the first symbol identifier and the second symbol identifier in the floating-point number processing result; If the first symbol identifier is the same as the second symbol identifier, then the mantissa value in the floating-point number processing result is shifted according to the first shift direction; If the first symbol identifier is different from the second symbol identifier, then the mantissa value in the floating-point number processing result is shifted according to the second shift direction; wherein the second shift direction is opposite to the first shift direction.

12. The method according to any one of claims 1 to 11, characterized in that, The target task is a subtask within a neural network processing task, wherein the neural network task includes at least one of a convolution processing task and a similarity processing task, and the method further includes: Based on the floating-point number processing result, the subsequent subtasks in the neural network processing task are executed to obtain the neural network processing result.

13. A multi-input floating-point processing device, characterized in that, The device includes: The acquisition module is used to acquire multiple floating-point numbers to be processed corresponding to the target task, and extract the exponent value of the exponent part and the mantissa value of the mantissa part of each floating-point number respectively. An allocation module is used to sort multiple floating-point numbers according to the magnitude of the exponent value of each floating-point number, and allocate a corresponding shifter to each floating-point number from multiple shifters with different preset bit lengths based on the sorting result. The number of multiple shifters is the same as the number of multiple floating-point numbers. The module includes: determining the sorting number corresponding to each floating-point number in the sorting result; determining the preset bit length corresponding to each sorting number according to the preset bit length set in advance for each sorting number; and allocating the multiple shifters to the floating-point numbers specified by the sorting numbers corresponding to the preset bit lengths, wherein the tail values ​​of the later sorted values ​​are effectively shifted, and the tail values ​​of the earlier sorted values ​​have a smaller shift range. The shift module is used to shift the mantissa of each floating-point number by means of a shifter corresponding to the floating-point number, so as to obtain the shift result. The determination module is used to determine the floating-point processing result corresponding to the target task based on each of the shift results.

14. The apparatus according to claim 13, characterized in that, The different preset number of bits of the multiple shifters are within a first preset range, and the preset number of bits of each shifter is evenly distributed within the first preset range.

15. The apparatus according to claim 13, characterized in that, The shift module is also used to determine the number of shift bits corresponding to the mantissa of each floating-point number based on the difference between the exponent values ​​of each floating-point number and the maximum exponent value, wherein the maximum exponent value is the maximum value among the exponent values ​​of multiple floating-point numbers; for each floating-point number, the corresponding mantissa value is shifted based on the number of shift bits corresponding to the mantissa value of the corresponding floating-point number through the shifter allocated to the floating-point number to obtain the shift result.

16. The apparatus according to claim 15, characterized in that, The shift module is further configured to, for each floating-point number, determine whether the number of shift bits corresponding to the mantissa of the floating-point number is within the shift range corresponding to the preset number of bits of the shifter allocated to the floating-point number; if the number of shift bits is within the shift range, then, through the shifter allocated to the floating-point number, each mantissa member constituting the mantissa in the floating-point number is shifted in the same shift direction within the corresponding shift range; wherein, the shift direction includes left shift or right shift; if the number of shift bits is outside the shift range, then, through the shifter allocated to the floating-point number, each mantissa member constituting the mantissa in the floating-point number is shifted in the same shift direction by the preset number of bits; the mantissa obtained after shifting each floating-point number is taken as its respective shift result.

17. The apparatus according to claim 13, characterized in that, The determining module further includes a compression unit, which is used to divide the shifters of different preset bit lengths into multiple domain segments based on a first preset range, and determine compressors corresponding to the multiple domain segments respectively, wherein different compressors have different preset compression ratios; for each domain segment, determine multiple intra-domain shift results within the corresponding domain segment, wherein a single intra-domain shift result is the intra-domain portion of the shift result corresponding to a single floating-point number; through each compressor, perform segmented compression processing on the multiple intra-domain shift results within the domain segment corresponding to the corresponding compressor to obtain multiple segmented compression results; based on the multiple segmented compression results, determine the floating-point number processing result corresponding to the target task.

18. The apparatus according to claim 17, characterized in that, The values ​​of the different preset compression ratios of the multiple compressors are within a second preset range, and the values ​​of the preset compression ratios of each compressor are evenly distributed within the second preset range.

19. The apparatus according to claim 17, characterized in that, The compression unit is also used to take multiple intra-domain shift results within their respective domain segments as inputs to each compressor; each compressor performs segmented compression processing on its own input according to its own preset compression ratio to obtain the local result and the carry result, and the local result and the carry result constitute the segmented compression result corresponding to the segmenter.

20. The apparatus according to claim 17, characterized in that, The determining module further includes an addition unit, which is used to select a first domain segment (which has not undergone compression and corresponds to only a single intra-domain shift result) as the selection result of the first domain segment from among the multiple domain segments obtained by division; to select a second domain segment (which has not undergone compression and corresponds to more than one intra-domain shift result) based on the more than one intra-domain shift result within the second domain segment; to select a third domain segment (which has undergone compression) based on the segmented compression result corresponding to each third domain segment; to select a third domain segment (which has undergone compression) according to the segment height, starting from the lowest bit segment, and sequentially determining the selection result corresponding to each segment until the highest bit segment is obtained, wherein the selection result of the other segments besides the first domain segment is one of the true value result and the pseudo value result of the corresponding segment; and to determine the floating-point processing result corresponding to the target task based on the selection results of each segment.

21. The apparatus according to claim 20, characterized in that, The determining module further includes a splicing unit, which is used to splice the selection results of each domain segment in order of the bit height of each domain segment to obtain the floating-point processing result corresponding to the target task.

22. The apparatus according to claim 13, characterized in that, The device further includes: The post-processing module is used to normalize the floating-point number processing result so that the floating-point number processing result conforms to the preset floating-point number standard.

23. The apparatus according to claim 22, characterized in that, The post-processing module is further configured to determine a first symbol identifier and a second symbol identifier in the floating-point number processing result; if the first symbol identifier is the same as the second symbol identifier, then the mantissa value in the floating-point number processing result is shifted according to a first shift direction; If the first symbol identifier is different from the second symbol identifier, then the mantissa value in the floating-point number processing result is shifted according to the second shift direction; wherein the second shift direction is opposite to the first shift direction.

24. The apparatus according to any one of claims 13 to 23, characterized in that, The target task is a subtask within a neural network processing task, and the neural network task includes at least one of a convolution processing task and a similarity processing task. The apparatus further includes: Based on the floating-point number processing result, the subsequent subtasks in the neural network processing task are executed to obtain the neural network processing result.

25. A processor, characterized in that, include: At least one shifter with a different preset number of bits is provided, each shifter being assigned to shift the mantissa of one of a plurality of floating-point numbers to be processed; wherein the shifter assigned to each floating-point number is determined by a sorting result obtained by sorting the exponents of the exponents of each floating-point number, and the number of shifters is the same as the number of floating-point numbers, including: determining the sorting number corresponding to each floating-point number in the sorting result; determining the preset number of bits corresponding to each sorting number according to the preset number of bits preset for each sorting number, and assigning the plurality of shifters to the floating-point numbers specified by the sorting numbers corresponding to the preset number of bits, wherein the mantissas of later sorted numbers are effectively shifted, and the mantissas of earlier sorted numbers have a smaller shift range; The logic processing unit is used to perform logical processing on the multiple shift results obtained by each of the shifters to obtain floating-point processing results.

26. The processor according to claim 25, characterized in that, The different preset number of bits of the at least one shifter are within a first preset range, and the preset number of bits of each shifter are evenly distributed within the first preset range.

27. The processor according to claim 25, characterized in that, The logic processing unit includes: At least one compressor with a different preset compression ratio is connected to the shifter, and each compressor is assigned to perform segmented compression processing on multiple shift results obtained by the shifting process to obtain segmented compression results. At least one adder, connected to the compressor, is used to generate true and pseudo results for multiple domain segments based on the segmented compression result. At least one selector, connected to the adder, is used to determine the selection result of each field segment based on the truth value and pseudo-value results of multiple field segments; the selection results are used to concatenate and generate floating-point number processing results.

28. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 12.

29. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 12.

30. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 12.

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