Microcontrol chip and access method

Abstract

A micro control chip and an access method. The micro control chip is coupled with an external memory, and includes a central processing unit, an address corresponding circuit and an address bus. The central processing unit is used to provide an internal address. The address corresponding circuit calculates a unique number and a sub code to generate a base parameter, and performs a disorder operation on the internal address according to the base parameter to generate an encrypted address. The address bus is coupled between the address corresponding circuit and the external memory to provide the encrypted address to the external memory. The external memory stores a specific data according to the encrypted address.

Description

Technical Field

[0001] This invention relates to a microcontroller chip, and more particularly to a microcontroller chip for accessing an external memory. Background Technology

[0002] With the advancement of technology, electronic devices are becoming increasingly diverse in type and function. The code that the microcontrollers within these devices need to execute is also growing larger. However, the internal memory of the microcontroller is insufficient to store this code. Therefore, the microcontroller may store its code in an external memory. Because this external memory is independent of the microcontroller, the code stored there is easily stolen by third parties. Summary of the Invention

[0003] One embodiment of the present invention provides a microcontroller chip coupled to an external memory, and includes a central processing unit (CPU), an address mapping circuit, and an address bus. The CPU provides an internal address. The address mapping circuit calculates a unique identifier and a subcode to generate a base parameter, and performs a scrambling operation on the internal address based on the base parameter to generate an encrypted address. The address bus is coupled between the address mapping circuit and the external memory to provide the encrypted address to the external memory. The external memory stores specific data based on the encrypted address.

[0004] The present invention also provides a microcontroller chip coupled to an external memory, and including an address protection circuit, a data protection circuit, an address bus, and a data bus. The address protection circuit encrypts an internal address to generate an encrypted address. The data protection circuit encrypts internal data to generate encrypted data. The address bus outputs the encrypted address to the external memory. The data bus outputs the encrypted data to the external memory. Attached Figure Description

[0005] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0006] Figure 1 This is a schematic diagram of the access system of the present invention.

[0007] Figure 2 This is another schematic diagram of the access system of the present invention.

[0008] Figure 3 This is another schematic diagram of the access system of the present invention.

[0009] Figure 4 This is a schematic flowchart of the access method of the present invention.

[0010] [Symbol Explanation]

[0011] 100, 200, 300: Access System

[0012] 110, 210, 310: External hosts

[0013] 120, 220, 320: Chips

[0014] 121, 221, 321: Address protection circuits

[0015] 122, 126, 222, 227, 231, 327, 331: Internal memory

[0016] 123, 223: Address correspondence circuit

[0017] 124, 224, 324: Central Processing Unit

[0018] 125, 225, 325: Input / output interfaces

[0019] 140, 240, 340: External memory

[0020] 226: Data Protection Circuit

[0021] 228, 328: Cryptographic circuits

[0022] 229, 329: Encryption circuits

[0023] 230, 330: Decoding circuit

[0024] ADR: Internal Address

[0025] ADR_E, ADR_E1, ADR_E2: Encrypted addresses

[0026] uID: Unique ID

[0027] SD: Seed code

[0028] BP: Basic parameters

[0029] BTC: Activation Code

[0030] ABS: Address Bus

[0031] DBS: Data Bus

[0032] DA: Internal Data

[0033] DAR, DAR1, DAR2: Read data

[0034] DA_E, DA_E1, DA_E2: Encrypted data

[0035] DA_D, DA_D1, DA_D2: Decrypted data

[0036] KY1~KY3: Golden Key

[0037] S411~S414: Steps Detailed Implementation

[0038] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of the devices in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0039] Figure 1 This is a schematic diagram of the access system of the present invention. As shown, the access system 100 includes an external host 110, a chip 120, and an external memory 140. In this embodiment, the external host 110, the microcontroller chip 120, and the external memory 140 are each independently configured. The external host 110 is used to provide firmware to the microcontroller chip 120. In a possible embodiment, the external host 110 is a firmware downloader tool.

[0040] The microcontroller chip 120 includes an address protection circuit 121. The address protection circuit 121 encrypts an internal address ADR to generate an encrypted address ADR_E. This invention does not limit how the address protection circuit 121 encrypts the internal address ADR. In one possible embodiment, the address protection circuit 121 uses an algorithm to calculate a unique ID uID and a seed code SD to generate a basic parameter BP. This invention does not limit how the address protection circuit 121 calculates the unique ID uID and the seed code SD. In one possible embodiment, the address protection circuit 121 performs at least one of a mutual exclusion OR operation, an OR operation, an addition operation, and a subtraction operation on the unique ID uID and the seed code SD. In other embodiments, the unique ID uID is the identification code of the microcontroller chip 120. In some embodiments, the seed code SD is provided by an external host 110.

[0041] In this embodiment, the address protection circuit 121 performs a scrambling operation on the internal address ADR based on the basic parameter BP to generate the encrypted address ADR_E. For example, the internal address ADR might be 0000 1000. After the address protection circuit 121 converts the internal address ADR, the encrypted address ADR_E might be 0000 5000. In this example, the encrypted address ADR_E is different from the internal address ADR.

[0042] This invention does not limit the architecture of the address protection circuit 121. In this embodiment, the address protection circuit 121 includes an internal memory 122 and an address reorder circuit 123. The internal memory 122 is used to store a unique identifier uID and a seed code SD. In some embodiments, the internal memory 122 is a non-volatile memory. The address reorder circuit 123 calculates the unique identifier uID and the seed code SD to generate a basic parameter BP, and converts the internal address ADR according to the basic parameter BP to generate an encrypted address ADR_E.

[0043] In one possible embodiment, the microcontroller 120 further includes a central processing unit 124. The central processing unit 124 provides an internal address ADR to the address mapping circuitry 123. In another possible embodiment, the microcontroller 120 further includes an input / output interface 125. The input / output interface 125 is used to couple to an external host 110. The present invention is not limited to the type of input / output interface 125. In one possible embodiment, the input / output interface 125 is a Universal Serial Bus (USB) interface.

[0044] The central processing unit 124 receives the seed code SD from the external host 110 via the input / output interface 125. In this example, the user may input the seed code SD into the external host 110. The central processing unit 124 stores the seed code SD in the internal memory 122. Since the address mapping circuit 123 encrypts the internal address ADR based on the basic parameter BP, and the basic parameter BP is related to the seed code SD, the user can control the encryption operation by setting the seed code SD, thereby increasing the flexibility of the encryption operation.

[0045] In some embodiments, the microcontroller chip 120 further includes an internal memory 126. The internal memory 126 stores a boot code BTC. When the central processing unit 124 executes the boot code BTC, the central processing unit 124 generates internal data DA. In one possible embodiment, the internal memory 126 is a mask read-only memory (mask ROM). In this example, the boot code BTC is directly written to the internal memory 126 during the fabrication of the microcontroller chip 120 and cannot be altered. In another possible embodiment, the internal memory 126 is a flash memory. In this example, the internal memory 126 stores the boot code BTC provided by an external host 110.

[0046] In other embodiments, the microcontroller chip 120 further includes an address bus ABS and a data bus DBS. The address bus ABS is coupled between the address mapping circuit 123 and the external memory 140, and is used to output the encrypted address ADR_E to the external memory 140. The data bus DBS is coupled between the central processing unit 124 and the external memory 140, and is used to transmit internal data DA to the external memory 140. In one possible embodiment, the internal data DA is provided by the central processing unit 124. In this example, after the central processing unit 124 executes the boot code BTC, it provides the internal data DA to the data bus DBS.

[0047] External memory 140 is independent of microcontroller chip 120 and coupled to address bus ABS and data bus DBS. When external memory 140 receives a write command, it stores internal data DA in the corresponding memory cell according to the address on address bus ABS (e.g., encrypted address ADR_E). When external memory 140 receives a read command, it reads the corresponding memory cell according to the address on address bus ABS (e.g., encrypted address ADR_E) to provide read data DAR. In some embodiments, external memory 140 is a flash memory.

[0048] Since the external memory 140 is independent of the microcontroller chip 120, the data or code stored in the external memory 140 can easily be stolen by a third party. Therefore, the microcontroller chip 120 scrambles the data order, making it difficult for a third party to decipher the data in the external memory 140. In this embodiment, the address protection circuit 121 uses the unique identifier uID of the microcontroller chip 120 and a subcode SD to encrypt the internal address. Since different chips have different identifiers, the address protection circuit 121 on different chips generates different encrypted addresses for the same internal address. External personnel cannot predict the data storage address, thus significantly reducing the chance of successful data theft. In addition, even if an external personnel remove the external memory 140 and connect it to another chip, that chip cannot correctly decrypt (disassembly) the code stored in the external memory 140.

[0049] Figure 2 This is another schematic diagram of the access system of the present invention. The access system 200 includes an external host 210, a microcontroller chip 220, and an external memory 240. Since the characteristics of the external host 210 and the external memory 240 are similar... Figure 1 The characteristics of the external host 110 and external memory 140 will not be described in detail. In this embodiment, the microcontroller chip 220 includes an address protection circuit 221 and a data protection circuit 226. Since the characteristics of the address protection circuit 221 are similar to... Figure 1 The characteristics of the address protection circuit 121 are not described in detail here.

[0050] Data protection circuit 226 is coupled between central processing unit 224 and external memory 240 and operates in an encryption mode or a decryption mode. For example, when data protection circuit 226 receives internal data DA, it enters an encryption mode. In encryption mode, data protection circuit 226 encrypts the internal data DA to generate encrypted data DA_E. This invention does not limit how data protection circuit 226 encrypts internal data DA. In one possible embodiment, data protection circuit 226 performs operations on internal data DA according to a key KY1 to generate encrypted data DA_E.

[0051] In another possible embodiment, when the data protection circuit 226 receives a read data DAR, the data protection circuit 226 enters a decryption mode. In decryption mode, the data protection circuit 226 decrypts the read data DAR to generate decrypted data DA_D. This invention does not limit how the data protection circuit 226 decrypts the read data DAR. In one possible embodiment, the data protection circuit 226 performs calculations on the read data DAR according to the key KY1 to generate decrypted data DA_D.

[0052] This invention does not limit the source of the key KY1. In one possible embodiment, the key KY1 may be provided by the central processing unit 224. After the central processing unit 224 executes the boot code BTC, it can obtain a key KY1 and write the key KY1 into the data protection circuit 226. In another possible embodiment, the key KY1 may be the basic parameter BP. In this example, after the basic parameter BP is generated, the address mapping circuit 123 provides the basic parameter BP to the data protection circuit 226. The data protection circuit 226 uses the basic parameter BP as the key KY1. In other embodiments, the key KY1 may be the same as the unique number uID or the seed code SD.

[0053] External memory 240 receives encrypted address ADR_E via address bus ABS and receives encrypted data DA_E or outputs read data DAR via data bus DBS. For example, when external memory 240 receives a write command, it stores encrypted data DA_E in the corresponding memory cell according to the encrypted address ADR_E. When external memory 240 receives a read command, it reads the read data DAR corresponding to the encrypted address ADR_E and outputs the read data DAR. Since the address and data received by external memory 240 are encrypted, the security of data in external memory 240 can be greatly improved.

[0054] This invention does not limit the architecture of the data protection circuit 226. In this embodiment, the data protection circuit 226 includes an internal memory 227 and a cryptographic circuit 228. The internal memory 227 is used to store the key KY1. The cryptographic circuit 228 is used to perform an encryption operation or a decryption operation. In this embodiment, the cryptographic circuit 228 includes an encryption circuit 229 and a decoding circuit 230. The encryption circuit 229 encrypts the internal data DA to provide encrypted data DA_E. The decryption circuit 230 decrypts the read data DAR to provide decrypted data DA_D.

[0055] In some embodiments, the microcontroller chip 220 further includes an internal memory 232. In this example, when the internal address ADR issued by the central processing unit 224 points to the internal memory 232, the data protection circuit 226 stores the decrypted data DA_D in the internal memory 232. The present invention does not limit the type of internal memory 232. In one possible embodiment, the internal memory 232 is a static random access memory (SRAM).

[0056] In another possible embodiment, the microcontroller chip 220 further includes an internal memory 231. The internal memory 231 is used to store the boot code BTC. In one possible embodiment, the central processing unit 224 receives the boot code BTC from the external host 210 via the input / output interface 225 and stores the boot code BTC in the internal memory 231. In some embodiments, when the central processing unit 224 executes the boot code BTC, the central processing unit 224 generates internal data DA. The present invention does not limit the type of internal memory 231. In one possible embodiment, the internal memory 231 is a non-volatile memory, such as a read-only memory (ROM).

[0057] Figure 3 This is another schematic diagram of the access system of the present invention. The access system 300 includes an external host 310, a microcontroller chip 320, and an external memory 340. Since the characteristics of the external host 310 and the external memory 340 are similar... Figure 1 The characteristics of the external host 110 and external memory 140 are not described in detail here. In this embodiment, the microcontroller chip 320 includes an address protection circuit 321, a central processing unit 324, a data protection circuit 326, an input / output interface 325, and internal memories 331 and 332. Since the characteristics of the address protection circuit 321, the central processing unit 324, the input / output interface 325, and the internal memories 331 and 332 are similar to those of... Figure 2 The characteristics of the address protection circuit 221, central processing unit 224, input / output interface 225, internal memory 231 and 232 are not described in detail here.

[0058] The data protection circuit 326 includes an internal memory 327, a cryptographic circuit 328, and a verification circuit 333. The internal memory 327 stores the key KY1. The cryptographic circuit 328 uses the key KY1 to encrypt the internal data DA, generating encrypted data DA_E1. Due to the characteristics of the cryptographic circuit 328 and... Figure 2 The characteristics of the cryptographic circuit 228 are similar, so they will not be described in detail here.

[0059] To identify whether external memory 340 is a valid memory, internal memory 327 further stores keys KY2 and KY3. Key KY2 represents preset data, and key KY3 represents a preset address. External memory 340 stores key KY2 in the corresponding memory cell based on key KY3. When microcontroller chip 320 prepares to access external memory 340, microcontroller chip 320 first reads the data at the preset address of external memory 340 and determines whether the data at the preset address is the same as key KY2. If yes, it indicates that external memory 340 is a valid memory. Therefore, microcontroller chip 320 continues to access external memory 340. If no, it indicates that external memory 340 is an invalid memory. Therefore, microcontroller chip 320 does not access external memory 340. In one possible embodiment, key KY2 is a signature, and key KY3 is an offset value.

[0060] In some embodiments, address protection circuit 321 encrypts key KY3 to generate encrypted address ADR_E2. In this example, data protection circuit 326 encrypts key KY2 to generate encrypted data DA_E2. External memory 340 stores encrypted data DA_E2 in the corresponding memory cell according to encrypted address ADR_E2. When central processing unit 324 prepares to access external memory 340, address protection circuit 321 reads key KY3 to generate encrypted address ADR_E2. External memory 340 outputs read data DAR2 corresponding to encrypted address ADR_E2. Data protection circuit 326 decrypts read data DAR2 to generate decrypted data DA_D2. Data protection circuit 326 determines whether decrypted data DA_D2 is the same as key KY2. If yes, it indicates that external memory 340 is a valid memory. Therefore, central processing unit 324 begins to access external memory 340. If no, it indicates that external memory 340 is an invalid memory. Therefore, the central processing unit 324 does not access the external memory 340.

[0061] In this embodiment, the data protection circuit 326 further includes a verification circuit 333. The verification circuit 333 determines whether the decrypted data DA_D2 is the same as the key KY2. If yes, the verification circuit 333 writes a first preset value into a specific storage unit of the internal memory 331. If no, the verification circuit 333 writes a second preset value into the specific storage unit of the internal memory 331. The central processing unit 324 determines whether the external memory 340 is a legitimate memory based on the data (first or second preset value) stored in the specific storage unit of the internal memory 331.

[0062] When external memory 340 is a valid memory, CPU 324 may enter a write mode. In write mode, CPU 324 issues an internal address ADR (or write address). Address protection circuit 321 encrypts the internal address ADR to generate an encrypted address ADR_E1. At this time, CPU 324 outputs internal data DA (or write data). Data protection circuit 326 encrypts the internal data DA to generate encrypted data DA_E1. External memory 340 stores internal data DA according to the encrypted address ADR_E1. When CPU 324 enters a read mode, CPU 324 issues an internal address ADR (or read address). Address protection circuit 321 encrypts the internal address ADR to generate an encrypted address ADR_E1. External memory 340 reads the read data DAR1 corresponding to the encrypted address ADR_E1. Data protection circuit 326 decrypts and reads data DAR1 to generate decrypted data DA_D1, and provides decrypted data DA_D1 to at least one of internal memory 332 and central processing unit 324.

[0063] Figure 4 This is a schematic flowchart of the access method of the present invention. The access method of the present invention is applicable to a microcontroller chip for accessing an external memory. In this embodiment, the external memory is independent of the microcontroller chip. In a possible embodiment, the microcontroller chip may be... Figure 1 Microcontroller chip 120 Figure 2 Microcontroller chip 220, or Figure 3 The microcontroller chip 320. First, read the unique serial number of the microcontroller chip (step S411). Figure 1 For example, the central processing unit 124 may store the unique number of the microcontroller chip 120 in the internal memory 122.

[0064] Next, a unique identifier and a sub-code are calculated to generate a basic parameter (step S412). Figure 1 For example, an address mapping circuit (such as 123) substitutes a unique number and a seed code into an arithmetic expression to generate a basic parameter BP. In one possible embodiment, the arithmetic expression may include at least one of a mutual exclusion OR operation, an OR operation, an addition operation, and a subtraction operation.

[0065] Based on the basic parameters, a shuffling operation is performed on multiple internal addresses to generate multiple encrypted addresses (step S413). Figure 1For example, an address mapping circuit (such as 123) adjusts an internal address ADR to generate an encrypted address ADR_E. In one possible embodiment, the address mapping circuit 123 substitutes the basic parameter BP and the internal address ADR into another expression. In this example, the result of the operation between the basic parameter BP and the internal address ADR is used as the encrypted address ADR_E. In some embodiments, the address mapping circuit 123 records the correspondence between these internal addresses and these encrypted addresses. Therefore, when the address mapping circuit 123 receives an internal address ADR, it can use a lookup table to find the corresponding encrypted address. The address mapping circuit 123 does not need to recalculate the basic parameter BP and the internal address ADR.

[0066] Based on multiple encrypted addresses, multiple specific data items are written to the external memory (step S414). In one possible embodiment, the microcontroller chip has an address bus and a data bus. The external memory receives encrypted addresses through the address bus and specific data through the data bus. In this example, the external memory stores the specific data in the corresponding memory cell according to the encrypted address.

[0067] In other embodiments, the microcontroller further stores a boot code. In this example, the microcontroller executes the boot code to generate a seed code. The invention does not limit the source of the boot code. In one possible embodiment, the boot code is provided by an external host. In this example, the microcontroller may have an input / output interface for coupling to the external host. The external host is independent of the microcontroller.

[0068] In some embodiments, the specific data is encrypted before being output to external memory. For example, the microcontroller uses a first key to encrypt first internal data to generate the specific data. In this example, when the microcontroller reads data stored in external memory, it first uses the first key to decrypt the data stored in external memory to generate second internal data. The microcontroller then stores the second internal data in internal memory. This internal memory may be a static random access memory (SRAM).

[0069] In another possible embodiment, the microcontroller chip further stores a second key and a third key. Based on the basic parameters, the microcontroller chip performs the scrambling operation on the third key to generate a write address. The external memory stores the second key in the corresponding memory cell based on this write address. In this example, since the microcontroller chip does not encrypt the second key, it does not need to decrypt the second key stored in the external memory when reading it. The microcontroller chip determines whether the second key stored in the external memory is the same as the second key stored within the microcontroller chip itself. If yes, the external memory is a valid memory. If no, the external memory is an invalid memory. Therefore, the microcontroller chip may temporarily suspend access to the external memory.

[0070] In another possible embodiment, the microcontroller encrypts a second key to generate an encryption key. In this example, the external memory stores the encryption key in the corresponding memory cell according to the write address. When the external memory receives a read instruction and the write address, it outputs the encryption key. The microcontroller decrypts the encryption key to generate a decryption result. The microcontroller compares the decryption result with the second key. If the decryption result is the same as the third key, it indicates that the external memory is a valid memory. Therefore, the microcontroller continues to access the external memory. If the decryption result is different from the second key, it indicates that the external memory is an invalid memory. Therefore, the microcontroller stops accessing the external memory. In one possible embodiment, the second key is one of a unique identifier and a seed code, and the third key is the other of a unique identifier and a seed code.

[0071] It is important to understand that when a device or layer is mentioned as being "coupled" to another device or layer, it can be directly coupled or connected to the other device or layer, or there can be other devices or layers between them. Conversely, if a device or layer is "connected" to another device or layer, there will be no other devices or layers between them.

[0072] The access method, or a specific form or part thereof, of the present invention can exist in the form of code. The code can be stored on physical media, such as floppy disks, optical disks, hard disks, or any other machine-readable (e.g., computer-readable) storage media, and is not limited to external computer program products. When the code is loaded and executed by a machine, such as a computer, that machine becomes a microcontroller chip participating in the present invention. The code can also be transmitted via some transmission medium, such as wires or cables, optical fibers, or any transmission method. When the code is received, loaded, and executed by a machine, such as a computer, that machine becomes a microcontroller chip participating in the present invention. When implemented in a general-purpose processing unit, the code, combined with the processing unit, provides a unique device that operates similarly to an application-specific logic circuit.

[0073] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by those skilled in the art. Furthermore, unless expressly stated otherwise, definitions of terms in general dictionaries should be interpreted as consistent with their meaning in the context of their relevant technical field, and not as idealized or overly formal expressions. While terms such as "first," "second," etc., may be used to describe various devices, these devices should not be limited by these terms. These terms are merely used to distinguish one device from another.

[0074] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the preceding claims.

Claims

1. A microcontroller chip coupled to an external memory, characterized in that, include: A central processing unit, used to provide a first internal address; An address-to-circuit is used to calculate a unique number and a sub-code to generate a basic parameter, and to perform a scrambling operation on the first internal address based on the basic parameter to generate a first encrypted address. as well as An address bus, coupled between the address-corresponding circuit and the external memory, is used to provide the first encrypted address to the external memory; The external memory stores specific data according to the first encrypted address.

2. The microcontroller chip according to claim 1, characterized in that, Also includes: A first internal memory for storing a boot code, wherein the central processing unit executes the boot code to generate the seed code.

3. The microcontroller chip according to claim 1, characterized in that, Also includes: A data bus, coupled between the central processing unit and the external memory, is used to provide the specific data to the external memory.

4. The microcontroller chip according to claim 3, characterized in that, Also includes: A data protection circuit is coupled between the central processing unit and the data bus and operates in an encryption mode or a decryption mode.

5. The microcontroller chip according to claim 4, characterized in that, When the central processing unit provides first internal data, the data protection circuit enters the encryption mode. In the encryption mode, the data protection circuit encrypts the first internal data to generate the specific data, and outputs the specific data to the external memory through the data bus.

6. The microcontroller chip according to claim 5, characterized in that, When the external memory provides read data, the data protection circuit enters the decryption mode. In the decryption mode, the data protection circuit decrypts the read data to generate a second internal data for the central processing unit.

7. The microcontroller chip according to claim 6, characterized in that, The data protection circuit includes: A second internal memory, storing a first gold key; A cryptographic circuit processes the first key and the first internal data to generate the specific data, and processes the first key and the read data to generate the second internal data.

8. An access method applicable to a microcontroller chip, said microcontroller chip being coupled to an external memory, characterized in that, The access method includes: Read a unique serial number of the microcontroller chip; Calculate the unique number and a sub-code to generate a basic parameter; Based on the aforementioned basic parameters, a shuffling operation is performed on multiple internal addresses to generate multiple encrypted addresses; and Based on the multiple encrypted addresses, write multiple specific data to the external memory; The external memory is independent of the microcontroller chip.

9. A microcontroller chip coupled to an external memory, characterized in that, include: An address protection circuit encrypts an internal address to generate an encrypted address; A data protection circuit encrypts internal data to generate encrypted data; An address bus is provided for outputting the encrypted address to the external memory. as well as A data bus for outputting the encrypted data to the external memory; The address protection circuit calculates a unique number and a sub-code to generate a basic parameter, and performs a scrambling operation on the internal address based on the basic parameter to generate the encrypted address.

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