A testability design method for a processor on a chip

Abstract

This invention discloses a testable design method for an on-chip processor, comprising: dividing the chip into different cores according to its structure, obtaining key features of different cores, and setting the number of inserted scan chains and the type of test controller; decompressing and compressing the scan chains in the cores based on a timing compression architecture, thereby increasing the number of scan chains and reducing their length in actual testing of each core, thus achieving a shorter test time; inserting a data selection circuit into the SoC layer to connect the various cores and control them through a top-level controller, thereby enabling different cores to be tested under different states, improving test efficiency; and finally, inserting a boundary scan chain into the SoC layer to test the chip's signal input and output capabilities. This invention, by dividing the chip into cores, compressing the number of scan chains in the cores, and controlling different cores to be tested separately through data selectors and controllers, significantly shortens the chip testing time compared to existing technologies.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit testability design technology. Background Technology

[0002] As integrated circuit process dimensions continue to shrink and chip complexity increases, the integrated circuit industry places higher demands on chip testing. Therefore, Design for Test (DFT), an indispensable part of chip testing technology, also faces greater challenges. Chip testability technology primarily aims to test for physical defects that may arise during chip manufacturing, leading to functional failures (such as fixed failures or transient failures). A key technology involves replacing registers in the circuit with scan registers, using scan enable signals to control each scan register to be in the shift or capture phase for chip scanning tests. For large-scale systems-on-a-chip (SoCs), chips are more modular and complex. The traditional method of inserting scan chains into the entire chip and then deriving test vectors using automatic test vector generation tools significantly reduces the testing efficiency of DFT tools and prolongs testing time. Developing modular test schemes for large SoCs can optimize the testing process. By compressing the scan chain through a timing compression architecture, testing efficiency can be improved and testing time optimized. Summary of the Invention

[0003] Purpose of the invention: To address the problems of limited test architecture, long scan test time, and low efficiency in the existing chip testability design process for large-scale on-chip systems, this invention provides a chip testability design method for SoCs. It optimizes previous technologies in terms of test architecture, test efficiency, and test time. It can not only divide the on-chip system structure into reasonable test logic, but also improve the efficiency of chip testing and reduce test time by using a timing-compressed logic architecture.

[0004] Technical Solution: A testable design method for an on-chip processor, comprising: dividing the chip into different cores according to the chip structure; setting the number of scan chains for scan testing and the input / output ports of the scan chains according to the key features of different cores, and setting the type of test controller; for each core, inserting scan chains according to the set number of scan chains, and performing decompression and compression of the scan chains based on a timing compression architecture; inserting a top-level controller at the SoC layer, and inserting a data selection circuit between the top-level controller and the core for test selection; inserting a boundary scan chain at the SoC layer, testing the chip input / output ports and controlling the controller.

[0005] Furthermore, the key features include: the number of sequential logic units within the kernel, the number and specific functions of clock signals and reset signals; the test controller is used to put the kernel into different types of test modes through control signal terminals, the test modes including wrp_if, wrp_of, and scan.

[0006] Furthermore, the decompression and compression of the scan chain based on a time-series compression architecture specifically includes:

[0007] a: Set up N scan input channels and 1 scan output channel. Decompress the inserted scan chain through a timing compression architecture to M scan chains, where M>N. Then, use the scan chain balancing function of the DTF tool to allocate the number of registers on each chain.

[0008] During decompression, a pseudo-random linear XOR function is established based on the input seed value to decompress a single-bit signal into a multi-bit pseudo-random data stream, obtaining the decompression result of the scan chain. This process is controlled by a clock signal in compression mode. The decompression structure in the timing compression architecture consists of PRPG Shadow, PRPG, Care PRPG, CARE Shadow, and CARE phase-shifter. PRPG generates a linear XOR function based on the input seed value. By setting the shift control signal, the seed value is loaded into PRPG and shifted through one or more scan registers. After PRPG loading is complete and the shift control signal is released, PRPG generates a pseudo-random sequence. Care PRPG generates a pseudo-random sequence corresponding to the fault model for the specific fault type, with its input seed value being the data provided by the ATPG tool based on the fault type. PRPG continues to drive CARE Shadow, a register used when the ATPG tool is in low-power mode to keep the scan data unchanged during the shift phase. CARE Shadow drives CARE phase-shifter. The phase-shifter consists of multiple XOR gates and is used to widen the bit width of the data stream generated by PRPG;

[0009] b: The decompressed M scan links are input into the timing compression architecture for compression, so that only one scan output channel is used; the timing compression architecture is based on MISR, which compresses multi-bit data into one-bit data output through multiple XOR logics;

[0010] c: Synthesize the configured kernel scan chain architecture.

[0011] Furthermore, the multi-bit shift register used in the decompression step needs to break the Q-end based on the number of scan output ports, and insert OR logic on each Q-end to D-end path. The inputs are respectively from the Q-end value of the previous bit and the local input value obtained by the XOR decompression logic in the decompressor. When the shift signal Shift is set to 1, the capure stage is entered, and when the Shift signal is set to 0, the shift stage is entered, thereby further compressing the scan output path.

[0012] Furthermore, a top-level controller is inserted at the SoC layer, and a data selection circuit is inserted between the top-level controller and the core for test selection, specifically including the following steps:

[0013] a: The test of each core is controlled by the data selection circuit. The input signal of the data selection circuit is encoded accordingly, and different cores are selected. The scan enable signal is input to test the selected core.

[0014] b: Connect the output of the data selection circuit to the top server of the chip's top controller, select the kernel to be tested, and then control the test mode port of the 1687 IP in the kernel.

[0015] Furthermore, boundary scan registers are inserted into the input / output ports at the top layer of the chip and connected in series to form the boundary scan chain for functional testing of the input / output pins.

[0016] Beneficial Effects: This invention divides the chip into cores based on the overall system-on-a-chip (SoC) architecture, identifying different test areas and setting targeted test modes, scan chain architectures, and controller types according to the characteristics of each core. For each relatively independent SoC core, the scan chain architecture and specific test details are determined based on its internal clock, number and function of reset signals, and number of internal sequential logic units. A novel scan chain compression method based on a timing compression architecture is used, thereby improving test efficiency, significantly shortening test time, and saving scan input / output port resources. This invention also designs data selectors and corresponding top-level controllers for controlling different cores, rationally controlling the test sequence, improving test efficiency, and avoiding redundant testing. Finally, this invention inserts boundary scan chains for the SoC's communication ports to ensure the rationality and integrity of the test method. The feasibility of this invention is ensured through test vector generation and simulation. Attached Figure Description

[0017] Figure 1 This is a flowchart of the method of the present invention;

[0018] Figure 2 This is a diagram illustrating the design architecture for system-on-chip testability in an embodiment of the present invention.

[0019] Figure 3 This is a diagram of the compressor structure under the temporal compression architecture used in the method of the present invention;

[0020] Figure 4 This is a circuit diagram of the PRPG register used in the method of the present invention;

[0021] Figure 5 This is a circuit diagram of the multi-bit shift register used in the method of this invention;

[0022] Figure 6 This refers to the test coverage results in this embodiment of the invention. Detailed Implementation

[0023] The present invention will now be described in further detail with reference to the embodiments and accompanying drawings.

[0024] like Figure 1 As shown, a testable design method for an on-chip processor includes the following steps:

[0025] Step 1: Divide the chip into different cores, such as core 0, core 1, etc., according to the chip structure.

[0026] Step 2: Based on the key features of different kernels, set the number of scan chains to be inserted for scan testing and the scan chain input / output ports, and set the type of test controller.

[0027] In this implementation, the on-chip processor test circuit architecture is as follows: Figure 2 As shown, the entire chip is divided into two cores, core0 and core1. For each core, its original functional clock signal func_clk is defined as the fast clock fase_clk, and a slow clock signal ate_clk is created for ATE (Automatic Test Equipment) testing, while retaining its original reset control signal. A timing compression architecture is applied to both cores, with Coedc in the diagram representing the compression control section. 1687 IPs are inserted into core0 and core1 respectively as controllers for controlling core-level test modes. At the top level, the two 1687 controllers are unified through a top server, serving as the top-level controller to control the test sequence and test mode for each core. Simultaneously, a top-level port access controller (TAP Controller) is configured to control the input / output ports at the entire chip boundary for boundary testing.

[0028] Specifically, based on the different chip cores, and according to the number of sequential logic units, the number of clock signals, and the specific functions of reset signals, different clock and reset signals are allocated for different test modes. For wpr_if, wpr_of, and scan modes, fast_clk is used as the capture clock for its capture behavior, and ate_clk is used as the shift clock for its shift behavior. For compression modes, a separate clock is created and used to control the compressor / decompressor; the reset signal can directly use the original chip's reset signal. Since each core in this embodiment contains approximately 120,000 registers, 180 compressed scan chains are required to ensure that each scan chain is neither too short nor too long. To conserve input / output scan ports as much as possible, 15 scan input ports are set. For scan output ports, since the sequential compression architecture of this invention allows for multi-bit data input and single-bit data output through multi-bit shift registers, only one scan output port is needed.

[0029] Step 3: Configure the chip's test mode, including:

[0030] Step 3-1: Based on the 15 scan input channels and 1 scan output channel set in this embodiment, the input scan chain is decompressed through a timing compression architecture to 180 scan chains. The number of registers on each chain is allocated through the scan chain balancing function of the DTF tool, so that the overall register shift time is reasonably shortened.

[0031] The temporal compression architecture used in this invention is specifically as follows: Figure 3 As shown, during the decompression process, a pseudo-random linear XOR function is established at the input seed to decompress a one-bit signal into a multi-bit pseudo-random data stream, obtaining the decompression result of the input scan chain. This process is controlled by the clock signal in compression mode. The decompressor in the timing compression architecture consists of PRPG Shadow, PRPG, Care PRPG, CARE Shadow, and CARE phase-shifter. Among them, PRPG (Pseudo Randompatten Generation) is used to generate a linear XOR function based on the existing data word (i.e., the seed value) of the input. Its internal structure is as follows. Figure 4As shown. By setting the shift control signal, the seed (i.e., the first input data) is loaded into the PRPG and shifted through one or more scan registers. When the PRPG loading is complete and the shift control signal is released, the PRPG generates a string of data, which is in the form of a random sequence, but is actually a function of the input seed value. Each seed value generates a corresponding pseudo-random sequence after being input into the PRPG. The CARE PRPG is used to generate pseudo-random sequences corresponding to fault models of specific fault types, so its input seed value is the data provided by the ATPG tool according to the fault type. The CARE PRPG continues to drive the CARE Shadow. CAREShadow is a register used when the ATPG tool is in low-power mode. This register keeps the scan data unchanged during the shifting phase, thus not interfering with the CARE PRPG. The CARE Shadow register drives the CARE phase-shifter (combinatorial decompression logic), which consists of multiple XOR gates to widen the number of bits in the data stream generated by the PRPG, thus allowing it to continue driving a large number of scan chains.

[0032] In the decompression step, the multi-bit shift register used needs to break the Q-end based on the number of scan output ports, and insert OR logic on each Q-end to D-end path. The inputs are respectively from the Q-end value of the previous bit and the local input value obtained by the XOR decompression logic in the decompressor. When the shift signal Shift is set to 1, the capure stage is entered, and when the shift signal is set to 0, the shift stage is entered, thereby further compressing the scan output path.

[0033] Step 3-2: Input the decompressed 150 scan links into the timing compression architecture for compression, so that only one scan output channel is used. This design uses a timing compression architecture based on MISR (Multi-Bit Shift Register), which compresses multi-bit data into a single bit output through multiple XOR logic operations, thus greatly saving the resources occupied by the scan output signal. The structure of the multi-bit shift register is as follows: Figure 5 .

[0034] Step 3-3: Synthesize the configured in-core scan chain architecture.

[0035] Steps 3-4: Derive the corresponding test vectors through automatic test vector generation, apply them to the synthesized circuit, and perform simulation verification.

[0036] Step 4: Insert the top-level controller at the SoC layer, and insert a data selection circuit between the top-level controller and the core for test selection. This includes the following steps:

[0037] Step 4-1: At the top level of the system-on-chip, multiplexers are applied to the circuit to unify the various cores, control the testing of each core, encode the input signals of the multiplexers accordingly, select different cores, and input scan enable signals to test the selected cores.

[0038] Furthermore, the input control signals of the chip's top-level selection controller, as well as the overall test mode control signals of the chip, are uniformly controlled through the top-level controller (top server). The input signals of the data selection circuit are connected to the top-level chip's controller (top server), and the mode selection port in the top server controls the input code sequence of the data selection circuit, as well as other test modes.

[0039] Step 4-2: Connect the output of the data selection circuit to the top server of the chip's top layer controller, select the core to be tested, and then control the test mode port of the 1687 IP in the core.

[0040] Step 5: Insert a boundary scan chain on the top layer of the chip to synthesize and simulate the overall test circuit.

[0041] Step 5-1: Insert boundary scan registers into the top-level input / output ports of the chip and connect them in series to form a boundary scan chain. This is used for functional testing of input / output pins and to control the calibration controller, thereby improving the completeness and effectiveness of the chip testing method.

[0042] Step 5-2: Integrate the entire on-chip system of the insertion scan chain, controller, and boundary scan chain.

[0043] Step 5-3: Derive the corresponding test vectors using an automatic test vector generation tool and apply them to the top layer of the on-chip system for simulation verification. The overall test coverage under this method is obtained as follows: 98.49% under the fixed fault model and 84.56% under the transmission fault model. Figure 6 As shown.

Claims

1. A testable design method for an on-chip processor, characterized in that, include: Based on the chip architecture, different cores are divided. According to the key characteristics of each core, the number of scan chains inserted for scan testing and the scan chain input / output ports are set, along with the type of test controller. For each core, a scan chain is inserted according to the set number of scan chains, and the scan chains are decompressed and compressed based on a timing compression architecture. A top-level controller is inserted at the SoC layer, and a data selection circuit is inserted between the top-level controller and the core for test selection. Boundary scan chains are inserted at the SoC layer to test the chip's input / output ports and control the top-level controller. The decompression and compression of the scan chain based on a time-series compression architecture specifically includes: a: Set up N scan input channels and 1 scan output channel. Decompress the inserted scan chain through a timing compression architecture to M scan chains, where M>N. Then, use the scan chain balancing function of the DTF tool to allocate the number of registers on each chain. During decompression, a pseudo-random linear XOR function is established based on the input seed value to decompress a single-bit signal into a multi-bit pseudo-random data stream, obtaining the decompression result of the scan chain. This process is controlled by a clock signal in compression mode. The decompression structure in the timing compression architecture consists of PRPG Shadow, PRPG, Care PRPG, CAREShadow, and CARE phase-shifter. PRPG generates a linear XOR function based on the input seed value. By setting the shift control signal, the seed value is loaded into PRPG and shifted through one or more scan registers. After PRPG loading is complete and the shift control signal is released, PRPG generates a pseudo-random sequence. Care PRPG generates a pseudo-random sequence corresponding to the fault model for the specific fault type, with its input seed value being the data provided by the ATPG tool based on the fault type. PRPG continues to drive CARE Shadow, a register used when the ATPG tool is in low-power mode to keep the scan data unchanged during the shift phase. CAREShadow drives CARE phase-shifter. The phase-shifter consists of multiple XOR gates and is used to widen the bit width of the data stream generated by PRPG; b: The decompressed M scan links are input into the timing compression architecture for compression, so that only one scan output channel is used; the timing compression architecture is based on MISR, which compresses multi-bit data into one-bit data output through multiple XOR logics; c: Synthesize the configured kernel scan chain architecture.

2. The testable design method for an on-chip processor according to claim 1, characterized in that, The key features include: the number of sequential logic units within the kernel, the number and specific functions of clock signals and reset signals; the test controller is used to put the kernel into different types of test modes through control signal terminals, the test modes including wrp_if, wrp_of, and scan.

3. The testable design method for an on-chip processor according to claim 1, characterized in that, The multi-bit shift register used in the compression step needs to break the Q-end based on the number of scan output ports, and insert OR logic on each Q-end to D-end path. The inputs are respectively from the Q-end value of the previous bit and the local input value obtained by the XOR decompression logic in the decompressor. When the shift signal Shift is set to 1, the capure stage is entered, and when the Shift signal is set to 0, the shift stage is entered, thereby further compressing the scan output path.

4. The testable design method for an on-chip processor according to claim 1, characterized in that, Inserting a top-level controller at the SoC layer and then inserting a data selection circuit between the top-level controller and the core for test selection involves the following steps: a: The test of each core is controlled by the data selection circuit. The input signal of the data selection circuit is encoded accordingly, and different cores are selected. The scan enable signal is input to test the selected core. b: Connect the output of the data selection circuit to the top server of the chip's top controller, select the kernel to be tested, and then control the test mode port of the 1687 IP in the kernel.

5. The testable design method for an on-chip processor according to claim 1, characterized in that, Boundary scan registers are inserted into the input / output ports at the top layer of the chip and connected in series to form the boundary scan chain, which is used for functional testing of the input / output pins.

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