Display device

Abstract

A display device according to an exemplary embodiment of the present disclosure can include a lower substrate capable of being stretched, a lower pattern layer disposed on the lower substrate and including a plurality of lower plate patterns and a plurality of lower line patterns, a plurality of pixel circuits disposed on each of the plurality of lower plate patterns, a plurality of lower stretch lines disposed on each of the plurality of lower line patterns, an upper pattern layer disposed on the lower pattern layer and including a plurality of upper plate patterns and a plurality of upper line patterns, a plurality of light emitting elements disposed on each of the plurality of upper plate patterns, and a plurality of upper stretch lines disposed on each of the plurality of upper line patterns, so that uniform power can be provided.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a stretchable display device. Background Technology

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include self-emissive organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs) that require a separate light source.

[0003] Such display devices are being used in an increasing number of diverse fields, including not only computer monitors and TVs, but also personal mobile devices, and therefore, research is underway on display devices that have a wide effective area while having a reduced size and weight.

[0004] Recently, display devices that are manufactured to be stretchable in a specific direction and can be changed into various shapes by forming display units, lines, etc. on a flexible substrate (such as plastic as a flexible material) have received considerable attention as the next generation of display devices. Summary of the Invention

[0005] One object of this disclosure is to provide a display device that allows connecting lines to be arranged on different planes.

[0006] Another object of this disclosure is to provide a display device that minimizes the line resistance of a stretched line.

[0007] Another object of this disclosure is to provide a display device in which the connecting line can transmit various signals.

[0008] The purpose of this disclosure is not limited to the above-described purposes, and other purposes will be clearly understood by those skilled in the art from the following description.

[0009] A display device according to an exemplary embodiment of the present disclosure may include: a stretchable lower substrate; a lower patterning layer disposed on the lower substrate and including a plurality of lower plate patterns and a plurality of lower line patterns; a plurality of pixel circuits disposed on each of the plurality of lower plate patterns; a plurality of lower stretch lines disposed on each of the plurality of lower line patterns; an upper patterning layer disposed on the lower patterning layer and including a plurality of upper plate patterns and a plurality of upper line patterns; a plurality of light-emitting elements disposed on each of the plurality of upper plate patterns; and a plurality of upper stretch lines disposed on each of the plurality of upper line patterns, enabling the provision of uniform power.

[0010] Further details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0011] According to this disclosure, a larger gap between the tension lines can be ensured, thereby improving tension reliability.

[0012] According to this disclosure, image uniformity can be achieved by reducing the change in high-potential voltage.

[0013] According to this disclosure, the line resistance of the stretched wire is reduced, which minimizes the signal delay of the gating signal and the data voltage.

[0014] The effects of this disclosure are not limited to those exemplified above, and include a variety of other effects in this specification. Attached Figure Description

[0015] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 This is a plan view of a display device according to an exemplary embodiment of the present disclosure.

[0017] Figure 2 This is an enlarged plan view of the effective area of ​​a display device according to an exemplary embodiment of the present disclosure.

[0018] Figure 3 It is along Figure 2 The cross-sectional view taken by the cutting line III-III' shown.

[0019] Figure 4 It is along Figure 2 The cross-sectional view shown is taken by the cutting line IV-IV'.

[0020] Figure 5 It is along Figure 2 The cross-sectional view shown is taken by the cutting line V-V'.

[0021] Figure 6 This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0022] Figure 7A This is a view illustrating the arrangement relationship between the lower stretched line and the lower unstretched line of a display device according to an exemplary embodiment of the present disclosure.

[0023] Figure 7B This is a view illustrating the arrangement relationship between the upper stretched line and the upper unstretched line of a display device according to an exemplary embodiment of the present disclosure.

[0024] Figure 8 It is along Figure 7A and Figure 7B The cross-sectional view shown is taken by the cutting line VIII-VIII'.

[0025] Figure 9 It is along Figure 7A and Figure 7B The cross-sectional view shown is taken by the cutting line IX-IX'.

[0026] Figure 10A This is a view illustrating the arrangement relationship between the lower stretched line and the lower unstretched line of a display device according to another exemplary embodiment of the present disclosure.

[0027] Figure 10B This is a view illustrating the arrangement relationship between the upper stretched line and the upper unstretched line of a display device according to another exemplary embodiment of the present disclosure.

[0028] Figure 11 It is along Figure 10A and Figure 10B The cross-sectional view shown is taken by the cutting line XI-XI'.

[0029] Figure 12 It is along Figure 10A and Figure 10B The cross-sectional view shown is taken by the cutting line XII-XII'.

[0030] Figure 13A This is a view illustrating the arrangement relationship between the lower stretched line and the lower unstretched line of a display device according to yet another exemplary embodiment of the present disclosure.

[0031] Figure 13B This is a view illustrating the arrangement relationship between the upper stretched line and the upper unstretched line of a display device according to yet another exemplary embodiment of the present disclosure.

[0032] Figure 14 It is along Figure 13A and Figure 13B The cross-sectional view shown is taken by the cutting line XIV-XIV'.

[0033] Figure 15 It is along Figure 13A and Figure 13B The cross-sectional view shown is taken by the cutting line XV-XV'. Detailed Implementation

[0034] The advantages and features of this disclosure, as well as methods for implementing it, will become clearer from the exemplary embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments described below, but can be implemented in various different forms. Exemplary embodiments are provided only to complete the disclosure of this disclosure, and this disclosure is fully provided to those skilled in the art to which the category to which this disclosure pertains belongs, and this disclosure will be defined by the appended claims.

[0035] The shapes, dimensions, ratios, angles, numbers, etc., illustrated in the accompanying drawings to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used only in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0036] Even if not explicitly stated, components are interpreted as including the normal tolerance range.

[0037] When using terms such as “above,” “over,” “below,” and “next” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used in conjunction with the terms “closely to” or “directly.”

[0038] When a component or layer is referred to as being "on" another component or layer, it can be directly on the other component or layer, or there can be an intermediate component or layer.

[0039] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below can be the second component in the technical concept of this disclosure.

[0040] Throughout the specification, the same reference numerals denote the same elements.

[0041] Since the dimensions and thicknesses of each component illustrated in the accompanying drawings are shown for ease of interpretation, this disclosure is not necessarily limited to the dimensions and thicknesses of each illustrated component.

[0042] Features of the various embodiments of this disclosure may be partially or completely linked to or combined with each other, and may be interlocked and operated in various technical ways, and the embodiments may be performed independently of each other or in relation to each other.

[0043] In the following, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0044] The display device according to the exemplary embodiments of this disclosure is a display device capable of displaying images even when bent or stretched, and may also be referred to as a stretchable display device or a flexible display device. The display device can have greater flexibility and stretchability than conventional typical display devices. Therefore, a user can bend or stretch the display device and freely change its shape according to the user's manipulation. For example, when a user grasps and pulls one end of the display device, the display device can be stretched by the user in the pulling direction. If the user places the display device on an uneven outer surface, the display device can be configured to bend according to the shape of the outer surface. When the force applied by the user is removed, the display device can return to its original shape.

[0045] Figure 1 This is a plan view of a display device according to an exemplary embodiment of the present invention.

[0046] Figure 2 This is an enlarged plan view of the effective area of ​​a display device according to an exemplary embodiment of the present disclosure.

[0047] Figure 3 It is along Figure 2 The cross-sectional view taken by the cutting line III-III' shown.

[0048] Specifically, Figure 2 yes Figure 1 The enlarged plan view of region A shown in the figure.

[0049] Reference Figure 1 A display device 100 according to an exemplary embodiment of the present disclosure may include a lower substrate 111, a pattern layer 120, a plurality of pixels PX, a gating driver GD, a data driver DD, and a power supply PS. Furthermore, referring to... Figure 3 The display device 100 according to an exemplary embodiment of the present disclosure may further include a filler layer 190 and an upper substrate 112.

[0050] The lower substrate 111 is a substrate used to support and protect various components of the display device 100. The upper substrate 112 is a substrate used to cover and protect the various components of the display device 100. Specifically, the lower substrate 111 is a substrate supporting the pattern layer 120, on which pixels PX, gating drivers GD, and power supplies PS are formed. Furthermore, the upper substrate 112 is a substrate covering the pixels PX, gating drivers GD, and power supplies PS.

[0051] Each of the lower substrate 111 and the upper substrate 112 is a ductile substrate and may be formed of an insulating material that can be bent or stretched. For example, each of the lower substrate 111 and the upper substrate 112 may be formed of silicone rubber (such as polydimethylsiloxane (PDMS)) or elastomers (such as polyurethane (PU) and polytetrafluoroethylene (PTFE)), and therefore may have flexible properties. In addition, the materials of the lower substrate 111 and the upper substrate 112 may be the same, but are not limited thereto, and may be modified differently.

[0052] Each of the lower substrate 111 and the upper substrate 112 is a ductile substrate and can be reversibly expandable and contractible. Therefore, the lower substrate 111 can be referred to as a lower stretchable substrate, a lower flexible substrate, a lower extendable substrate, a lower stretchable substrate, a first stretchable substrate, a first flexible substrate, a first extendable substrate, or a first stretchable substrate, and the upper substrate 112 can be referred to as an upper stretchable substrate, an upper flexible substrate, an upper extendable substrate, an upper stretchable substrate, a second stretchable substrate, a second flexible substrate, a second extendable substrate, or a second stretchable substrate. Furthermore, the elastic modulus of the lower substrate 111 and the upper substrate 112 can be from a few MPa to several hundred MPa. Furthermore, the ductile failure rate of the lower substrate 111 and the upper substrate 112 can be 100% or higher. Here, the ductile failure rate refers to the elongation at which the object to be stretched is damaged or broken. The thickness of the lower substrate can be from 10 μm to 1 mm, but is not limited to this.

[0053] The lower substrate 111 may have an effective area AA and an ineffective area NA surrounding the effective area AA. However, the effective area AA and the ineffective area NA are not limited to the lower substrate 111 and can be referenced throughout the display device.

[0054] The effective area AA is the area on the display device 100 where an image is displayed. Multiple pixels PX are disposed within the effective area AA. Furthermore, each pixel PX may include a display element and various driving elements for driving the display element. These driving elements may represent at least one thin-film transistor (TFT) and a capacitor, but are not limited thereto. Additionally, each of the multiple pixels PX can be connected to various lines. For example, each of the multiple pixels PX can be connected to various lines such as gate lines, data lines, high-potential voltage lines, low-potential voltage lines, reference lines, and initialization voltage lines.

[0055] The inactive region NA is a region where no image is displayed. The inactive region NA can be a region adjacent to the active region AA. Furthermore, the inactive region NA can be a region adjacent to and surrounding the active region AA. However, this disclosure is not limited to this, and the inactive region NA corresponds to the region of the lower substrate 111 other than the active region AA, and can be changed and separated into various shapes. Components for driving the plurality of pixels PX disposed in the active region AA are disposed in the inactive region NA. A gating driver GD and a power supply PS can be disposed in the inactive region NA. Additionally, a plurality of pads connected to the gating driver GD and the data driver DD can be disposed in the inactive region NA, and each pad can be connected to each of the plurality of pixels PX in the active region AA.

[0056] A pattern layer 120 is provided on the lower substrate 111. The pattern layer 120 includes a plurality of inner plate patterns 121 and a plurality of inner line patterns 122 provided in the effective area AA, and a plurality of outer plate patterns 123 and a plurality of outer line patterns 124 provided in the non-effective area NA.

[0057] Multiple inner board patterns 121 can be disposed in the effective area AA of the lower substrate 111. Multiple pixels PX can be formed on the multiple inner board patterns 121. In addition, multiple outer board patterns 123 can be disposed in the ineffective area NA of the lower substrate 111. Furthermore, a gating driver GD and a power supply PS are formed on the multiple outer board patterns 123.

[0058] The plurality of inner panel patterns 121 and the plurality of outer panel patterns 123 described above can be arranged in the form of islands spaced apart from each other. Each of the plurality of inner panel patterns 121 and the plurality of outer panel patterns 123 can be separated individually. Therefore, the plurality of inner panel patterns 121 and the plurality of outer panel patterns 123 can be referred to as a first island pattern and a second island pattern, or a first individual pattern and a second individual pattern.

[0059] Specifically, the gate driver GD can be mounted on multiple outer board patterns 123. When manufacturing various components on the inner board pattern 121, the gate driver GD can be formed on the outer board pattern 123 according to the panel-in-panel (GIP) method. Therefore, various circuit components constituting the gate driver GD (such as various transistors, capacitors, and wires) can be arranged on multiple outer board patterns 123. However, this disclosure is not limited to this, and the gate driver GD can also be mounted according to the chip-on-film (COF) method.

[0060] Additionally, a power supply PS can be mounted on multiple outer panel patterns 123. The power supply PS can be formed on the outer panel pattern 123 having multiple power blocks, which are patterned when various components on the inner panel pattern 121 are manufactured. Therefore, power blocks disposed on different layers can be disposed on the outer panel pattern 123. That is, lower power blocks and upper power blocks can be sequentially disposed on the outer panel pattern 123. Furthermore, a low potential voltage can be applied to the lower power block, and a high potential voltage can be applied to the upper power block. Therefore, a low potential voltage can be provided to multiple pixels PX through the lower power block. Conversely, a high potential voltage can be provided to multiple pixels PX through the upper power block.

[0061] Reference Figure 1 The size of the plurality of outer board patterns 123 can be larger than the size of the plurality of inner board patterns 121. Specifically, the size of each of the plurality of outer board patterns 123 can be larger than the size of each of the plurality of inner board patterns 121. As described above, a gating driver GD can be disposed on each of the plurality of outer board patterns 123, and a stage of the gating driver GD can be disposed on each of the plurality of outer board patterns 123. Therefore, since the area occupied by the various circuit components constituting a stage of the gating driver GD is relatively larger than the area occupied by the pixel PX, the size of each of the plurality of outer board patterns 123 can be larger than the size of each of the inner board patterns 121.

[0062] exist Figure 1 In this embodiment, multiple outer panel patterns 123 are illustrated as being disposed on both sides in a first direction X within an inactive region NA. However, this disclosure is not limited to this, and the multiple outer panel patterns 123 can be disposed in any region of the inactive region NA. Furthermore, although the multiple inner panel patterns 121 and the multiple outer panel patterns 123 are shown in a quadrilateral shape, this disclosure is not limited to this, and the multiple inner panel patterns 121 and the multiple outer panel patterns 123 can be varied in various forms.

[0063] Reference Figure 1 and Figure 3 The pattern layer 120 may also include a plurality of inner line patterns 122 disposed in the effective area AA and a plurality of outer line patterns 124 disposed in the non-effective area NA.

[0064] Multiple inner line patterns 122 are patterns disposed in the effective area AA and connecting the inner plate patterns 121 adjacent to each other, and can be referred to as inner connecting patterns. That is, multiple inner line patterns 122 are disposed between multiple inner plate patterns 121.

[0065] Multiple outer line patterns 124 can be patterns disposed in the non-active area NA and connecting the inner panel pattern 121 and the outer panel pattern 123 adjacent to each other, or multiple outer panel patterns 123 connecting each other adjacent to each other. Therefore, multiple outer line patterns 124 can be referred to as outer connection patterns. Furthermore, multiple outer line patterns 124 can be disposed between adjacent inner panel patterns 121 and outer panel patterns 123, and can be disposed between multiple adjacent outer panel patterns 123. (Refer to...) Figure 1 The multiple inner line patterns 122 and multiple outer line patterns 124 have a wavy shape. For example, the multiple inner line patterns 122 and multiple outer line patterns 124 can have a sine wave shape. However, the shape of the multiple inner line patterns 122 and multiple outer line patterns 124 is not limited to this. For example, the multiple inner line patterns 122 and multiple outer line patterns 124 can extend in a zigzag manner. Alternatively, the multiple inner line patterns 122 and multiple outer line patterns 124 can have various shapes, such as a shape in which multiple rhomboid substrates extend by connecting at their vertices. Additionally, Figure 1 The number and shape of the plurality of inner line patterns 122 and outer line patterns 124 shown are exemplary, and the number and shape of the plurality of inner line patterns 122 and outer line patterns 124 can be varied according to different designs.

[0066] Furthermore, the plurality of inner plate patterns 121, the plurality of inner line patterns 122, the plurality of outer plate patterns 123, and the plurality of outer line patterns 124 are rigid patterns. That is, compared with the lower substrate 111 and the upper substrate 112, the plurality of inner plate patterns 121, the plurality of inner line patterns 122, the plurality of outer plate patterns 123, and the plurality of outer line patterns 124 can be rigid. Therefore, the elastic modulus of the plurality of inner plate patterns 121, the plurality of inner line patterns 122, the plurality of outer plate patterns 123, and the plurality of outer line patterns 124 can be higher than the elastic modulus of the lower substrate 111. The elastic modulus is a parameter that represents the rate of deformation relative to the stress applied to the substrate. When the elastic modulus is relatively high, the hardness may be relatively high. Therefore, the plurality of inner plate patterns 121, the plurality of inner line patterns 122, the plurality of outer plate patterns 123, and the plurality of outer line patterns 124 can be referred to as a plurality of first rigid patterns, a plurality of second rigid patterns, a plurality of third rigid patterns, and a plurality of fourth rigid patterns, respectively. The elastic modulus of the plurality of inner plate patterns 121, the plurality of inner line patterns 122, the plurality of outer plate patterns 123 and the plurality of outer line patterns 124 may be 1,000 times higher than the elastic modulus of the lower substrate 111 and the upper substrate 112, but this disclosure is not limited thereto.

[0067] The multiple inner plate patterns 121, multiple inner line patterns 122, multiple outer plate patterns 123, and multiple outer line patterns 124, which are multiple rigid substrates, can be formed of a plastic material with lower flexibility than the lower substrate 111 and the upper substrate 112. For example, the multiple inner plate patterns 121, multiple inner line patterns 122, multiple outer plate patterns 123, and multiple outer line patterns 124 can be formed of at least one material selected from polyimide (PI), polyacrylate, and polyacetate. In this case, the multiple inner plate patterns 121, multiple inner line patterns 122, multiple outer plate patterns 123, and multiple outer line patterns 124 can be formed of the same material, but they are not limited to this and can be formed of different materials. When the multiple inner plate patterns 121, multiple inner line patterns 122, multiple outer plate patterns 123, and multiple outer line patterns 124 are formed of the same material, they can be integrally formed.

[0068] In some embodiments, the lower substrate 111 may be defined as including a plurality of first lower patterns and a plurality of second lower patterns. The plurality of first lower patterns may be regions of the lower substrate 111 that overlap with a plurality of inner plate patterns 121 and a plurality of outer plate patterns 123. The second lower patterns may be regions of the lower substrate 111 that do not overlap with the plurality of inner plate patterns 121 and the plurality of outer plate patterns 123.

[0069] Furthermore, the upper substrate 112 may be defined as including a plurality of first upper patterns and a plurality of second upper patterns. The plurality of first upper patterns may be areas of the upper substrate 112 that overlap with a plurality of inner plate patterns 121 and a plurality of outer plate patterns 123, and the second upper pattern may be areas of the upper substrate 112 that do not overlap with a plurality of inner plate patterns 121 and a plurality of outer plate patterns 123.

[0070] In this case, the elastic modulus of the plurality of first lower patterns and first upper patterns can be greater than that of the second lower patterns and second upper patterns. For example, the plurality of first lower patterns and first upper patterns can be formed of the same material as the plurality of inner plate patterns 121 and the plurality of outer plate patterns 123, and the second lower patterns and second upper patterns can be formed of a material with an elastic modulus lower than that of the plurality of inner plate patterns 121 and the plurality of outer plate patterns 123.

[0071] In other words, the first lower pattern and the first upper pattern can be formed from polyimide (PI), polyacrylate, polyacetate, etc., and the second lower pattern and the second upper pattern can be formed from silicone rubber such as polydimethylsiloxane (PDMS) or elastomers such as polyurethane (PU) and polytetrafluoroethylene (PTFE).

[0072] <Ineffective region drive element>

[0073] A gating driver GD is a component that provides gating voltages to multiple pixels PX disposed in an effective area AA. The gating driver GD includes multiple stages formed on multiple outer plate patterns 123, and each stage of the gating driver GD can be electrically connected to each other via multiple gating connection lines. Therefore, a gating voltage output from one stage can be transferred to another stage. Furthermore, each stage can sequentially provide gating voltages to the multiple pixels PX connected to that stage.

[0074] A power supply PS can be connected to a gating driver GD and provide a gating drive voltage and a gating clock voltage. Furthermore, the power supply PS can be connected to multiple pixels PX and provide a pixel drive voltage to each of the pixels PX. The power supply PS can also be formed on multiple outer board patterns 123. That is, the power supply PS can be formed on multiple outer board patterns 123 adjacent to the gating driver GD. Furthermore, each power supply PS formed on the multiple outer board patterns 123 can be electrically connected to the gating driver GD and the multiple pixels PX. That is, the multiple power supplies PS formed on the multiple outer board patterns 123 can be connected via gating power connection lines and pixel power connection lines. Therefore, each of the multiple power supplies PS can provide a gating drive voltage, a gating clock voltage, and a pixel drive voltage.

[0075] A printed circuit board (PCB) is a component that transmits signals and voltages used to drive the display element from the control unit. Therefore, a PCB can also be called a drive substrate. Control units such as IC chips or circuits can be mounted on the PCB. Furthermore, memory, processors, and the like can be mounted on the PCB. Additionally, the PCB provided in the display device 100 can include stretchable and non-stretchable areas to ensure stretchability. Furthermore, IC chips, circuits, memory, processors, etc., can be mounted on the non-stretchable areas, while lines electrically connected to the IC chips, circuits, memory, and processor can be provided in the stretchable areas.

[0076] The data driver (DD) is a component that provides data voltage to multiple pixels (PX) located in the active area (AA). The data driver (DD) can be configured as an IC chip and is therefore also called a data integrated circuit (D-IC). Furthermore, the data driver (DD) can be mounted on a non-stretchable area of ​​a printed circuit board (PCB). That is, the data driver (DD) can be mounted on the PCB as a chip-on-board (COB). Although in Figure 1 The example shown illustrates a data driver DD mounted as a chip-on-board (COB) assembly, but this disclosure is not limited thereto, and the data driver DD can also be mounted as a chip-on-film (COF), chip-on-glass (COG), or cable-mounted package (TCP) assembly.

[0077] Furthermore, despite Figure 1 The illustration shows a data driver DD configured to correspond to a line of the inner panel pattern 121 located in the active area AA, but this disclosure is not limited thereto. That is, a data driver DD can be configured to correspond to multiple columns of the inner panel pattern 121.

[0078] In the following, a more detailed description of the effective area AA of the display device 100 according to an exemplary embodiment of the present disclosure is incorporated herein by reference. Figure 4 and Figure 5 Furthermore, for ease of explanation, the plurality of inner panel patterns 121 are referred to as a plurality of panel patterns 121, and the plurality of inner line patterns 122 are referred to as a plurality of line patterns 122.

[0079] Figure 4 It is along Figure 2 The cross-sectional view shown is taken by the cutting line IV-IV'.

[0080] Figure 5 It is along Figure 2 The cross-sectional view shown is taken by the cutting line V-V'.

[0081] For ease of explanation, Figures 1 to 3 They were cited together.

[0082] Reference Figure 3 and Figure 4 The plurality of board patterns 121 include a lower board pattern 121a disposed on the lower substrate 111 and an upper board pattern 121b disposed on the lower board pattern 121a. Furthermore, the plurality of line patterns 122 include a lower line pattern 122a disposed on the lower substrate 111 and an upper line pattern 122b disposed on the lower line pattern 122a. That is, the pattern layer 120 may include lower pattern layers 121a and 122a and upper pattern layers 121b and 122b. The lower pattern layers 121a and 122a are disposed on the lower substrate 111 and include a plurality of lower board patterns 121a and a plurality of lower line patterns 122a. The upper pattern layers 121b and 122b are disposed on the lower pattern layers 121a and 122a and include a plurality of upper board patterns 121b and a plurality of upper line patterns 122b.

[0083] Reference Figure 2 and Figure 3Pixels PX, comprising multiple sub-pixels SPX, are disposed on multiple board patterns 121. Furthermore, each of the sub-pixels SPX may include a light-emitting element 170 and pixel circuitry, the pixel circuitry including a driving transistor 160 and a switching transistor 150 for driving the light-emitting element 170. However, the light-emitting element in the sub-pixel SPX is not limited to LEDs and may be an organic light-emitting diode. Additionally, the multiple sub-pixels SPX may include red sub-pixels, green sub-pixels, and blue sub-pixels, but are not limited to these. The colors of the multiple sub-pixels SPX can be changed differently as needed.

[0084] More specifically, such as Figure 3 As shown, the driving transistor 160 and the switching transistor 150 constituting the pixel circuit are disposed on a plurality of lower plate patterns 121a. In addition, the light-emitting element 170 is disposed on a plurality of upper plate patterns 121b.

[0085] Multiple sub-pixels SPX can be connected to multiple stretch lines 181 and 182. That is, multiple sub-pixels SPX can be electrically connected to a first stretch line 181 extending in a first direction X. In addition, multiple sub-pixels SPX can be electrically connected to a second stretch line 182 extending in a second direction Y.

[0086] More specifically, such as Figure 4 As shown, the first stretch line 181 may include a first lower stretch line 181a disposed on the lower stretch pattern 122a and a first upper stretch line 181b disposed on the upper stretch pattern 122b. Furthermore, as... Figure 3 As shown, the second stretch line 182 may include a second lower stretch line 182a disposed on the lower line pattern 122a and a second upper stretch line 182b disposed on the upper line pattern 122b.

[0087] In the following text, reference will be made to Figure 3 Describe in detail the cross-sectional structure of the effective region AA.

[0088] Reference Figure 3 Multiple inorganic insulating layers are disposed on multiple lower plate patterns 121a. For example, the multiple inorganic insulating layers may include a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145. However, this disclosure is not limited thereto. Various inorganic insulating layers may be further disposed on the multiple lower plate patterns 121a. One or more of the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, and passivation layer 145 may be omitted from the multiple lower plate patterns 121a.

[0089] Specifically, a buffer layer 141 is disposed on a plurality of lower plate patterns 121a. The buffer layer 141 is formed on the plurality of lower plate patterns 121a to protect the various components of the display device 100 from the penetration of moisture (H2O), oxygen (O2), etc., from the lower substrate 111 and the outer surfaces of the plurality of lower plate patterns 121a. The buffer layer 141 can be formed of an insulating material. For example, the buffer layer 141 can be formed as a single layer or multiple layers of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), etc. However, depending on the structure or characteristics of the display device 100, the buffer layer 141 may be omitted.

[0090] In this case, the buffer layer 141 may be formed only in the region where the buffer layer 141 overlaps with the plurality of lower plate patterns 121a and the plurality of outer plate patterns 123. As described above, the buffer layer 141 may be formed of an inorganic material. Therefore, when the display device 100 is stretched, the buffer layer 141 may be easily damaged, such as easily breaking. Therefore, the buffer layer 141 may not be formed in the region between the plurality of lower plate patterns 121a and the plurality of outer plate patterns 123. The buffer layer 141 may be patterned into the shape of the plurality of lower plate patterns 121a and the plurality of outer plate patterns 123, and formed only on the upper part of the plurality of lower plate patterns 121a and the plurality of outer plate patterns 123. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the buffer layer 141 is formed only in the area where the buffer layer 141 overlaps with the plurality of lower plate patterns 121a and the plurality of outer plate patterns 123, which are rigid substrates, so that damage to various components of the display device 100 can be prevented even when the display device 100 is deformed (e.g., bent or stretched).

[0091] Reference Figure 3 A switching transistor 150, including a gate 151, an active layer 152, a source 153, and a drain 154, and a driving transistor 160, including a gate 161, an active layer 162, a source 153, and a drain 164, are formed on a buffer layer 141.

[0092] First, refer to Figure 1 The active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 are disposed on the buffer layer 141. For example, each of the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may be formed of an oxide semiconductor. Alternatively, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), organic semiconductors, etc.

[0093] A gate insulating layer 142 is disposed on the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160. The gate insulating layer 142 is configured to electrically insulate the gate 151 of the switching transistor 150 from the active layer 152 of the switching transistor 150, and to electrically insulate the gate 161 of the driving transistor 160 from the active layer 162 of the driving transistor 160. Furthermore, the gate insulating layer 142 may be formed of an insulating material. For example, the gate insulating layer 142 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0094] The gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160 are disposed on the gate insulating layer 142. The gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160 are spaced apart from each other on the gate insulating layer 142. Furthermore, the gate 151 of the switching transistor 150 overlaps with the active layer 152 of the switching transistor 150, and the gate 161 of the driving transistor 160 overlaps with the active layer 162 of the driving transistor 160.

[0095] Each of the gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160 may be formed of any of a variety of metallic materials (e.g., any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, each of the gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160 may be formed of two or more of them in an alloy or multiple layers thereof, but is not limited thereto.

[0096] A first interlayer insulating layer 143 is disposed on the gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160. The first interlayer insulating layer 143 insulates the gate 161 of the driving transistor 160 from the intermediate metal layer IM. The first interlayer insulating layer 143 may also be formed of an inorganic material similar to the buffer layer 141. For example, the first interlayer insulating layer 143 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0097] An intermediate metal layer IM is disposed on the first interlayer insulating layer 143. Furthermore, the intermediate metal layer IM overlaps with the gate 161 of the driving transistor 160. Therefore, a storage capacitor is formed in the region where the intermediate metal layer IM overlaps with the gate 161 of the driving transistor 160. Specifically, the gate 161 of the driving transistor 160, the first interlayer insulating layer 143, and the intermediate metal layer IM form a storage capacitor. However, the location of the intermediate metal layer IM is not limited to this. The intermediate metal layer IM can overlap with another electrode in various ways to form a storage capacitor.

[0098] The intermediate metal layer IM can be formed from any of a variety of metallic materials (e.g., any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the intermediate metal layer IM can be formed from an alloy of two or more of them or from multiple layers thereof, but is not limited thereto.

[0099] A second interlayer insulating layer 144 is disposed on the intermediate metal layer IM. The second interlayer insulating layer 144 insulates the gate 151 of the switching transistor 150 from the source 153 and drain 154 of the switching transistor 150. Furthermore, the second interlayer insulating layer 144 insulates the intermediate metal layer IM from the source and drain 164 of the driving transistor 160. The second interlayer insulating layer 144 may also be formed of an inorganic material similar to the buffer layer 141. For example, the first interlayer insulating layer 143 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0100] The source 153 and drain 154 of the switching transistor 150 are disposed on the second interlayer insulating layer 144. Furthermore, the source and drain 164 of the driving transistor 160 are disposed on the second interlayer insulating layer 144. The source 153 and drain 154 of the switching transistor 150 are configured to be spaced apart from each other on the same layer. Furthermore, although... Figure 1 The source of driving transistor 160 is not illustrated, but it is also positioned on the same layer and spaced apart from its drain 164. In switching transistor 150, source 153 and drain 154 can be electrically connected to active layer 152 to contact it. Similarly, in driving transistor 160, source and drain 164 can be electrically connected to active layer 162 to contact it. Furthermore, the drain 154 of switching transistor 150 can be electrically connected to the gate 161 of driving transistor 160 to contact it via a contact hole.

[0101] The source 153 and drains 154 and 164 can be formed of any of a variety of metallic materials (e.g., any of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the source 153 and drains 154 and 164 can be formed of an alloy of two or more of them or multiple layers thereof, but are not limited thereto.

[0102] Furthermore, in this disclosure, the driving transistor 160 has been described as having a coplanar structure, but various types of transistors having interleaved structures, etc., can also be used. Moreover, in this specification, the transistor can be formed not only in the top gate structure but also in the bottom gate structure.

[0103] The gating pad GP and the data pad DP can be set on the second interlayer insulating layer 144.

[0104] Specifically, refer to Figure 4 The gating pad GP is used to transmit the gating voltage to multiple sub-pixels SPX. The gating pad GP is connected to the first pull-down line 181a via a contact hole. In addition, the gating voltage provided from the first pull-down line 181a can be transmitted from the gating pad GP to the gate 151 of the switching transistor 150 via a line formed on the lower plate pattern 121a.

[0105] Additionally, refer to Figure 3 The data pad DP is used to transfer data voltage to multiple sub-pixels SPX. The data pad DP is connected to the second lower stretch line 182a via a contact hole. In addition, the data voltage provided from the second lower stretch line 182a can be transferred from the data pad DP to the source 153 of the switching transistor 150 via an unstretched line formed on the lower plate pattern 121a.

[0106] although Figure 3 Although not shown, the display device according to an exemplary embodiment of this disclosure may further include voltage pads connected to the upper stretch line via contact holes. These voltage pads are pads used to transfer low-potential voltages or high-potential voltages to a plurality of sub-pixels SPX. Additionally, the low-potential voltage provided from the voltage pads can be transferred to the n-electrode 174 of the light-emitting element 170 via the second connection pad CNT2. Furthermore, the high-potential voltage provided from the voltage pads can be transferred to the source 163 of the driving transistor 160.

[0107] The voltage pad VP, gating pad GP, and data pad DP can be formed from the same material as the source 153 and the drain 154 and 164, but are not limited thereto.

[0108] Reference Figure 3A passivation layer 145 is formed on the switching transistor 150 and the driving transistor 160. The passivation layer 145 covers the switching transistor 150 and the driving transistor 160 to protect them from the penetration of moisture, oxygen, etc. The passivation layer 145 can be formed from an inorganic material and can be formed as a single layer or multiple layers, but is not limited thereto.

[0109] Furthermore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 can be patterned and formed only in the regions where they overlap with the plurality of lower plate patterns 121a. The gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 can also be formed from an inorganic material similar to the buffer layer 141. Therefore, when the display device 100 is stretched, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 can be easily damaged, such as easily broken. Therefore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may not be formed in the regions between the plurality of lower plate patterns 121a, and can be patterned into the shape of the plurality of lower plate patterns 121a and formed only on the upper part of the plurality of lower plate patterns 121a.

[0110] A planarization layer 146 is formed on the passivation layer 145. The planarization layer 146 is used to flatten the upper parts of the switching transistor 150 and the driving transistor 160. The planarization layer 146 can be formed as a single layer or multiple layers, and can be formed of organic materials. Therefore, the planarization layer 146 can also be referred to as an organic insulating layer. For example, the planarization layer 146 can be formed of an acrylic-based organic material, but is not limited thereto.

[0111] Reference Figure 3A planarization layer 146 can be disposed on a plurality of lower plate patterns 121a to cover the upper and side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. Furthermore, the planarization layer 146, together with the plurality of lower plate patterns 121a, surrounds the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. Specifically, the planarization layer 146 can be disposed to cover the upper and side surfaces of the passivation layer 145, the side surfaces of the first interlayer insulating layer 143, the second interlayer insulating layer 144, the side surfaces of the gate insulating layer 142, the side surfaces of the buffer layer 141, and a portion of the upper surfaces of the plurality of lower plate patterns 121a. Therefore, the planarization layer 146 can compensate for the steps between the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144 and the passivation layer 145, and the planarization layer 146 can enhance the adhesion strength between the planarization layer 146 and the second lower stretch line 182a disposed on the side surface of the planarization layer 146.

[0112] Reference Figure 3 The tilt angle of the side surface of the planarization layer 146 can be smaller than that of the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. For example, the side surface of the planarization layer 146 can have a gentler tilt than the side surfaces of the passivation layer 145, the first interlayer insulating layer 143, the second interlayer insulating layer 144, the gate insulating layer 142, and the buffer layer 141. Therefore, the tension lines 181 and 182, which are configured to contact the side surface of the planarization layer 146, are configured to have a gentler tilt. Therefore, when the display device 100 is stretched, the stress generated in the second lower tension line 182a can be reduced. Moreover, cracking in the second lower tension line 182a or peeling of the second lower tension line 182a from the side surface of the planarization layer 146 can be suppressed.

[0113] Reference Figures 2 to 4 Stretch lines 181 and 182 refer to lines that electrically connect multiple pixels on multiple lower plate patterns 121a. Stretch lines 181 and 182 are provided on multiple line patterns 122.

[0114] More specifically, the first lower stretch line 181a and the second lower stretch line 182a can be set on the lower line pattern 122a, and the first upper stretch line 181b and the second upper stretch line 182b can be set on the upper line pattern 122b.

[0115] Additionally, stretch lines 181 and 182 can also extend on multiple line patterns 122 to electrically connect to gate pads GP and data pads DP on multiple lower board patterns 121a. Furthermore, refer to... Figure 2 Line pattern 122 is not set in the area between multiple lower plate patterns 121a where no stretch lines 181 and 182 are set.

[0116] The stretch lines 181 and 182 include a first stretch line 181 and a second stretch line 182. The first stretch line 181 and the second stretch line 182 are disposed between a plurality of lower plate patterns 121a. Specifically, the first stretch line 181 refers to the stretch line 181 or 182 that extends along the X-axis direction between the plurality of lower plate patterns 121a. The second stretch line 182 refers to the stretch line 181 or 182 that extends along the Y-axis direction between the plurality of lower plate patterns 121a.

[0117] More specifically, such as Figure 4 As shown, the first stretch line 181 may include a first lower stretch line 181a disposed on the lower stretch pattern 122a and a first upper stretch line 181b disposed on the upper stretch pattern 122b. Furthermore, as... Figure 3 As shown, the second stretch line 182 may include a second lower stretch line 182a disposed on the lower line pattern 122a and a second upper stretch line 182b disposed on the upper line pattern 122b.

[0118] The drawn wires 181 and 182 may be formed of metallic materials (such as copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo)), or the drawn wires 181 and 182 may have a laminated structure of metallic materials (such as copper / molybdenum-titanium (Cu / MoTi), titanium / aluminum / titanium (Ti / Al / Ti) etc.), but are not limited thereto.

[0119] In the display panel of a general-purpose display device, various lines, such as multiple gate lines and multiple data lines, extend in straight lines and are arranged between multiple sub-pixels, and multiple sub-pixels are connected to a single signal line. Therefore, in the display panel of a general-purpose display device, various lines, such as gate lines, data lines, high-potential voltage lines, reference lines, etc., extend continuously from one side to the other on the substrate of the display panel of the organic light-emitting display device.

[0120] In contrast, in the display device 100 according to an exemplary embodiment of the present disclosure, various lines such as gate lines, data lines, high-potential voltage lines, reference lines, initialization voltage lines, etc., are provided on a plurality of lower plate patterns 121a and a plurality of outer plate patterns 123. These lines are formed as straight lines and are considered to be unstretched lines used in the display panel of a general display device. In the display device 100 according to an exemplary embodiment of the present disclosure, unstretched lines formed as straight lines are provided only on the plurality of lower plate patterns 121a and the plurality of outer plate patterns 123.

[0121] In the display device 100 according to an exemplary embodiment of the present disclosure, pads on two adjacent lower board patterns 121a can be connected by stretch lines 181 and 182. Therefore, stretch lines 181 and 182 electrically connect various pads, such as gate pads GP or data pads DP, to two adjacent lower board patterns 121a. Thus, the display device 100 according to an exemplary embodiment of the present disclosure may include multiple stretch lines 181 and 182 to electrically connect various unstretched lines, such as gate lines, data lines, high-potential voltage lines, reference lines, etc., between multiple lower board patterns 121a. For example, a gate line, as an unstretched line, can be provided on multiple lower board patterns 121a arranged adjacent to each other along a first direction X. Furthermore, a gate pad GP can be provided at both ends of the gate line. In this case, multiple gate pads GP on multiple lower board patterns 121a arranged adjacent to each other in the first direction X can be connected to each other by a first lower stretch line 181a serving as a gate line. Therefore, the gate lines provided on the plurality of lower plate patterns 121a and the first lower pull line 181a provided on the inner line pattern 122 can be used as a single gate line. The aforementioned gate line can be referred to as a scan signal line. In addition, lines extending along the first direction X (such as light-emitting signal lines, low-potential voltage lines, and high-potential voltage lines) that can be included in all the various lines in the display device 100 can also be electrically connected via the first pull line 181 as described above.

[0122] Reference Figure 2 and Figure 4 The first stretched line 181 can connect two unstretched lines or gating pads GP on two adjacent lower plate patterns 121a arranged along the first direction X. Alternatively, the first stretched line 181 can be used as a gating line, a light-emitting signal line, a high-potential voltage line, or a low-potential voltage line, but is not limited thereto. The gating pads GP on the plurality of lower plate patterns 121a arranged along the first direction X can be connected by the first stretched line 181a used as a gating line. A single gating voltage can be transmitted to them.

[0123] In addition, refer to Figure 2 and Figure 3The second stretched line 182 can connect unstretched lines or data pads DP on two adjacent lower board patterns 121a arranged side-by-side along the second direction Y. The second stretched line 182 can be used as a data line, a high-potential voltage line, a low-potential voltage line, or a reference line, but is not limited thereto. Lines on the multiple lower board patterns 121a arranged along the second direction Y can be connected by multiple second stretched lines 182a used as data lines. A single data voltage can be transmitted to them.

[0124] like Figure 4 As shown, the first lower stretch line 181a can contact the upper surface and side surface of the planarization layer 146 provided on the lower pattern 121a. Furthermore, the first lower stretch line 181a can extend to the upper surface of the lower pattern 122a. Additionally, the first upper stretch line 181b can be formed on the upper plate pattern 121b provided on the first lower stretch line 181a. The second lower stretch line 182a can be configured to contact the upper surface and side surface of the planarization layer 146 provided on the lower pattern 121a. Furthermore, the second lower stretch line 182a can extend to the upper surface of the lower pattern 122a. Additionally, the second upper stretch line 182b can be formed on the upper plate pattern 121b provided on the second lower stretch line 182a.

[0125] However, as Figure 5 As shown, it is not necessary to set the rigid pattern in the area where the first tension line 181 and the second tension line 182 are not provided. Therefore, the inner line pattern 122, which is a rigid pattern, is not provided below the first tension line 181 and the second tension line 182.

[0126] At the same time, refer to Figure 3 Upper pattern layers 121b and 122b are formed on the lower stretch lines 181a and 182a and the planarization layer 146. The upper pattern layers 121b and 122b can be disposed on the lower pattern layers 121a and 122a. Furthermore, the upper pattern layers 121b and 122b may include a plurality of upper plate patterns 121b and a plurality of upper line patterns 122b.

[0127] The upper patterned layers 121b and 122b are insulating materials and can be formed from plastic materials with low flexibility, such as polyimide (PI), polyacrylate, polyacetate, etc.

[0128] Therefore, the upper pattern layers 121b and 122b are used to insulate adjacent components. Specifically, multiple upper plate patterns 121b electrically insulate the light emitting element LED from the lower pull lines 181a and 182a, and multiple upper line patterns 122b electrically insulate the upper pull lines 181b and 182b from the lower pull lines 181a and 182a. Thus, the upper pull lines 181b and 182b and the lower pull lines 181a and 182a can transmit different voltages or different signals.

[0129] Additionally, the upper stretch lines 181b and 182b, the embankment 147, and the light-emitting element 170 can be disposed on the upper pattern layers 121b and 122b.

[0130] Specifically, refer to Figure 3 A dam 147 is formed on the first connecting pad CNT1, the upper stretch lines 181b and 182b, and the planarization layer 146. The dam 147 is a component used to distinguish adjacent sub-pixels SPX. The dam 147 is configured to cover at least a portion of the pad PD, the upper stretch lines 181b and 182b, and the planarization layer 146. The dam 147 can be formed of an insulating material. Furthermore, the dam 147 can contain a black material. Because the dam 147 contains a black material, it is used to hide lines visible through the effective area AA. The dam 147 can be formed of, for example, a transparent carbon-based mixture. Specifically, the dam 147 can contain carbon black, but is not limited thereto. The dam 147 can also be formed of a transparent insulating material. Moreover, although the height of the dam 147 is shown as lower than... Figure 3 The height of the light-emitting element 170 is not limited to this, and the height of the embankment 147 can be the same as the height of the light-emitting element 170.

[0131] Reference Figure 3 The light-emitting element 170 is disposed on the first connection pad CNT1 and the second connection pad CNT2. The light-emitting element 170 includes an n-type layer 171, an active layer 172, a p-type layer 173, an n-electrode 174, and a p-electrode 175. The light-emitting element 170 of the display device 100 according to an exemplary embodiment of the present disclosure has a flip-chip structure, wherein the n-electrode 174 and the p-electrode 175 are formed on one of its surfaces.

[0132] The n-type layer 171 can be formed by implanting n-type impurities into gallium nitride (GaN), which has excellent crystallinity. The n-type layer 171 can be disposed on a separate base substrate formed of a light-emitting material.

[0133] An active layer 172 is disposed on the n-type layer 171. The active layer 172 is a light-emitting layer that emits light in the light-emitting element 170, and can be formed of a nitride semiconductor (e.g., indium gallium nitride (InGaN)). A p-type layer 173 is disposed on the active layer 172. The p-type layer 173 can be formed by implanting p-type impurities into gallium nitride (GaN).

[0134] As described above, the light-emitting element 170 according to an exemplary embodiment of this disclosure is manufactured by sequentially laminating an n-type layer 171, an active layer 172, and a p-type layer 173, and then etching predetermined regions of the layers to thereby form an n-electrode 174 and a p-electrode 175. In this case, the predetermined region is the space where the n-electrode 174 and the p-electrode 175 are separated from each other and etched to expose a portion of the n-type layer 171. In other words, the surface of the light-emitting element 170 on which the n-electrode 174 and the p-electrode 175 are disposed may not be flat and may have different height levels.

[0135] In this manner, the n-electrode 174 is disposed in the etched region, and the n-electrode 174 can be formed of a conductive material. Additionally, the p-electrode 175 is disposed in the non-etched region, and the p-electrode 175 can also be formed of a conductive material. For example, the n-electrode 174 is disposed on the n-type layer 171 exposed by the etching process, and the p-electrode 175 is disposed on the p-type layer 173. The p-electrode 175 can be formed of the same material as the n-electrode 174.

[0136] An adhesive layer AD is disposed on the upper surfaces of the first connection pad CNT1 and the second connection pad CNT2, and between the first connection pad CNT1 and the second connection pad CNT2. Therefore, the light-emitting element 170 can be bonded to the first connection pad CNT1 and the second connection pad CNT2. In this case, an n-electrode 174 can be disposed on the second connection pad CNT2, and a p-electrode 175 can be disposed on the first connection pad CNT1.

[0137] The adhesive layer AD can be a conductive adhesive layer formed by dispersing conductive balls in an insulating substrate member. Therefore, when heat or pressure is applied to the adhesive layer AD, the conductive balls are electrically connected to have conductive properties in a portion of the adhesive layer AD to which heat or pressure is applied. Furthermore, areas of the adhesive layer AD not under pressure can have insulating properties. For example, the n-electrode 174 is electrically connected to the second connection pad CNT2 via the adhesive layer AD, and the p-electrode 175 is electrically connected to the first connection pad CNT1 via the adhesive layer AD. After the adhesive layer AD is applied to the upper surfaces of the second connection pad CNT2 and the first connection pad CNT1 by an inkjet method or the like, the light-emitting element 170 can be transferred onto the adhesive layer AD. The light-emitting element 170 can then be pressed and heated, thereby electrically connecting the first connection pad CNT1 to the p-electrode 175 and the second connection pad CNT2 to the n-electrode 174. However, the portion of the adhesive layer AD excluded from the portion between the n electrode 174 and the second connection pad CNT2, and the portion between the p electrode 175 and the first connection pad CNT1, have insulating properties. Simultaneously, the adhesive layer AD can be individually disposed on each of the first connection pad CNT1 and the second connection pad CNT2.

[0138] Furthermore, the first connection pad CNT1 is electrically connected to the drain 164 of the driving transistor 160 and receives the driving voltage from the driving transistor 160 for driving the light-emitting element 170. Although Figure 3 The example illustrates that the first connection pad CNT1 and the drain 164 of the driving transistor 160 are indirectly connected to each other without direct contact, but this disclosure is not limited thereto, and the first connection pad CNT1 and the drain 164 of the driving transistor 160 can be in direct contact. Additionally, a low-potential driving voltage for driving the light-emitting element 170 is applied to the second connection pad CNT2. Therefore, when the display device 100 is turned on, the different voltage levels applied to the first connection pad CNT1 and the second connection pad CNT2 are respectively transmitted to the n-electrode 174 and the p-electrode 175, causing the light-emitting element 170 to emit light.

[0139] The upper substrate 112 is used to support various components disposed below the upper substrate 112. Specifically, the upper substrate 112 can be formed by coating and hardening a material used to form the upper substrate 112 on the lower substrate 111 and the lower plate pattern 121a. Therefore, the upper substrate 112 can be configured to contact the lower substrate 111, the lower plate pattern 121a, the lower line pattern 122a, and the stretch lines 181 and 182.

[0140] The upper substrate 112 can be formed of the same material as the lower substrate 111. For example, the upper substrate 112 can be formed of silicone rubber such as polydimethylsiloxane (PDMS) or elastomers such as polyurethane (PU) and polytetrafluoroethylene (PTFE). Therefore, the upper substrate 112 can be flexible. However, the material of the upper substrate 112 is not limited to this.

[0141] At the same time, although Figure 3 Although not shown, a polarizing layer may also be disposed on the upper substrate 112. The polarizing layer polarizes light incident from outside the display device and reduces the reflection of external light. In addition, other optical films may be disposed on the upper substrate 112 instead of the polarizing layer.

[0142] Additionally, a filler layer 190 may be provided on the entire surface of the lower substrate 111, filling the gaps between components disposed on the upper substrate 112 and the lower substrate 111. The filler layer 190 may be formed of a curable adhesive. Specifically, the material used to form the filler layer 190 is coated on the entire surface of the lower substrate 111 and then cured, such that the filler layer 190 can be disposed between components disposed on the upper substrate 112 and the lower substrate 111. For example, the filler layer 190 may be an optically clear adhesive (OCA) and may include acrylic adhesives, silicone adhesives, and polyurethane adhesives.

[0143] Figure 6 This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0144] For reference, Figure 3 The switching transistor 150 shown can be used with Figure 6 Corresponding to the first transistor T1, Figure 3 The driving transistor 160 shown can be with Figure 6 The driving transistor DT corresponds to, and Figure 3 The light-emitting element 170 shown can be coupled with Figure 6 The corresponding light-emitting element is LED.

[0145] In a display device according to an exemplary embodiment of the present disclosure, each of the sub-pixels includes a light-emitting element LED, a driving transistor DT, a first transistor T1 to a fifth transistor T5, and a storage capacitor Cst.

[0146] The LED emits light by a drive current supplied from the driving transistor DT. The anode of the LED is connected to the fourth transistor T4 and the fifth transistor T5, and the cathode of the LED is connected to a low-potential voltage line to which a low-potential voltage VSS is applied.

[0147] The driving transistor DT controls the driving current applied to the light-emitting element LED according to its gate-source voltage Vgs. In addition, the source of the driving transistor DT is connected to the high potential voltage line applied by the high potential voltage VDD, the gate of the driving transistor DT is connected to the second node N2, and the drain of the driving transistor DT is connected to the third node N3.

[0148] The first transistor T1 applies a data voltage Vdata supplied from the data line to the first node N1. The first transistor T1 includes a source connected to the data line, a drain connected to the first node N1, and a gate connected to a scan signal line that transmits the scan signal SCAN. Therefore, the first transistor T1 applies the data voltage Vdata supplied from the data line to the first node N1 in response to the scan signal SCAN being at a low level (which is an on level). In other words, the first transistor T1 can be a switching transistor that applies any one of a plurality of data voltages Vdata to each of a plurality of pixel circuits according to the scan signal SCAN.

[0149] The second transistor T2 is diode-connected to the gate and drain of the driving transistor DT. The second transistor T2 includes a source connected to a third node N3, which serves as the drain of the driving transistor DT; a drain connected to a second node N2, which serves as the gate of the driving transistor DT; and a gate connected to the scan signal line that transmits the scan signal SCAN. Therefore, the second transistor T2 diode-connects the gate and drain of the driving transistor DT in response to a scan signal SCAN that is at a low level (which is the on level).

[0150] The third transistor T3 applies a reference voltage Vref to the first node N1. The third transistor T3 includes a source connected to a reference line that transmits the reference voltage Vref, a drain connected to the first node N1, and a gate connected to a light-emitting signal line that emits a light-emitting signal EM. Therefore, the third transistor T3 applies the reference voltage Vref to the first node N1 in response to the light-emitting signal EM being at a low level (which is the on level).

[0151] The fourth transistor T4 forms a current path between the driving transistor DT and the light-emitting element LED. The fourth transistor T4 includes a source connected to the third node N3, which serves as the drain of the driving transistor DT; a drain connected to the light-emitting element LED; and a gate connected to the light-emitting signal line that transmits the light-emitting signal EM. Therefore, the fourth transistor T4 can be a light-emitting control transistor that forms a current path between the light-emitting element LED and the drain of the driving transistor DT in response to the light-emitting signal EM.

[0152] The fifth transistor T5 applies a reference voltage Vref to the anode of the LED. The fifth transistor T5 includes a source connected to a reference line transmitting the reference voltage Vref, a drain connected to the anode of the LED, and a gate connected to a scan signal line transmitting the scan signal SCAN. Therefore, the fifth transistor T5 applies the reference voltage Vref to the anode of the LED in response to a scan signal SCAN that is at a low level (on level). The fifth transistor T5 can be an initialization transistor for applying the reference voltage Vref to the anode of the LED.

[0153] The storage capacitor Cst includes a first electrode connected to a first node N1 and a second electrode connected to a second node N2. That is, one electrode of the storage capacitor Cst is connected to the gate of the driving transistor DT, and the other electrode of the storage capacitor Cst is connected to the drain of the first transistor T1.

[0154] Figure 7A This is a view illustrating the arrangement relationship between the lower stretched line and the lower unstretched line of a display device according to an exemplary embodiment of the present disclosure.

[0155] Figure 7B This is a view illustrating the arrangement relationship between the upper stretched line and the upper unstretched line of a display device according to an exemplary embodiment of the present disclosure.

[0156] Figure 7A The relationship between the lower stretched line and the lower unstretched line shown in the figure, and Figure 7B The arrangement of the upper stretched line and the upper unstretched line shown can overlap in a direction that is perpendicular to each other in the XY plane.

[0157] In the following text, for ease of explanation, the light-emitting element 170 will be described as a plurality of light-emitting elements R, G, and B. The data voltage Vdata may include a first data voltage Vdata_R input to the red light-emitting element R, a second data voltage Vdata_G input to the green light-emitting element G, and a third data voltage Vdata_B input to the blue light-emitting element B.

[0158] Reference Figure 7A Multiple unstretched lines 183a are provided on the lower plate pattern 121a. In addition, multiple first stretch lines 181a and multiple second stretch lines 182a are provided on multiple lower line patterns 122a.

[0159] Furthermore, a plurality of corresponding unstretched lower wires 183a may extend in the second direction Y and connect to a plurality of second stretched lower wires 182a. For example, the plurality of unstretched lower wires 183a and the plurality of second stretched lower wires 182a may be integrally formed. Each of the plurality of second stretched lower wires 182a and each of the plurality of unstretched lower wires 183a may be formed of a conductive layer.

[0160] In addition, the scan signal SCAN and the light emission signal EM are applied to multiple first lower pull lines 181a. Therefore, one of the multiple first lower pull lines 181a can be used as a scan signal line to transmit the scan signal SCAN, and another of the multiple first lower pull lines 181a can be used as a light emission signal line to transmit the light emission signal EM. That is to say, the multiple first lower pull lines 181a can be used as gate lines.

[0161] In addition, each of the plurality of first lower drawing lines 181a can be electrically connected to each other through a metal layer disposed below the plurality of first lower drawing lines 181a in the lower plate pattern 121a.

[0162] Additionally, a first data voltage Vdata_R and a second data voltage Vdata_G are applied to multiple second lower pull lines 182a. Therefore, one of the multiple second lower pull lines 182a can be used as a first data line to transmit the first data voltage Vdata_R, and another of the multiple second lower pull lines 182a can be used as a second data line to transmit the second data voltage Vdata_G. In other words, the multiple second lower pull lines 182a can be used as multiple data lines.

[0163] Furthermore, each of the plurality of second lower stretched lines 182a can be electrically connected to each other through each of the plurality of lower unstretched lines 183a disposed on the lower plate pattern 121a. Therefore, the plurality of lower unstretched lines 183a and the plurality of second lower stretched lines 182a can be used as a single unit as a plurality of data lines.

[0164] Reference Figure 7B Multiple unstretched lines 183b are provided on the upper plate pattern 121b. In addition, multiple first stretch lines 181b and multiple second stretch lines 182b are provided on multiple upper line patterns 122b.

[0165] Additionally, multiple corresponding unstretched upper lines 183b may extend in the first direction X and connect to multiple first stretched upper lines 181b. For example, the multiple unstretched upper lines 183b and the multiple first stretched upper lines 181b may be integrally formed. Each of the multiple first stretched upper lines 181b and each of the multiple unstretched upper lines 183b may be formed from a conductive layer.

[0166] Furthermore, a low-potential voltage VSS and a high-potential voltage VDD are applied to multiple first upward-stretched lines 181b. Therefore, any one of the multiple first upward-stretched lines 181b can be used as a low-potential voltage line to transmit the low-potential voltage VSS, and another of the first upward-stretched lines 181b can be used as a high-potential voltage line to transmit the high-potential voltage VDD. In other words, the multiple first upward-stretched lines 181b can be used as voltage lines.

[0167] Furthermore, each of the plurality of first stretched lines 181b can be electrically connected to each other through each of the plurality of unstretched lines 183b disposed on the upper plate pattern 121b. Therefore, the plurality of unstretched lines 183b and the plurality of first stretched lines 181b can be used integrally as high-potential voltage lines and low-potential voltage lines.

[0168] Additionally, a third data voltage Vdata_B and a reference voltage Vref are applied to multiple second upper pull lines 182b. Therefore, any one of the multiple second upper pull lines 182b can be used as a third data line to transmit the third data voltage Vdata_B, and another of the multiple second upper pull lines 182b can be used as a reference line to transmit the reference voltage Vref.

[0169] In addition, each of the plurality of second upper stretch lines 182b can be electrically connected to each other through a metal layer disposed below the plurality of second upper stretch lines 182b in the upper plate pattern 121b.

[0170] In the following text, reference will be made to Figure 3 describe Figure 8 and Figure 9 The cross-sectional view shown. Figure 8 and Figure 9 Examples are shown in the settings. Figure 6 The diagram shows the cross-sectional relationship between the driving transistor DT, the light-emitting control transistor T4, and the light-emitting element between the high-potential voltage line and the low-potential voltage line.

[0171] Figure 8 It is along Figure 7A and Figure 7B The cross-sectional view shown is taken by the cutting line VIII-VIII'.

[0172] Figure 9 It is along Figure 7A and Figure 7B The cross-sectional view shown is taken by the cutting line IX-IX'.

[0173] Specifically, Figure 8 The cross-sectional structure of the light-emitting signal EM being applied to the gate of the light-emitting control transistor and the cross-sectional structure of the high-potential voltage VDD being applied to the source of the driving transistor are illustrated.

[0174] exist Figure 8 In this design, the layer containing the gates of multiple transistors is denoted as the gate layer GAT, and the layer containing the source and drain of multiple transistors is denoted as the source-drain layer SD.

[0175] Reference Figure 8 The first lower pull line 181a is connected to the intermediate metal layer IM through a contact hole. The intermediate metal layer IM is connected to the source-drain layer SD through another contact hole, and the source-drain layer SD is connected to the gate layer GAT through yet another contact hole. Therefore, the light emission signal EM transmitted through the first lower pull line 181a can be applied to the gate of the light emission control transistor.

[0176] Furthermore, referring to Figure 8 The first upper pull line 181b is connected to the intermediate metal layer IM through a contact hole, and the intermediate metal layer IM is connected to the source-drain layer SD through another contact hole. Therefore, the high potential voltage VDD transmitted through the first upper pull line 181b can be applied to the source of the driving transistor.

[0177] Furthermore, referring to Figure 9 The driving transistor 160 and the light-emitting control transistor 160' are electrically connected. Additionally, the light-emitting control transistor 160' and the first connection pad CNT1 can be electrically connected.

[0178] Specifically, the drain 164 of the driving transistor 160 and the source 163' of the light-emitting control transistor 160' can be connected. For example, as Figure 9 As shown, the drain 164 of the driving transistor 160 and the source 163' of the light-emitting control transistor 160' can be integrally formed. In other words, referring to... Figure 6 The drain 164 of the driving transistor 160 and the source 163' of the light-emitting control transistor 160' can be connected to the third node N3.

[0179] Furthermore, the drain 164' of the light-emitting control transistor 160' can be connected to the first connection pad CNT1 via the intermediate metal layer IM. More specifically, the drain 164' of the light-emitting control transistor 160' can be connected to the intermediate metal layer IM via a contact hole, and the intermediate metal layer IM can be connected to the first connection pad CNT1 via another contact hole. In other words, referring to... Figure 6 The drain 164' of the light-emitting control transistor 160' and the first connection pad CNT1 can be connected to the fourth node N4.

[0180] Therefore, based on the voltage applied to the gate 161 of the driving transistor 160, the driving current Ids flowing through the source 163, active layer 162, and drain 164 of the driving transistor 160 is determined. Furthermore, when an on-level light emission signal EM is applied to the gate 161' of the light emission control transistor 160', the driving current Ids is transmitted to the first connection pad CNT1 through the source 163', active layer 162', and drain 164' of the light emission control transistor 160'.

[0181] Therefore, the driving voltage caused by the driving current Ids is applied to the n electrode 174, and the low potential voltage VSS is applied from the upper unstretched line 183b to the p electrode 175, so that the light-emitting element can emit light.

[0182] As described above, a display device according to an exemplary embodiment of the present disclosure may include a plurality of lower lines disposed on a lower pattern layer and a plurality of upper lines disposed on an upper pattern layer.

[0183] Therefore, the lines used to drive the display device do not have to be arranged on only one plane, but can be arranged on multiple planes.

[0184] For example, in a conventional display device, four stretch lines should be provided on only one pattern layer, while in a display device according to an exemplary embodiment of the present disclosure, only two stretch lines are provided on each of two pattern layers, so that a total of four stretch lines can be provided.

[0185] In other words, in a predetermined area based on the upper surface, four tension lines should be provided in a conventional display device, while in a display device according to an exemplary embodiment of the present disclosure, only two tension lines may be provided. Therefore, a larger gap between the tension lines provided in the display device according to an exemplary embodiment of the present disclosure can be ensured. Consequently, when the tension lines are stretched, the probability of damage to the tension lines due to adjacent tension lines is significantly reduced, thereby improving stretching reliability.

[0186] Furthermore, in the display device according to an exemplary embodiment of the present disclosure, upper stretched lines and upper unstretched lines are formed separately, and a high potential voltage and a low potential voltage are applied to them, the high potential voltage and the low potential voltage being constant power supplies.

[0187] In conventional display devices, high-potential voltage lines are formed in the line layers that form gate lines and data lines. As a result, the line resistance of the high-potential voltage lines is relatively increased, causing the difference in high-potential voltage levels between pixels located at the edges of the display panel and pixels located at the center of the display panel to be approximately 1.66V.

[0188] In contrast, in the display device according to the exemplary embodiment of this disclosure, the upper stretched lines and the upper unstretched lines are formed separately and used as high-potential voltage lines. Therefore, the line resistance of the high-potential voltage lines is relatively reduced, such that the difference in the level of the high-potential voltage applied to pixels located at the edge of the display panel and pixels located at the center of the display panel is reduced to approximately 0.75V.

[0189] Therefore, in a display device according to an exemplary embodiment of the present disclosure, the uniformity of the image can be improved by reducing the variation of the high potential voltage supplied to the plurality of pixels.

[0190] Furthermore, in the display device according to an exemplary embodiment of this disclosure, in addition to the high-potential voltage line, the lower-stretched line and the lower-unstretched line can be used only as gating lines and data lines. Therefore, the line resistance of the gating line and data line is relatively reduced, thereby minimizing the signal delay of the gating signal and data voltage.

[0191] In the following, a display device according to another exemplary embodiment of the present disclosure will be described.

[0192] Since the display device according to another exemplary embodiment of the present disclosure differs from the display device according to an exemplary embodiment of the present disclosure only in terms of the lower unstretched line, this will be described.

[0193] The same reference numerals are used for the same components of the display device according to another exemplary embodiment of the present disclosure and the display device according to an exemplary embodiment of the present disclosure.

[0194] Figure 10A This is a view illustrating the arrangement relationship between the lower stretched line and the lower unstretched line of a display device according to another exemplary embodiment of the present disclosure.

[0195] Figure 10B This is a view illustrating the arrangement relationship between the upper stretched line and the upper unstretched line of a display device according to another exemplary embodiment of the present disclosure.

[0196] Figure 10A The relationship between the lower stretched line and the lower unstretched line shown in the figure, and Figure 10B The arrangement of the upper stretched line and the upper unstretched line shown can overlap in a direction where they are perpendicular to each other in the XY plane.

[0197] In the following text, for ease of explanation, the light-emitting element 170 will be described as a plurality of light-emitting elements R, G, and B. The data voltage Vdata may include a first data voltage Vdata_R input to the red light-emitting element R, a second data voltage Vdata_G input to the green light-emitting element G, and a third data voltage Vdata_B input to the blue light-emitting element B.

[0198] Reference Figure 10A Multiple unstretched lines 283a are provided on the lower plate pattern 121a. In addition, multiple first stretch lines 281a and multiple second stretch lines 282a are provided on multiple lower line patterns 122a.

[0199] Furthermore, a plurality of corresponding unstretched lower wires 283a may extend in the first direction X and connect to a plurality of first stretching lower wires 281a. For example, the plurality of unstretched lower wires 283a and the plurality of first stretching lower wires 281a may be integrally formed. Each of the plurality of first stretching lower wires 281a and each of the plurality of unstretched lower wires 283a may be formed of a conductive layer.

[0200] Furthermore, the scan signal SCAN and the light emission signal EM are applied to multiple first lower pull lines 281a. Therefore, one of the multiple first lower pull lines 281a can be used as a scan signal line to transmit the scan signal SCAN, and another of the multiple first lower pull lines 281a can be used as a light emission signal line to transmit the light emission signal EM. In other words, the multiple first lower pull lines 281a can be used as gate lines.

[0201] Furthermore, each of the plurality of first lower drawn lines 281a can be electrically connected to each other through each of the plurality of lower undrawn lines 283a disposed on the lower plate pattern 121a. Therefore, the plurality of lower undrawn lines 283a and the plurality of first lower drawn lines 281a can be used as a single unit as a plurality of gate lines.

[0202] Furthermore, a first data voltage Vdata_R and a second data voltage Vdata_G are applied to a plurality of second lower pull lines 282a. Therefore, one of the plurality of second lower pull lines 282a can be used as a first data line to transmit the first data voltage Vdata_R, and another of the plurality of second lower pull lines 282a can be used as a second data line to transmit the second data voltage Vdata_G. In other words, the plurality of second lower pull lines 282a can serve as multiple data lines.

[0203] In addition, each of the plurality of second lower stretch lines 282a can be electrically connected to each other through a metal layer disposed below the plurality of second lower stretch lines 282a in the lower plate pattern 121a.

[0204] Reference Figure 10B Multiple unstretched lines 283b are provided on the upper plate pattern 121b. In addition, multiple first stretch lines 281b and multiple second stretch lines 282b are provided on multiple upper line patterns 122b.

[0205] Furthermore, a plurality of corresponding unstretched upper lines 283b may extend in the first direction X and connect to a plurality of first stretchable upper lines 281b. For example, the plurality of unstretched upper lines 283b and the plurality of first stretchable upper lines 281b may be integrally formed. Each of the plurality of first stretchable upper lines 281b and each of the plurality of unstretched upper lines 283b may be formed of a conductive layer.

[0206] Furthermore, a low-potential voltage VSS and a high-potential voltage VDD are applied to multiple first upward-stretched lines 281b. Therefore, any one of the multiple first upward-stretched lines 281b can be used as a low-potential voltage line to transmit the low-potential voltage VSS, and another of the first upward-stretched lines 281b can be used as a high-potential voltage line to transmit the high-potential voltage VDD. In other words, the multiple first upward-stretched lines 281b can be used as voltage lines.

[0207] Furthermore, each of the plurality of first stretched lines 281b can be electrically connected to each other through each of the plurality of unstretched lines 283b disposed on the upper plate pattern 121b. Therefore, the plurality of unstretched lines 283b and the plurality of first stretched lines 281b can be used integrally as high-potential voltage lines and low-potential voltage lines.

[0208] Additionally, a third data voltage Vdata_B and a reference voltage Vref are applied to multiple second upper pull lines 282b. Therefore, any one of the multiple second upper pull lines 282b can be used as a third data line to transmit the third data voltage Vdata_B, and another of the multiple second upper pull lines 282b can be used as a reference line to transmit the reference voltage Vref.

[0209] In addition, each of the plurality of second upper stretch lines 282b can be electrically connected to each other through a metal layer disposed below the plurality of second upper stretch lines 282b in the upper plate pattern 121b.

[0210] In the following text, reference will be made to Figure 3 describe Figure 11 and Figure 12 The cross-sectional view shown. Figure 11 and Figure 12 Examples are shown in the settings. Figure 6 The diagram shows the cross-sectional relationship between the driving transistor DT, the light-emitting control transistor T4, and the light-emitting element between the high-potential voltage line and the low-potential voltage line.

[0211] Figure 11 It is along Figure 10A and Figure 10B The cross-sectional view shown is taken by the cutting line XI-XI'.

[0212] Figure 12 It is along Figure 10A and Figure 10B The cross-sectional view shown is taken by the cutting line XII-XII'.

[0213] Specifically, Figure 11 The cross-sectional structure of the light-emitting signal EM being applied to the gate of the light-emitting control transistor and the cross-sectional structure of the high-potential voltage VDD being applied to the source of the driving transistor are illustrated.

[0214] exist Figure 11 In this design, the layer containing the gates of multiple transistors is denoted as the gate layer GAT, and the layer containing the source and drain of multiple transistors is denoted as the source-drain layer SD.

[0215] Reference Figure 11 The first lower pull line 281a is connected to the intermediate metal layer IM through a contact hole. The intermediate metal layer IM is connected to the source-drain layer SD through another contact hole, and the source-drain layer SD is connected to the gate layer GAT through yet another contact hole. Therefore, the light emission signal EM transmitted through the first lower pull line 281a can be applied to the gate of the light emission control transistor.

[0216] Furthermore, referring to Figure 11 The first upper pull line 281b is connected to the intermediate metal layer IM through a contact hole, and the intermediate metal layer IM is connected to the source-drain layer SD through another contact hole. Therefore, the high potential voltage VDD transmitted through the first upper pull line 281b can be applied to the source of the driving transistor.

[0217] Furthermore, referring to Figure 12 The driving transistor 160 and the light-emitting control transistor 160' are electrically connected. Additionally, the light-emitting control transistor 160' and the first connection pad CNT1 can be electrically connected.

[0218] Specifically, the drain 164 of the driving transistor 160 and the source 163' of the light-emitting control transistor 160' can be connected. For example, as Figure 12 As shown, the drain 164 of the driving transistor 160 and the source 163' of the light-emitting control transistor 160' can be integrally formed. In other words, referring to... Figure 6 The drain 164 of the driving transistor 160 and the source 163' of the light-emitting control transistor 160' can be connected to the third node N3.

[0219] Furthermore, the drain 164' of the light-emitting control transistor 160' can be connected to the first connection pad CNT1 via the intermediate metal layer IM. More specifically, the drain 164' of the light-emitting control transistor 160' can be connected to the intermediate metal layer IM via a contact hole, and the intermediate metal layer IM can be connected to the first connection pad CNT1 via another contact hole. In other words, referring to... Figure 6The drain 164' of the light-emitting control transistor 160' and the first connection pad CNT1 can be connected to the fourth node N4.

[0220] Therefore, based on the voltage applied to the gate 161 of the driving transistor 160, the driving current Ids flowing through the source 163, active layer 162, and drain 164 of the driving transistor 160 is determined. Furthermore, when an on-level light emission signal EM is applied to the gate 161' of the light emission control transistor 160', the driving current Ids is transmitted to the first connection pad CNT1 through the source 163', active layer 162', and drain 164' of the light emission control transistor 160'.

[0221] Therefore, the driving voltage caused by the driving current Ids is applied to the n electrode 174, and the low potential voltage VSS is applied from the upper unstretched line 283b to the p electrode 175, so that the light-emitting element can emit light.

[0222] As described above, the display device according to another exemplary embodiment may further include a plurality of lower lines disposed on a lower pattern layer and a plurality of upper lines disposed on an upper pattern layer.

[0223] As described above, the display device according to another exemplary embodiment of the present disclosure can also ensure a larger gap between the tension lines, thereby improving tension reliability.

[0224] Furthermore, in a display device according to another exemplary embodiment of the present disclosure, the uniformity of the image can be improved by reducing the variation of the high potential voltage provided to multiple pixels.

[0225] Furthermore, in a display device according to another exemplary embodiment of the present disclosure, the line resistance of the gating line and the data line is relatively reduced, thereby minimizing the signal delay of the gating signal and the data voltage.

[0226] In the following, a display device according to yet another exemplary embodiment of the present disclosure will be described.

[0227] There are differences between the display device according to another exemplary embodiment of the present disclosure and the display device according to an exemplary embodiment of the present disclosure in terms of the number and shape of the stretched lines and the number and shape of the unstretched lines.

[0228] The same reference numerals are used for the same components of the display device according to yet another exemplary embodiment of the present disclosure and the display device according to an exemplary embodiment of the present disclosure.

[0229] Figure 13A This is a view illustrating the arrangement relationship between the lower stretched line and the lower unstretched line of a display device according to yet another exemplary embodiment of the present disclosure.

[0230] Figure 13B This is a view illustrating the arrangement relationship between the upper stretched line and the upper unstretched line of a display device according to yet another exemplary embodiment of the present disclosure.

[0231] Figure 13A The relationship between the lower stretched line and the lower unstretched line shown in the figure, and Figure 13B The arrangement of the upper stretched line and the upper unstretched line shown can overlap in a direction that is perpendicular to each other in the XY plane.

[0232] In the following text, for ease of explanation, the light-emitting element 170 will be described as a plurality of light-emitting elements R, G, and B. The data voltage Vdata may include a first data voltage Vdata_R input to the red light-emitting element R, a second data voltage Vdata_G input to the green light-emitting element G, and a third data voltage Vdata_B input to the blue light-emitting element B.

[0233] Reference Figure 13A Multiple unstretched lines 383a are provided on the lower plate pattern 321a. In addition, multiple first stretch lines 381a and multiple second stretch lines 382a are provided on multiple lower line patterns 322a.

[0234] Furthermore, a plurality of corresponding unstretched lower wires 383a may extend in the first direction X and connect to a plurality of first stretching lower wires 381a. For example, the plurality of unstretched lower wires 383a and the plurality of first stretching lower wires 381a may be integrally formed. Each of the plurality of first stretching lower wires 381a and each of the plurality of unstretched lower wires 383a may be formed of a conductive layer.

[0235] In addition, multiple scan signals SCAN1 and SCAN2, a high-potential voltage VDD, and a light emission signal EM are applied to multiple first lower pull lines 381a. Therefore, one of the multiple first lower pull lines 381a can be used as a scan signal line to transmit any one of the multiple scan signals SCAN1. Furthermore, another of the multiple first lower pull lines 381a can be used as a scan signal line to transmit another of the multiple scan signals SCAN2. Additionally, yet another of the multiple first lower pull lines 381a can be used as a high-potential voltage line to transmit the high-potential voltage VDD. The remaining one of the multiple first lower pull lines 381a can be used as a light emission signal line to transmit the light emission signal EM. That is, each of the multiple first lower pull lines 381a can be used as a gating line and a high-potential voltage line.

[0236] Furthermore, each of the plurality of first lower drawn lines 381a can be electrically connected to each other through each of the plurality of lower undrawn lines 383a disposed on the lower plate pattern 321a. Therefore, the plurality of lower undrawn lines 383a and the plurality of first lower drawn lines 381a can be used integrally as a gate line and a high-potential voltage line.

[0237] Furthermore, each of the multiple data voltages Vdata_R, Vdata_G, and Vdata_B, and the reference voltage Vref, is applied to multiple second lower pull lines 382a. Therefore, any one of the multiple second lower pull lines 382a can be used as a first data line to transmit the first data voltage Vdata_R. Additionally, another of the multiple second lower pull lines 382a can be used as a second data line to transmit the second data voltage Vdata_G. Furthermore, yet another of the multiple second lower pull lines 382a can be used as a third data line to transmit the third data voltage Vdata_B. Furthermore, the remaining one of the multiple second lower pull lines 382a can be used as a reference line to transmit the reference voltage Vref. In other words, each of the multiple second lower pull lines 382a can be used as both a data line and a reference line.

[0238] In addition, each of the plurality of second lower stretch lines 382a can be electrically connected to each other through a metal layer disposed below the plurality of second lower stretch lines 382a in the lower plate pattern 321a.

[0239] Reference Figure 13B Multiple unstretched lines 383b are provided on the upper plate pattern 321b. In addition, multiple first stretch lines 381b and multiple second stretch lines 382b are provided on multiple upper line patterns 322b.

[0240] Furthermore, a plurality of corresponding unstretched upper lines 383b may extend in the first direction X and connect to a plurality of first stretched upper lines 381b. For example, the plurality of unstretched upper lines 383b and the plurality of first stretched upper lines 381b may be integrally formed. Each of the plurality of first stretched upper lines 381b and each of the plurality of unstretched upper lines 383b may be formed of a conductive layer.

[0241] Furthermore, a low-potential voltage VSS and a high-potential voltage VDD are applied to a plurality of first upward-stretched lines 381b. Therefore, any pair of the plurality of first upward-stretched lines 381b can be used as a low-potential voltage line to transmit the low-potential voltage VSS, and another pair of first upward-stretched lines 381b can be used as a high-potential voltage line to transmit the high-potential voltage VDD. In other words, the plurality of first upward-stretched lines 381b can be used as voltage lines.

[0242] Furthermore, each of the plurality of first stretched lines 381b can be electrically connected to each other through each of the plurality of unstretched lines 383b disposed on the upper plate pattern 321b. Therefore, the plurality of unstretched lines 383b and the plurality of first stretched lines 381b can be used integrally as high-potential voltage lines and low-potential voltage lines.

[0243] In addition, each of the multiple data voltages Vdata_R, Vdata_G, and Vdata_B, and the reference voltage Vref, is applied to the multiple second upper pull lines 382b. Therefore, any one of the multiple second upper pull lines 382b can be used to transmit the first data voltage V. data_R The first data line. Additionally, another of the multiple second pull-up lines 382b can be used to transmit the second data voltage V. data_G The second data line. Additionally, another of the multiple second pull-up lines 382b can be used to transmit the third data voltage V. data_B The third data line. Additionally, the remaining one of the multiple second upward-stretched lines 382b can be used as a reference line to transmit the reference voltage Vref. That is, each of the multiple second upward-stretched lines 382b can be used as both a data line and a reference line.

[0244] In addition, each of the plurality of second upper stretch lines 382b can be electrically connected to each other through a metal layer disposed on the plurality of second upper stretch lines 382b in the upper plate pattern 321b.

[0245] In the following text, reference will be made to Figure 3 describe Figure 14 and Figure 15 The cross-sectional view shown. Figure 14 and Figure 15 Examples are shown in the settings. Figure 6 The diagram shows the cross-sectional relationship between the driving transistor DT, the light-emitting control transistor T4, and the light-emitting element between the high-potential voltage line and the low-potential voltage line.

[0246] Figure 14 It is along Figure 13A and Figure 13B The cross-sectional view shown is taken by the cutting line XIV-XIV'.

[0247] Figure 15 It is along Figure 13A and Figure 13B The cross-sectional view shown is taken by the cutting line XV-XV'.

[0248] Specifically, Figure 14 The cross-sectional structure of the light-emitting signal EM being applied to the gate of the light-emitting control transistor and the cross-sectional structure of the high-potential voltage VDD being applied to the source of the driving transistor are illustrated.

[0249] exist Figure 14 In this design, the layer containing the gates of multiple transistors is denoted as the gate layer GAT, and the layer containing the source and drain of multiple transistors is denoted as the source-drain layer SD.

[0250] Furthermore, referring to Figure 14 The first upper pull line 381b is connected to the first lower pull line 381a through a contact hole, the first lower pull line 381a is connected to the intermediate metal layer IM through a contact hole, and the intermediate metal layer IM is connected to the source-drain layer SD through another contact hole. Therefore, the high potential voltage VDD transmitted through the first upper pull line 381b and the first lower pull line 381a can be applied to the source of the driving transistor.

[0251] Furthermore, referring to Figure 15 The driving transistor 160 and the light-emitting control transistor 160' are electrically connected. Additionally, the light-emitting control transistor 160' and the first connection pad CNT1 can be electrically connected.

[0252] Specifically, the drain 164 of the driving transistor 160 and the source 163' of the light-emitting control transistor 160' can be connected. For example, as Figure 15 As shown, the drain 164 of the driving transistor 160 and the source 163' of the light-emitting control transistor 160' can be integrally formed. In other words, referring to... Figure 6 The drain 164 of the driving transistor 160 and the source 163' of the light-emitting control transistor 160' can be connected to the third node N3.

[0253] Furthermore, the drain 164' of the light-emitting control transistor 160' can be connected to the first connection pad CNT1 via the intermediate metal layer IM. More specifically, the drain 164' of the light-emitting control transistor 160' can be connected to the intermediate metal layer IM via a contact hole, and the intermediate metal layer IM can be connected to the first connection pad CNT1 via another contact hole. In other words, referring to... Figure 6 The drain 164' of the light-emitting control transistor 160' and the first connection pad CNT1 can be connected to the fourth node N4.

[0254] Therefore, based on the voltage applied to the gate 161 of the driving transistor 160, the driving current Ids flowing through the source 163, active layer 162, and drain 164 of the driving transistor 160 is determined. Furthermore, when an on-level light emission signal EM is applied to the gate 161' of the light emission control transistor 160', the driving current Ids is transmitted to the first connection pad CNT1 through the source 163', active layer 162', and drain 164' of the light emission control transistor 160'.

[0255] Therefore, the driving voltage caused by the driving current Ids is applied to the n electrode 174, and the low potential voltage VSS is applied from the upper unstretched line 383b to the p electrode 175, so that the light-emitting element can emit light.

[0256] As described above, the display device according to yet another exemplary embodiment may further include a plurality of lower lines disposed on a lower pattern layer and a plurality of upper lines disposed on an upper pattern layer.

[0257] As described above, in a display device according to yet another exemplary embodiment of the present disclosure, the uniformity of an image can be improved by reducing the variation of high potential voltages supplied to multiple pixels.

[0258] Furthermore, in a display device according to yet another exemplary embodiment of the present disclosure, the line resistance of the gating line and the data line is relatively reduced, thereby minimizing the signal delay of the gating signal and the data voltage.

[0259] Furthermore, in a display device according to yet another exemplary embodiment of the present disclosure, a larger number of stretch lines can be provided compared to the case in the display device according to the exemplary embodiment of the present disclosure. Therefore, in the display device according to yet another exemplary embodiment of the present disclosure, various signals, such as multiple scan signals, can be transmitted.

[0260] Exemplary embodiments of this disclosure can also be described as follows:

[0261] A display device according to an exemplary embodiment of the present disclosure may include: a stretchable lower substrate; a lower pattern layer disposed on the lower substrate and including a plurality of lower plate patterns and a plurality of lower line patterns; a plurality of pixel circuits disposed on each of the plurality of lower plate patterns; a plurality of lower stretch lines disposed on each of the plurality of lower line patterns; an upper pattern layer disposed on the lower pattern layer and including a plurality of upper plate patterns and a plurality of upper line patterns; a plurality of light-emitting elements disposed on each of the plurality of upper plate patterns; and a plurality of upper stretch lines disposed on each of the plurality of upper line patterns, such that uniform power can be provided.

[0262] The display device may also include a plurality of lower unstretched lines disposed on each of a plurality of lower plate patterns and connected to the lower stretching lines; and a plurality of upper unstretched lines disposed on each of a plurality of upper plate patterns and connected to the upper stretching lines.

[0263] The multiple downward stretching lines may include multiple first downward stretching lines extending in a first direction and multiple second downward stretching lines extending in a second direction, and the multiple upward stretching lines may include multiple first upward stretching lines extending in a first direction and multiple second upward stretching lines extending in a second direction.

[0264] Each of the plurality of pixel circuits may include: a driving transistor configured to receive a high-potential voltage to control a driving current applied to the light-emitting element; a switching transistor configured to apply any one of a plurality of data voltages to each of the plurality of pixel circuits according to a scan signal; an initialization transistor configured to apply a reference voltage to the light-emitting element according to the scan signal; and a light-emitting control transistor configured to form a current path between the driving transistor and the light-emitting element according to a light-emitting signal, wherein the plurality of data voltages may include a first data voltage, a second data voltage, and a third data voltage.

[0265] The light-emitting element may include an anode connected to a light-emitting control transistor and a cathode connected to a low-potential voltage line to which a low-potential voltage is applied.

[0266] The driving transistor may include a source connected to a high-potential voltage line to which a high-potential voltage is applied and a drain connected to a light-emitting control transistor. The switching transistor may include a source connected to a data line to which any one of a plurality of data voltages is applied and a gate connected to a scan signal line to which a scan signal is transmitted. The initialization transistor may include a source connected to a reference line to which a reference voltage is applied, a drain connected to the anode of the light-emitting element, and a gate connected to a scan signal line to which a scan signal is transmitted. The light-emitting control transistor may include a source connected to the driving transistor, a drain connected to the light-emitting element, and a gate connected to a light-emitting signal line to which a light-emitting signal is transmitted.

[0267] A scanning signal and a light emission signal can be applied to each of the plurality of first down-pulling lines, and a first data voltage and a second data voltage can be applied to each of the plurality of second down-pulling lines.

[0268] Each of the plurality of unstretched lower wires may extend in a second direction, and a first data voltage and a second data voltage may be applied to each of the plurality of unstretched lower wires.

[0269] Each of the multiple second lower stretched lines and each of the multiple lower unstretched lines can be formed by a conductive layer.

[0270] Each of the plurality of unstretched lower lines may extend in a first direction, and scanning signals and light emission signals may be applied to each of the plurality of unstretched lower lines.

[0271] Each of the plurality of first lower stretched lines and each of the plurality of lower unstretched lines can be formed by a conductive layer.

[0272] A high-potential voltage and a low-potential voltage can be applied to each of the plurality of first upper pull lines, and a third data voltage and a reference voltage can be applied to each of the plurality of second upper pull lines.

[0273] Each of the plurality of unstretched wires may extend in a first direction, and a high potential voltage and a low potential voltage may be applied to each of the plurality of unstretched wires.

[0274] Each of the plurality of first stretched lines and each of the plurality of unstretched lines can be formed by a conductive layer.

[0275] A scan signal, a light emission signal, and a high-potential voltage can be applied to each of the multiple first pull-down lines, and multiple data voltages and reference voltages can be applied to each of the multiple second pull-down lines.

[0276] Each of the plurality of unstretched lower lines may extend in a first direction, and scanning signals and light emission signals may be applied to each of the plurality of unstretched lower lines.

[0277] Each of the plurality of first lower stretched lines and each of the plurality of lower unstretched lines can be formed by a conductive layer.

[0278] A high-potential voltage and a low-potential voltage can be applied to each of the plurality of first upper pull lines, and a plurality of data voltages and a reference voltage can be applied to each of the plurality of second upper pull lines.

[0279] Each of the plurality of unstretched wires may extend in a first direction, and a high potential voltage and a low potential voltage may be applied to each of the plurality of unstretched wires.

[0280] Each of the plurality of first stretched lines and each of the plurality of unstretched lines can be formed by a conductive layer.

[0281] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the scope of their equivalents should be interpreted as falling within the scope of the present disclosure.

[0282] Cross-reference to related applications

[0283] This application claims the benefit and priority of Korean Patent Application No. 10-2021-0193487, filed in Korea on December 30, 2021, the entire contents of which are expressly incorporated herein by reference.

Claims

1. A display device, the display device comprising: A stretchable lower substrate; A lower pattern layer is disposed on the lower substrate and includes a plurality of lower substrate patterns and a plurality of lower line patterns; Multiple pixel circuits are disposed on each of the multiple lower plate patterns; Multiple pull-down lines, wherein the multiple pull-down lines are disposed on each of the multiple pull-down patterns; An upper pattern layer is disposed on the lower pattern layer and includes multiple upper plate patterns and multiple upper line patterns; Multiple light-emitting elements are disposed on each of the multiple upper plate patterns; as well as Multiple upper stretch lines are provided on each of the multiple upper stretch patterns. The plurality of lower stretch lines and the plurality of upper stretch lines are electrically insulated from the plurality of upper plate patterns and the plurality of upper line patterns.

2. The display device according to claim 1, further comprising: Multiple unstretched lines are provided on each of the multiple lower plate patterns and connected to the stretching lines; as well as Multiple unstretched lines are provided on each of the multiple upper plate patterns and connected to the stretching lines.

3. The display device according to claim 2, in, The plurality of downward stretching lines include a plurality of first downward stretching lines extending in a first direction and a plurality of second downward stretching lines extending in a second direction. The plurality of upper stretch lines include a plurality of first upper stretch lines extending in the first direction and a plurality of second upper stretch lines extending in the second direction.

4. The display device according to claim 3, in, Each of the plurality of pixel circuits includes: A driving transistor configured to receive a high potential voltage to control the driving current applied to the light-emitting element; A switching transistor configured to apply any one of a plurality of data voltages to each of the plurality of pixel circuits according to a scan signal; An initialization transistor, configured to apply a reference voltage to the light-emitting element according to the scan signal; and A light-emitting control transistor, configured to form a current path between the driving transistor and the light-emitting element based on a light-emitting signal. The plurality of data voltages includes a first data voltage, a second data voltage, and a third data voltage.

5. The display device according to claim 4, in, The light-emitting element includes an anode connected to the light-emitting control transistor and a cathode connected to a low-potential voltage line, to which a low-potential voltage is applied.

6. The display device according to claim 5, in, The driving transistor includes a source connected to the high-potential voltage line to which the high-potential voltage is applied and a drain connected to the light-emitting control transistor. The switching transistor includes a source connected to a data line applied to any of the plurality of data voltages and a gate connected to a scan signal line that transmits the scan signal. The initialization transistor includes a source connected to a reference line to which the reference voltage is applied, a drain connected to the anode of the light-emitting element, and a gate connected to the scan signal line that transmits the scan signal. The light-emitting control transistor includes a source connected to the driving transistor, a drain connected to the light-emitting element, and a gate connected to the light-emitting signal line that transmits the light-emitting signal.

7. The display device according to claim 5, in, The scanning signal and the light emission signal are applied to each of the plurality of first lower pull lines, and The first data voltage and the second data voltage are applied to each of the plurality of second pull-down lines.

8. The display device according to claim 7, in, Each of the plurality of unstretched lower wires extends in the second direction, and the first data voltage and the second data voltage are applied to each of the plurality of unstretched lower wires.

9. The display device according to claim 7, in, Each of the plurality of second lower drawn lines and each of the plurality of lower undrawn lines is formed by a conductive layer.

10. The display device according to claim 7, in, Each of the plurality of unstretched lower lines extends in the first direction, and the scanning signal and the luminous signal are applied to each of the plurality of unstretched lower lines.

11. The display device according to claim 10, in, Each of the plurality of first lower drawn lines and each of the plurality of lower undrawn lines are formed by a conductive layer.

12. The display device according to claim 5, in, The high-potential voltage and the low-potential voltage are applied to each of the plurality of first upper tension lines, and The third data voltage and the reference voltage are applied to each of the plurality of second upper tension lines.

13. The display device according to claim 12, in, Each of the plurality of unstretched wires extends in the first direction, and the high potential voltage and the low potential voltage are applied to each of the plurality of unstretched wires.

14. The display device according to claim 13, in, Each of the plurality of first stretched lines and each of the plurality of unstretched lines is formed by a conductive layer.

15. The display device according to claim 5, in, The scanning signal, the light emission signal, and the high-potential voltage are applied to each of the plurality of first downward-stretching lines, and The plurality of data voltages and the reference voltage are applied to each of the plurality of second pull-down lines.

16. The display device according to claim 15, in, Each of the plurality of unstretched lower lines extends in the first direction, and the scanning signal and the luminous signal are applied to each of the plurality of unstretched lower lines.

17. The display device according to claim 16, in, Each of the plurality of first lower drawn lines and each of the plurality of lower undrawn lines are formed by a conductive layer.

18. The display device according to claim 5, in, The high-potential voltage and the low-potential voltage are applied to each of the plurality of first upper tension lines, and The plurality of data voltages and the reference voltage are applied to each of the plurality of second upper tension lines.

19. The display device according to claim 18, in, Each of the plurality of unstretched wires extends in the first direction, and the high potential voltage and the low potential voltage are applied to each of the plurality of unstretched wires.

20. The display device according to claim 19, in, Each of the plurality of first stretched lines and each of the plurality of unstretched lines is formed by a conductive layer.

21. The display device according to claim 1, wherein, The plurality of upward-stretching lines are formed separately relative to the gate lines and data lines included in the display device.

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